Document behaviour of .align 0 for ARM targets.
Remove incomplete v5e code from tc-arm.c
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Nick Clifton
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@ -1,3 +1,10 @@
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2000-04-24 Nick Clifton <nickc@cygnus.com>
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* doc/c-arm.texi (ARM Directives): Document behaviour of .align 0.
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* doc/as.texinfo (Align): Include arm and strongarm in list of
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targets that have the second form of the behaviour of the .align
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directive.
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2000-04-24 Mark Klein <mklein@dis.com>
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* obj-som.c: Terminate obj_pseudo_table.
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@ -52,7 +52,6 @@
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#define ARM_HALFWORD 0x00000020 /* allow half word loads */
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#define ARM_THUMB 0x00000040 /* allow BX instruction */
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#define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
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#define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
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/* Architectures are the sum of the base and extensions. */
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#define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
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@ -6748,7 +6747,6 @@ md_parse_option (c, arg)
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switch (*++str)
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{
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case 't': cpu_variant |= ARM_THUMB; break;
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case 'e': cpu_variant |= ARM_EXT_V5E; break;
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case 0: break;
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default:
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as_bad (_("Invalid architecture variant -m%s"), arg);
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@ -3296,7 +3296,8 @@ alignment request in bytes. For example @samp{.align 8} advances
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the location counter until it is a multiple of 8. If the location counter
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is already a multiple of 8, no change is needed.
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For other systems, including the i386 using a.out format, it is the
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For other systems, including the i386 using a.out format, and the arm and
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strongarm, it is the
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number of low-order zero bits the location counter must have after
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advancement. For example @samp{.align 3} advances the location
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counter until it a multiple of 8. If the location counter is already a
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@ -1,4 +1,4 @@
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@c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
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@c Copyright (C) 1996, 1998, 1999, 2000 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ -27,66 +27,86 @@
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@section Options
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@cindex ARM options (none)
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@cindex options for ARM (none)
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@table @code
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@cindex @code{-marm} command line option, ARM
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@item -marm [@var{2}|@var{250}|@var{3}|@var{6}|@var{60}|@var{600}|@var{610}|@var{620}|@var{7}|@var{7m}|@var{7d}|@var{7dm}|@var{7di}|@var{7dmi}|@var{70}|@var{700}|@var{700i}|@var{710}|@var{710c}|@var{7100}|@var{7500}|@var{7500fe}|@var{7tdmi}|@var{8}|@var{810}|@var{9}|@var{9tdmi}|@var{920}|@var{strongarm}|@var{strongarm110}|@var{strongarm1100}]
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@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
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This option specifies the target processor. The assembler will issue an
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor.
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@cindex @code{-marmv} command line option, ARM
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@item -marmv [@var{2}|@var{2a}|@var{3}|@var{3m}|@var{4}|@var{4t}|@var{5}|@var{5t}]
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@item -marmv@code{[2|2a|3|3m|4|4t|5|5t]}
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This option specifies the target architecture. The assembler will issue
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an error message if an attempt is made to assemble an instruction which
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will not execute on the target architecture.
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@cindex @code{-mthumb} command line option, ARM
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@item -mthumb
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This option specifies that only Thumb instructions should be assembled.
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@cindex @code{-mall} command line option, ARM
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@item -mall
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This option specifies that any Arm or Thumb instruction should be assembled.
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@cindex @code{-mfpa} command line option, ARM
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@item -mfpa [@var{10}|@var{11}]
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@item -mfpa @var{[10|11]}
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This option specifies the floating point architecture in use on the
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target processor.
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@cindex @code{-mfpe-old} command line option, ARM
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@item -mfpe-old
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Do not allow the assemble of floating point multiple instructions.
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@cindex @code{-mno-fpu} command line option, ARM
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@item -mno-fpu
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Do not allow the assembly of any floating point instructions.
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@cindex @code{-mthumb-interwork} command line option, ARM
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@item -mthumb-interwork
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This option specifies that the output generated by the assembler should
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be marked as supporting interworking.
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@cindex @code{-mapcs} command line option, ARM
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@item -mapcs [@var{26}|@var{32}]
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@item -mapcs @var{[26|32]}
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This option specifies that the output generated by the assembler should
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be marked as supporting the indicated version of the Arm Procedure.
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Calling Standard.
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@cindex @code{-mapcs-float} command line option, ARM
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@item -mapcs-float
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This indicates the the floating point variant of the APCS should be
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used. In this variant floating point arguments are passed in FP
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registers rather than integer registers.
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@cindex @code{-mapcs-reentrant} command line option, ARM
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@item -mapcs-reentrant
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This indicates that the reentrant variant of the APCS should be used.
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This variant supports position independent code.
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@cindex @code{-EB} command line option, ARM
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @code{-EL} command line option, ARM
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor.
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@cindex @code{-k} command line option, ARM
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@cindex PIC code generation for ARM
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@item -k
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This option enables the generation of PIC (position independent code).
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@cindex @code{-moabi} command line option, ARM
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@item -moabi
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This indicates that the code should be assembled using the old ARM ELF
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conventions, based on a beta release release of the ARM-ELF
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specifications, rather than the default conventions which are based on
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the final release of the ARM-ELF specifications.
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@end table
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@ -143,6 +163,13 @@ The ARM family uses @sc{ieee} floating-point numbers.
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@cindex ARM machine directives
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@table @code
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@cindex @code{align} directive, ARM
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@item .align @var{expression} [, @var{expression}]
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This is the generic @var{.align} directive. For the ARM however if the
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first argument is zero (ie no alignment is needed) the assembler will
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behave as if the argument had been 2 (ie pad to the next four byte
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boundary). This is for compatability with ARM's own assembler.
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@cindex @code{req} directive, ARM
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@item @var{name} .req @var{register name}
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This creates an alias for @var{register name} called @var{name}. For
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@ -153,7 +180,7 @@ example:
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@end smallexample
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@cindex @code{code} directive, ARM
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@item .code [@var{16}|@var{32}]
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@item .code @var{[16|32]}
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This directive selects the instruction set being generated. The value 16
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selects Thumb, with the value 32 selecting ARM.
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