Support the fcmXX zero instructions.
sim/aarch64/ * simulator.c (do_scalar_FCMGE_zero): New. (do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero) (do_scalar_FCMLT_zero): Likewise. (do_scalar_vec): Add calls to new functions. sim/testsuite/sim/aarch64/ * fcmXX.s: New.
This commit is contained in:
Jim Wilson
parent
aebcde5eb4
commit
ae27d3fe76
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@ -1,3 +1,9 @@
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2017-04-08 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
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do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
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(do_scalar_vec): Add calls to new functions.
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2017-03-25 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
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@ -8926,6 +8926,146 @@ do_scalar_SSHL (sim_cpu *cpu)
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aarch64_get_vec_s64 (cpu, rn, 0) >> - shift);
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}
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/* Floating point scalar compare greater than or equal to 0. */
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static void
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do_scalar_FCMGE_zero (sim_cpu *cpu)
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{
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/* instr [31,23] = 0111 1110 1
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instr [22,22] = size
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instr [21,16] = 1000 00
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instr [15,10] = 1100 10
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instr [9, 5] = Rn
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instr [4, 0] = Rd. */
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unsigned size = INSTR (22, 22);
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unsigned rn = INSTR (9, 5);
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unsigned rd = INSTR (4, 0);
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NYI_assert (31, 23, 0x0FD);
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NYI_assert (21, 16, 0x20);
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NYI_assert (15, 10, 0x32);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (size)
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aarch64_set_vec_u64 (cpu, rd, 0,
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aarch64_get_vec_double (cpu, rn, 0) >= 0.0 ? -1 : 0);
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else
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aarch64_set_vec_u32 (cpu, rd, 0,
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aarch64_get_vec_float (cpu, rn, 0) >= 0.0 ? -1 : 0);
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}
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/* Floating point scalar compare less than or equal to 0. */
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static void
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do_scalar_FCMLE_zero (sim_cpu *cpu)
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{
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/* instr [31,23] = 0111 1110 1
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instr [22,22] = size
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instr [21,16] = 1000 00
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instr [15,10] = 1101 10
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instr [9, 5] = Rn
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instr [4, 0] = Rd. */
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unsigned size = INSTR (22, 22);
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unsigned rn = INSTR (9, 5);
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unsigned rd = INSTR (4, 0);
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NYI_assert (31, 23, 0x0FD);
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NYI_assert (21, 16, 0x20);
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NYI_assert (15, 10, 0x36);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (size)
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aarch64_set_vec_u64 (cpu, rd, 0,
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aarch64_get_vec_double (cpu, rn, 0) <= 0.0 ? -1 : 0);
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else
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aarch64_set_vec_u32 (cpu, rd, 0,
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aarch64_get_vec_float (cpu, rn, 0) <= 0.0 ? -1 : 0);
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}
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/* Floating point scalar compare greater than 0. */
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static void
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do_scalar_FCMGT_zero (sim_cpu *cpu)
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{
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/* instr [31,23] = 0101 1110 1
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instr [22,22] = size
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instr [21,16] = 1000 00
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instr [15,10] = 1100 10
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instr [9, 5] = Rn
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instr [4, 0] = Rd. */
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unsigned size = INSTR (22, 22);
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unsigned rn = INSTR (9, 5);
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unsigned rd = INSTR (4, 0);
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NYI_assert (31, 23, 0x0BD);
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NYI_assert (21, 16, 0x20);
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NYI_assert (15, 10, 0x32);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (size)
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aarch64_set_vec_u64 (cpu, rd, 0,
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aarch64_get_vec_double (cpu, rn, 0) > 0.0 ? -1 : 0);
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else
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aarch64_set_vec_u32 (cpu, rd, 0,
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aarch64_get_vec_float (cpu, rn, 0) > 0.0 ? -1 : 0);
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}
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/* Floating point scalar compare equal to 0. */
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static void
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do_scalar_FCMEQ_zero (sim_cpu *cpu)
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{
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/* instr [31,23] = 0101 1110 1
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instr [22,22] = size
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instr [21,16] = 1000 00
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instr [15,10] = 1101 10
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instr [9, 5] = Rn
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instr [4, 0] = Rd. */
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unsigned size = INSTR (22, 22);
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unsigned rn = INSTR (9, 5);
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unsigned rd = INSTR (4, 0);
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NYI_assert (31, 23, 0x0BD);
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NYI_assert (21, 16, 0x20);
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NYI_assert (15, 10, 0x36);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (size)
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aarch64_set_vec_u64 (cpu, rd, 0,
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aarch64_get_vec_double (cpu, rn, 0) == 0.0 ? -1 : 0);
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else
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aarch64_set_vec_u32 (cpu, rd, 0,
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aarch64_get_vec_float (cpu, rn, 0) == 0.0 ? -1 : 0);
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}
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/* Floating point scalar compare less than 0. */
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static void
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do_scalar_FCMLT_zero (sim_cpu *cpu)
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{
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/* instr [31,23] = 0101 1110 1
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instr [22,22] = size
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instr [21,16] = 1000 00
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instr [15,10] = 1110 10
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instr [9, 5] = Rn
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instr [4, 0] = Rd. */
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unsigned size = INSTR (22, 22);
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unsigned rn = INSTR (9, 5);
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unsigned rd = INSTR (4, 0);
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NYI_assert (31, 23, 0x0BD);
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NYI_assert (21, 16, 0x20);
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NYI_assert (15, 10, 0x3A);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (size)
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aarch64_set_vec_u64 (cpu, rd, 0,
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aarch64_get_vec_double (cpu, rn, 0) < 0.0 ? -1 : 0);
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else
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aarch64_set_vec_u32 (cpu, rd, 0,
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aarch64_get_vec_float (cpu, rn, 0) < 0.0 ? -1 : 0);
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}
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static void
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do_scalar_shift (sim_cpu *cpu)
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{
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@ -9249,7 +9389,9 @@ do_scalar_vec (sim_cpu *cpu)
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case 0x0D: do_scalar_CMGT (cpu); return;
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case 0x11: do_scalar_USHL (cpu); return;
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case 0x2E: do_scalar_NEG (cpu); return;
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case 0x32: do_scalar_FCMGE_zero (cpu); return;
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case 0x35: do_scalar_FABD (cpu); return;
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case 0x36: do_scalar_FCMLE_zero (cpu); return;
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case 0x39: do_scalar_FCM (cpu); return;
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case 0x3B: do_scalar_FCM (cpu); return;
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default:
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@ -9263,6 +9405,9 @@ do_scalar_vec (sim_cpu *cpu)
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{
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case 0x21: do_double_add (cpu); return;
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case 0x11: do_scalar_SSHL (cpu); return;
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case 0x32: do_scalar_FCMGT_zero (cpu); return;
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case 0x36: do_scalar_FCMEQ_zero (cpu); return;
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case 0x3A: do_scalar_FCMLT_zero (cpu); return;
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default:
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HALT_NYI;
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}
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@ -1,3 +1,7 @@
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2017-04-08 Jim Wilson <jim.wilson@linaro.org>
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* fcmXX.s: New.
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2017-03-25 Jim Wilson <jim.wilson@linaro.org>
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* adds.s: Add checks for values -2 and 1, where C is not set.
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@ -0,0 +1,77 @@
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# mach: aarch64
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# Check the FP scalar compare zero instructions: fcmeq, fcmle, fcmlt, fcmge,
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# fcmgt.
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# Check values -1, 0, and 1.
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.include "testutils.inc"
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start
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fmov s0, wzr
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fcmeq s1, s0, #0.0
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mov w0, v1.s[0]
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cmp w0, #-1
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bne .Lfailure
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fmov s0, #-1.0
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fcmeq s1, s0, #0.0
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mov w0, v1.s[0]
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cmp w0, #0
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bne .Lfailure
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fmov d0, xzr
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fcmeq d1, d0, #0.0
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mov x0, v1.d[0]
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cmp x0, #-1
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bne .Lfailure
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fmov d0, #1.0
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fcmeq d1, d0, #0.0
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mov x0, v1.d[0]
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cmp x0, #0
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bne .Lfailure
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fmov s0, #-1.0
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fcmle s1, s0, #0.0
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mov w0, v1.s[0]
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cmp w0, #-1
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bne .Lfailure
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fmov d0, #-1.0
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fcmle d1, d0, #0.0
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mov x0, v1.d[0]
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cmp x0, #-1
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bne .Lfailure
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fmov s0, #-1.0
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fcmlt s1, s0, #0.0
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mov w0, v1.s[0]
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cmp w0, #-1
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bne .Lfailure
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fmov d0, #-1.0
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fcmlt d1, d0, #0.0
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mov x0, v1.d[0]
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cmp x0, #-1
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bne .Lfailure
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fmov s0, #1.0
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fcmge s1, s0, #0.0
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mov w0, v1.s[0]
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cmp w0, #-1
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bne .Lfailure
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fmov d0, #1.0
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fcmge d1, d0, #0.0
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mov x0, v1.d[0]
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cmp x0, #-1
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bne .Lfailure
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fmov s0, #1.0
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fcmgt s1, s0, #0.0
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mov w0, v1.s[0]
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cmp w0, #-1
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bne .Lfailure
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fmov d0, #1.0
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fcmgt d1, d0, #0.0
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mov x0, v1.d[0]
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cmp x0, #-1
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bne .Lfailure
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pass
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.Lfailure:
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fail
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