aarch64: allow adding/removing just feature flags via .arch_extension
Rather than requiring to always also set/change the base architecture, allow just en-/disabling of architecture extensions, matching what ARM has.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
0a9ce86daf
commit
ae527cd876
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@ -1,3 +1,12 @@
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2014-11-18 Jan Beulich <jbeulich@suse.com>
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* config/tc-aarch64.c (s_aarch64_arch_extension): New.
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(md_pseudo_table): Add arch_extension.
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(aarch64_parse_features): New parameter "ext_only". Handle it.
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(aarch64_parse_cpu, aarch64_parse_arch, s_aarch64_cpu,
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s_aarch64_arch): Pass FALSE as new third argument of
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aarch64_parse_features().
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2014-11-17 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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* config/tc-aarch64.c (aarch64_cpus): Add "xgene2".
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@ -1917,6 +1917,7 @@ s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
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static void s_aarch64_arch (int);
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static void s_aarch64_cpu (int);
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static void s_aarch64_arch_extension (int);
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/* This table describes all the machine specific pseudo-ops the assembler
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has to support. The fields are:
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@ -1934,6 +1935,7 @@ const pseudo_typeS md_pseudo_table[] = {
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{"pool", s_ltorg, 0},
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{"cpu", s_aarch64_cpu, 0},
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{"arch", s_aarch64_arch, 0},
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{"arch_extension", s_aarch64_arch_extension, 0},
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{"inst", s_aarch64_inst, 0},
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#ifdef OBJ_ELF
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{"tlsdesccall", s_tlsdesccall, 0},
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@ -7238,7 +7240,8 @@ struct aarch64_long_option_table
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};
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static int
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aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
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aarch64_parse_features (char *str, const aarch64_feature_set **opt_p,
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bfd_boolean ext_only)
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{
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/* We insist on extensions being added before being removed. We achieve
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this by using the ADDING_VALUE variable to indicate whether we are
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@ -7254,17 +7257,19 @@ aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
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while (str != NULL && *str != 0)
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{
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const struct aarch64_option_cpu_value_table *opt;
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char *ext;
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char *ext = NULL;
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int optlen;
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if (*str != '+')
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if (!ext_only)
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{
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as_bad (_("invalid architectural extension"));
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return 0;
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}
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if (*str != '+')
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{
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as_bad (_("invalid architectural extension"));
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return 0;
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}
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str++;
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ext = strchr (str, '+');
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ext = strchr (++str, '+');
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}
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if (ext != NULL)
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optlen = ext - str;
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@ -7344,7 +7349,7 @@ aarch64_parse_cpu (char *str)
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{
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mcpu_cpu_opt = &opt->value;
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if (ext != NULL)
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return aarch64_parse_features (ext, &mcpu_cpu_opt);
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return aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE);
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return 1;
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}
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@ -7376,7 +7381,7 @@ aarch64_parse_arch (char *str)
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{
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march_cpu_opt = &opt->value;
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if (ext != NULL)
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return aarch64_parse_features (ext, &march_cpu_opt);
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return aarch64_parse_features (ext, &march_cpu_opt, FALSE);
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return 1;
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}
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@ -7559,7 +7564,7 @@ s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
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{
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mcpu_cpu_opt = &opt->value;
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if (ext != NULL)
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if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
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if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
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return;
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cpu_variant = *mcpu_cpu_opt;
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@ -7605,7 +7610,7 @@ s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
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{
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mcpu_cpu_opt = &opt->value;
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if (ext != NULL)
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if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
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if (!aarch64_parse_features (ext, &mcpu_cpu_opt, FALSE))
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return;
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cpu_variant = *mcpu_cpu_opt;
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@ -7620,6 +7625,28 @@ s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
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ignore_rest_of_line ();
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}
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/* Parse a .arch_extension directive. */
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static void
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s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED)
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{
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char saved_char;
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char *ext = input_line_pointer;;
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while (*input_line_pointer && !ISSPACE (*input_line_pointer))
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input_line_pointer++;
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saved_char = *input_line_pointer;
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*input_line_pointer = 0;
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if (!aarch64_parse_features (ext, &mcpu_cpu_opt, TRUE))
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return;
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cpu_variant = *mcpu_cpu_opt;
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*input_line_pointer = saved_char;
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demand_empty_rest_of_line ();
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}
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/* Copy symbol information. */
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void
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@ -1,3 +1,10 @@
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2014-11-18 Jan Beulich <jbeulich@suse.com>
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* gas/aarch64/crc32-directive.d: New.
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* gas/aarch64/crypto-directive.d: New.
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* gas/aarch64/crc32.s: Adjust to allow for directive use.
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* gas/aarch64/crypto.s: Likewise.
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* gas/i386/i386.exp: Run new tests.
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@ -0,0 +1,17 @@
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#objdump: -dr
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#as: --defsym DIRECTIVE=1
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#source: crc32.s
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.*>:
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0: 1acf40e3 crc32b w3, w7, w15
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4: 1ac345e7 crc32h w7, w15, w3
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8: 1ac7486f crc32w w15, w3, w7
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c: 9acf4ce3 crc32x w3, w7, x15
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10: 1acf50e3 crc32cb w3, w7, w15
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14: 1ac355e7 crc32ch w7, w15, w3
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18: 1ac7586f crc32cw w15, w3, w7
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1c: 9acf5ce3 crc32cx w3, w7, x15
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@ -21,6 +21,10 @@
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.text
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.ifdef DIRECTIVE
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.arch_extension crc
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.endif
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crc32b w3, w7, w15
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crc32h w7, w15, w3
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crc32w w15, w3, w7
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@ -29,3 +33,5 @@
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crc32ch w7, w15, w3
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crc32cw w15, w3, w7
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crc32cx w3, w7, x15
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.arch_extension nocrc
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@ -0,0 +1,27 @@
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#objdump: -dr
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#as: --defsym DIRECTIVE=1
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#source: crypto.s
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.*>:
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0: 4e284be7 aese v7.16b, v31.16b
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4: 4e285be7 aesd v7.16b, v31.16b
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8: 4e286be7 aesmc v7.16b, v31.16b
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c: 4e287be7 aesimc v7.16b, v31.16b
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10: 5e280be7 sha1h s7, s31
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14: 5e281be7 sha1su1 v7.4s, v31.4s
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18: 5e282be7 sha256su0 v7.4s, v31.4s
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1c: 5e1f01e7 sha1c q7, s15, v31.4s
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20: 5e1f11e7 sha1p q7, s15, v31.4s
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24: 5e1f21e7 sha1m q7, s15, v31.4s
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28: 5e1f31e7 sha1su0 v7.4s, v15.4s, v31.4s
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2c: 5e1f41e7 sha256h q7, q15, v31.4s
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30: 5e1f51e7 sha256h2 q7, q15, v31.4s
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34: 5e1f61e7 sha256su1 v7.4s, v15.4s, v31.4s
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38: 0e3fe1e7 pmull v7.8h, v15.8b, v31.8b
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3c: 0effe1e7 pmull v7.1q, v15.1d, v31.1d
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40: 4e3fe1e7 pmull2 v7.8h, v15.16b, v31.16b
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44: 4effe1e7 pmull2 v7.1q, v15.2d, v31.2d
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@ -20,6 +20,10 @@
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.text
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.ifdef DIRECTIVE
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.arch_extension crypto
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.endif
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aese v7.16b, v31.16b
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aesd v7.16b, v31.16b
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aesmc v7.16b, v31.16b
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@ -42,3 +46,5 @@
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pmull v7.1q, v15.1d, v31.1d
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pmull2 v7.8h, v15.16b, v31.16b
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pmull2 v7.1q, v15.2d, v31.2d
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.arch_extension nocrypto
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