i386: Generate lfence with load/indirect branch/ret [CVE-2020-0551]
Add 3 command-line options to generate lfence for load, indirect near branch and ret to help mitigate: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551 1. -mlfence-after-load=[no|yes]: -mlfence-after-load=yes generates lfence after load instructions. 2. -mlfence-before-indirect-branch=[none|all|memory|register]: a. -mlfence-before-indirect-branch=all generates lfence before indirect near branches via register and a warning before indirect near branches via memory. b. -mlfence-before-indirect-branch=memory issue a warning before indirect near branches via memory. c. -mlfence-before-indirect-branch=register generates lfence before indirect near branches via register. Note that lfence won't be generated before indirect near branches via register with -mlfence-after-load=yes since lfence will be generated after loading branch target register. 3. -mlfence-before-ret=[none|or|not] a. -mlfence-before-ret=or generates or with lfence before ret. b. -mlfence-before-ret=not generates not with lfence before ret. A warning will be issued and lfence won't be generated before indirect near branch and ret if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. * config/tc-i386.c (lfence_after_load): New. (lfence_before_indirect_branch_kind): New. (lfence_before_indirect_branch): New. (lfence_before_ret_kind): New. (lfence_before_ret): New. (last_insn): New. (load_insn_p): New. (insert_lfence_after): New. (insert_lfence_before): New. (md_assemble): Call insert_lfence_before and insert_lfence_after. Set last_insn. (OPTION_MLFENCE_AFTER_LOAD): New. (OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New. (OPTION_MLFENCE_BEFORE_RET): New. (md_longopts): Add -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. (md_parse_option): Handle -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. (md_show_usage): Display -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. * doc/c-i386.texi: Document -mlfence-after-load=, -mlfence-before-indirect-branch= and -mlfence-before-ret=.
This commit is contained in:
H.J. Lu
parent
5a13315d1c
commit
ae531041c7
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@ -1,3 +1,31 @@
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2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (lfence_after_load): New.
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(lfence_before_indirect_branch_kind): New.
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(lfence_before_indirect_branch): New.
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(lfence_before_ret_kind): New.
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(lfence_before_ret): New.
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(last_insn): New.
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(load_insn_p): New.
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(insert_lfence_after): New.
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(insert_lfence_before): New.
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(md_assemble): Call insert_lfence_before and insert_lfence_after.
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Set last_insn.
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(OPTION_MLFENCE_AFTER_LOAD): New.
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(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
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(OPTION_MLFENCE_BEFORE_RET): New.
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(md_longopts): Add -mlfence-after-load=,
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-mlfence-before-indirect-branch= and -mlfence-before-ret=.
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(md_parse_option): Handle -mlfence-after-load=,
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-mlfence-before-indirect-branch= and -mlfence-before-ret=.
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(md_show_usage): Display -mlfence-after-load=,
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-mlfence-before-indirect-branch= and -mlfence-before-ret=.
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(i386_cons_align): New.
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* config/tc-i386.h (i386_cons_align): New.
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(md_cons_align): New.
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* doc/c-i386.texi: Document -mlfence-after-load=,
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-mlfence-before-indirect-branch= and -mlfence-before-ret=.
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2020-03-11 Nick Clifton <nickc@redhat.com>
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PR 25611
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@ -629,7 +629,29 @@ static int omit_lock_prefix = 0;
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"lock addl $0, (%{re}sp)". */
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static int avoid_fence = 0;
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/* Type of the previous instruction. */
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/* 1 if lfence should be inserted after every load. */
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static int lfence_after_load = 0;
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/* Non-zero if lfence should be inserted before indirect branch. */
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static enum lfence_before_indirect_branch_kind
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{
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lfence_branch_none = 0,
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lfence_branch_register,
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lfence_branch_memory,
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lfence_branch_all
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}
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lfence_before_indirect_branch;
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/* Non-zero if lfence should be inserted before ret. */
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static enum lfence_before_ret_kind
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{
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lfence_before_ret_none = 0,
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lfence_before_ret_not,
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lfence_before_ret_or
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}
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lfence_before_ret;
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/* Types of previous instruction is .byte or prefix. */
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static struct
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{
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segT seg;
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@ -4311,6 +4333,283 @@ optimize_encoding (void)
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}
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}
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/* Return non-zero for load instruction. */
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static int
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load_insn_p (void)
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{
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unsigned int dest;
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int any_vex_p = is_any_vex_encoding (&i.tm);
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unsigned int base_opcode = i.tm.base_opcode | 1;
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if (!any_vex_p)
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{
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/* lea */
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if (i.tm.base_opcode == 0x8d)
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return 0;
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/* pop */
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if ((i.tm.base_opcode & ~7) == 0x58
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|| (i.tm.base_opcode == 0x8f && i.tm.extension_opcode == 0))
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return 1;
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/* movs, cmps, lods, scas. */
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if ((i.tm.base_opcode | 0xb) == 0xaf)
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return 1;
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/* outs */
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if (base_opcode == 0x6f)
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return 1;
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}
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/* No memory operand. */
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if (!i.mem_operands)
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return 0;
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if (any_vex_p)
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{
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/* vldmxcsr. */
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if (i.tm.base_opcode == 0xae
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&& i.tm.opcode_modifier.vex
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&& i.tm.opcode_modifier.vexopcode == VEX0F
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&& i.tm.extension_opcode == 2)
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return 1;
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}
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else
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{
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/* test, not, neg, mul, imul, div, idiv. */
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if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7)
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&& i.tm.extension_opcode != 1)
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return 1;
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/* inc, dec. */
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if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
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return 1;
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/* add, or, adc, sbb, and, sub, xor, cmp. */
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if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
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return 1;
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/* bt, bts, btr, btc. */
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if (i.tm.base_opcode == 0xfba
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&& (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7))
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return 1;
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/* rol, ror, rcl, rcr, shl/sal, shr, sar. */
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if ((base_opcode == 0xc1
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|| (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3))
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&& i.tm.extension_opcode != 6)
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return 1;
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/* cmpxchg8b, cmpxchg16b, xrstors. */
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if (i.tm.base_opcode == 0xfc7
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&& (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3))
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return 1;
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/* fxrstor, ldmxcsr, xrstor. */
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if (i.tm.base_opcode == 0xfae
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&& (i.tm.extension_opcode == 1
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|| i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 5))
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return 1;
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/* lgdt, lidt, lmsw. */
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if (i.tm.base_opcode == 0xf01
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&& (i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6))
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return 1;
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/* vmptrld */
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if (i.tm.base_opcode == 0xfc7
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&& i.tm.extension_opcode == 6)
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return 1;
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/* Check for x87 instructions. */
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if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf)
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{
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/* Skip fst, fstp, fstenv, fstcw. */
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if (i.tm.base_opcode == 0xd9
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&& (i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6
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|| i.tm.extension_opcode == 7))
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return 0;
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/* Skip fisttp, fist, fistp, fstp. */
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if (i.tm.base_opcode == 0xdb
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&& (i.tm.extension_opcode == 1
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|| i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 7))
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return 0;
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/* Skip fisttp, fst, fstp, fsave, fstsw. */
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if (i.tm.base_opcode == 0xdd
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&& (i.tm.extension_opcode == 1
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|| i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6
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|| i.tm.extension_opcode == 7))
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return 0;
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/* Skip fisttp, fist, fistp, fbstp, fistp. */
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if (i.tm.base_opcode == 0xdf
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&& (i.tm.extension_opcode == 1
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|| i.tm.extension_opcode == 2
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|| i.tm.extension_opcode == 3
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|| i.tm.extension_opcode == 6
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|| i.tm.extension_opcode == 7))
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return 0;
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return 1;
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}
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}
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dest = i.operands - 1;
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/* Check fake imm8 operand and 3 source operands. */
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if ((i.tm.opcode_modifier.immext
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|| i.tm.opcode_modifier.vexsources == VEX3SOURCES)
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&& i.types[dest].bitfield.imm8)
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dest--;
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/* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
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if (!any_vex_p
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&& (base_opcode == 0x1
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|| base_opcode == 0x9
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|| base_opcode == 0x11
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|| base_opcode == 0x19
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|| base_opcode == 0x21
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|| base_opcode == 0x29
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|| base_opcode == 0x31
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|| base_opcode == 0x39
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|| (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87)
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|| base_opcode == 0xfc1))
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return 1;
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/* Check for load instruction. */
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return (i.types[dest].bitfield.class != ClassNone
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|| i.types[dest].bitfield.instance == Accum);
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}
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/* Output lfence, 0xfaee8, after instruction. */
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static void
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insert_lfence_after (void)
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{
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if (lfence_after_load && load_insn_p ())
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{
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char *p = frag_more (3);
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*p++ = 0xf;
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*p++ = 0xae;
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*p = 0xe8;
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}
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}
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/* Output lfence, 0xfaee8, before instruction. */
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static void
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insert_lfence_before (void)
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{
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char *p;
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if (is_any_vex_encoding (&i.tm))
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return;
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if (i.tm.base_opcode == 0xff
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&& (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
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{
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/* Insert lfence before indirect branch if needed. */
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if (lfence_before_indirect_branch == lfence_branch_none)
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return;
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if (i.operands != 1)
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abort ();
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if (i.reg_operands == 1)
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{
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/* Indirect branch via register. Don't insert lfence with
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-mlfence-after-load=yes. */
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if (lfence_after_load
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|| lfence_before_indirect_branch == lfence_branch_memory)
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return;
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}
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else if (i.mem_operands == 1
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&& lfence_before_indirect_branch != lfence_branch_register)
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{
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as_warn (_("indirect `%s` with memory operand should be avoided"),
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i.tm.name);
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return;
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}
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else
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return;
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if (last_insn.kind != last_insn_other
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&& last_insn.seg == now_seg)
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{
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as_warn_where (last_insn.file, last_insn.line,
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_("`%s` skips -mlfence-before-indirect-branch on `%s`"),
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last_insn.name, i.tm.name);
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return;
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}
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p = frag_more (3);
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*p++ = 0xf;
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*p++ = 0xae;
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*p = 0xe8;
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return;
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}
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/* Output or/not and lfence before ret. */
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if (lfence_before_ret != lfence_before_ret_none
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&& (i.tm.base_opcode == 0xc2
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|| i.tm.base_opcode == 0xc3
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|| i.tm.base_opcode == 0xca
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|| i.tm.base_opcode == 0xcb))
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{
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if (last_insn.kind != last_insn_other
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&& last_insn.seg == now_seg)
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{
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as_warn_where (last_insn.file, last_insn.line,
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_("`%s` skips -mlfence-before-ret on `%s`"),
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last_insn.name, i.tm.name);
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return;
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}
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if (lfence_before_ret == lfence_before_ret_or)
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{
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/* orl: 0x830c2400. */
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p = frag_more ((flag_code == CODE_64BIT ? 1 : 0) + 4 + 3);
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if (flag_code == CODE_64BIT)
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*p++ = 0x48;
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*p++ = 0x83;
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*p++ = 0xc;
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*p++ = 0x24;
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*p++ = 0x0;
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}
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else
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{
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p = frag_more ((flag_code == CODE_64BIT ? 2 : 0) + 6 + 3);
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/* notl: 0xf71424. */
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if (flag_code == CODE_64BIT)
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*p++ = 0x48;
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*p++ = 0xf7;
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*p++ = 0x14;
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*p++ = 0x24;
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/* notl: 0xf71424. */
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if (flag_code == CODE_64BIT)
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*p++ = 0x48;
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*p++ = 0xf7;
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*p++ = 0x14;
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*p++ = 0x24;
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}
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*p++ = 0xf;
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*p++ = 0xae;
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*p = 0xe8;
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}
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}
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/* This is the guts of the machine-dependent assembler. LINE points to a
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machine dependent instruction. This function is supposed to emit
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the frags/bytes it assembles to. */
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@ -4628,9 +4927,13 @@ md_assemble (char *line)
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if (i.rex != 0)
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add_prefix (REX_OPCODE | i.rex);
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insert_lfence_before ();
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/* We are ready to output the insn. */
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output_insn ();
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insert_lfence_after ();
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last_insn.seg = now_seg;
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if (i.tm.opcode_modifier.isprefix)
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@ -12250,6 +12553,9 @@ const char *md_shortopts = "qnO::";
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#define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
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#define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
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#define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
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#define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
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#define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
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#define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
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struct option md_longopts[] =
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{
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@ -12289,6 +12595,10 @@ struct option md_longopts[] =
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{"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
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{"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
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{"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
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{"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
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{"mlfence-before-indirect-branch", required_argument, NULL,
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OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
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{"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
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{"mamd64", no_argument, NULL, OPTION_MAMD64},
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{"mintel64", no_argument, NULL, OPTION_MINTEL64},
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{NULL, no_argument, NULL, 0}
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@ -12668,6 +12978,41 @@ md_parse_option (int c, const char *arg)
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as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
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break;
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case OPTION_MLFENCE_AFTER_LOAD:
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if (strcasecmp (arg, "yes") == 0)
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lfence_after_load = 1;
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else if (strcasecmp (arg, "no") == 0)
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lfence_after_load = 0;
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else
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as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
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break;
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case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
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if (strcasecmp (arg, "all") == 0)
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lfence_before_indirect_branch = lfence_branch_all;
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||||
else if (strcasecmp (arg, "memory") == 0)
|
||||
lfence_before_indirect_branch = lfence_branch_memory;
|
||||
else if (strcasecmp (arg, "register") == 0)
|
||||
lfence_before_indirect_branch = lfence_branch_register;
|
||||
else if (strcasecmp (arg, "none") == 0)
|
||||
lfence_before_indirect_branch = lfence_branch_none;
|
||||
else
|
||||
as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
|
||||
arg);
|
||||
break;
|
||||
|
||||
case OPTION_MLFENCE_BEFORE_RET:
|
||||
if (strcasecmp (arg, "or") == 0)
|
||||
lfence_before_ret = lfence_before_ret_or;
|
||||
else if (strcasecmp (arg, "not") == 0)
|
||||
lfence_before_ret = lfence_before_ret_not;
|
||||
else if (strcasecmp (arg, "none") == 0)
|
||||
lfence_before_ret = lfence_before_ret_none;
|
||||
else
|
||||
as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
|
||||
arg);
|
||||
break;
|
||||
|
||||
case OPTION_MRELAX_RELOCATIONS:
|
||||
if (strcasecmp (arg, "yes") == 0)
|
||||
generate_relax_relocations = 1;
|
||||
|
|
@ -13025,6 +13370,15 @@ md_show_usage (FILE *stream)
|
|||
-mbranches-within-32B-boundaries\n\
|
||||
align branches within 32 byte boundary\n"));
|
||||
fprintf (stream, _("\
|
||||
-mlfence-after-load=[no|yes] (default: no)\n\
|
||||
generate lfence after load\n"));
|
||||
fprintf (stream, _("\
|
||||
-mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
|
||||
generate lfence before indirect near branch\n"));
|
||||
fprintf (stream, _("\
|
||||
-mlfence-before-ret=[none|or|not] (default: none)\n\
|
||||
generate lfence before ret\n"));
|
||||
fprintf (stream, _("\
|
||||
-mamd64 accept only AMD64 ISA [default]\n"));
|
||||
fprintf (stream, _("\
|
||||
-mintel64 accept only Intel64 ISA\n"));
|
||||
|
|
@ -13254,6 +13608,16 @@ i386_cons_align (int ignore ATTRIBUTE_UNUSED)
|
|||
last_insn.kind = last_insn_directive;
|
||||
last_insn.name = "constant directive";
|
||||
last_insn.file = as_where (&last_insn.line);
|
||||
if (lfence_before_ret != lfence_before_ret_none)
|
||||
{
|
||||
if (lfence_before_indirect_branch != lfence_branch_none)
|
||||
as_warn (_("constant directive skips -mlfence-before-ret "
|
||||
"and -mlfence-before-indirect-branch"));
|
||||
else
|
||||
as_warn (_("constant directive skips -mlfence-before-ret"));
|
||||
}
|
||||
else if (lfence_before_indirect_branch != lfence_branch_none)
|
||||
as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -464,6 +464,49 @@ on an instruction. It is equivalent to
|
|||
@option{-malign-branch-prefix-size=5}.
|
||||
The default doesn't align branches.
|
||||
|
||||
@cindex @samp{-mlfence-after-load=} option, i386
|
||||
@cindex @samp{-mlfence-after-load=} option, x86-64
|
||||
@item -mlfence-after-load=@var{no}
|
||||
@itemx -mlfence-after-load=@var{yes}
|
||||
These options control whether the assembler should generate lfence
|
||||
after load instructions. @option{-mlfence-after-load=@var{yes}} will
|
||||
generate lfence. @option{-mlfence-after-load=@var{no}} will not generate
|
||||
lfence, which is the default.
|
||||
|
||||
@cindex @samp{-mlfence-before-indirect-branch=} option, i386
|
||||
@cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
|
||||
@item -mlfence-before-indirect-branch=@var{none}
|
||||
@item -mlfence-before-indirect-branch=@var{all}
|
||||
@item -mlfence-before-indirect-branch=@var{register}
|
||||
@itemx -mlfence-before-indirect-branch=@var{memory}
|
||||
These options control whether the assembler should generate lfence
|
||||
after indirect near branch instructions.
|
||||
@option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
|
||||
after indirect near branch via register and issue a warning before
|
||||
indirect near branch via memory.
|
||||
@option{-mlfence-before-indirect-branch=@var{register}} will generate
|
||||
lfence after indirect near branch via register.
|
||||
@option{-mlfence-before-indirect-branch=@var{memory}} will issue a
|
||||
warning before indirect near branch via memory.
|
||||
@option{-mlfence-before-indirect-branch=@var{none}} will not generate
|
||||
lfence nor issue warning, which is the default. Note that lfence won't
|
||||
be generated before indirect near branch via register with
|
||||
@option{-mlfence-after-load=@var{yes}} since lfence will be generated
|
||||
after loading branch target register.
|
||||
|
||||
@cindex @samp{-mlfence-before-ret=} option, i386
|
||||
@cindex @samp{-mlfence-before-ret=} option, x86-64
|
||||
@item -mlfence-before-ret=@var{none}
|
||||
@item -mlfence-before-ret=@var{or}
|
||||
@itemx -mlfence-before-ret=@var{not}
|
||||
These options control whether the assembler should generate lfence
|
||||
before ret. @option{-mlfence-before-ret=@var{or}} will generate
|
||||
generate or instruction with lfence.
|
||||
@option{-mlfence-before-ret=@var{not}} will generate not instruction
|
||||
with lfence.
|
||||
@option{-mlfence-before-ret=@var{none}} will not generate lfence,
|
||||
which is the default.
|
||||
|
||||
@cindex @samp{-mx86-used-note=} option, i386
|
||||
@cindex @samp{-mx86-used-note=} option, x86-64
|
||||
@item -mx86-used-note=@var{no}
|
||||
|
|
|
|||
Loading…
Reference in New Issue