MIPS: Correct MUSTBE32 interpretation in delay slot handling
This change addresses `micromips_instruction_has_delay_slot' and `mips16_instruction_has_delay_slot' that both incorrectly interpret their MUSTBE32 argument. Their callers assume that when the flag is clear these functions will return 1 when any non-compact jump or branch instruction is present at ADDR, while in fact they will only return 1 for 16-bit such instructions only. This change makes the implementation match the expectations. * mips-tdep.c (micromips_instruction_has_delay_slot): When !mustbe32 also return 1 for 32-bit instructions. (mips16_instruction_has_delay_slot): Likewise. Add an explanatory comment.
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@ -1,3 +1,10 @@
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2014-10-05 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-tdep.c (micromips_instruction_has_delay_slot): When
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!mustbe32 also return 1 for 32-bit instructions.
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(mips16_instruction_has_delay_slot): Likewise. Add an
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explanatory comment.
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2014-10-03 Maciej W. Rozycki <macro@codesourcery.com>
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2014-10-03 Maciej W. Rozycki <macro@codesourcery.com>
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* elfread.c (elf_symtab_read): Also mark solib trampoline minimal
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* elfread.c (elf_symtab_read): Also mark solib trampoline minimal
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@ -7035,17 +7035,18 @@ micromips_instruction_has_delay_slot (struct gdbarch *gdbarch,
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if (status)
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if (status)
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return 0;
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return 0;
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if (!mustbe32) /* 16-bit instructions. */
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/* 16-bit instructions. */
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return (micromips_op (insn) == 0x11
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if ((micromips_op (insn) == 0x11
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/* POOL16C: bits 010001 */
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/* POOL16C: bits 010001 */
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&& (b5s5_op (insn) == 0xc
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&& (b5s5_op (insn) == 0xc
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/* JR16: bits 010001 01100 */
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/* JR16: bits 010001 01100 */
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|| (b5s5_op (insn) & 0x1e) == 0xe))
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|| (b5s5_op (insn) & 0x1e) == 0xe))
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/* JALR16, JALRS16: bits 010001 0111x */
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/* JALR16, JALRS16: bits 010001 0111x */
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|| (micromips_op (insn) & 0x37) == 0x23
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|| (micromips_op (insn) & 0x37) == 0x23
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/* BEQZ16, BNEZ16: bits 10x011 */
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/* BEQZ16, BNEZ16: bits 10x011 */
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|| micromips_op (insn) == 0x33;
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|| micromips_op (insn) == 0x33)
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/* B16: bits 110011 */
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/* B16: bits 110011 */
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return !mustbe32;
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/* 32-bit instructions. */
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/* 32-bit instructions. */
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if (micromips_op (insn) == 0x0)
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if (micromips_op (insn) == 0x0)
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@ -7091,6 +7092,10 @@ micromips_instruction_has_delay_slot (struct gdbarch *gdbarch,
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/* JALX: bits 111100 */
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/* JALX: bits 111100 */
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}
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}
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/* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
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slot (i.e. it is a non-compact jump instruction). The instruction
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must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
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static int
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static int
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mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr,
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mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr,
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int mustbe32)
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int mustbe32)
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@ -7102,8 +7107,8 @@ mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr,
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if (status)
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if (status)
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return 0;
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return 0;
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if (!mustbe32)
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if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
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return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
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return !mustbe32;
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return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
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return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
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}
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}
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