gas/testsuite/
2007-09-12 Jan Beulich <jbeulich@novell.com> * gas/i386/sse4_1.s, gas/i386/x86-64-sse4_1.s: Add two-operand forms of blendvps, blendvpd, and pblendvb. * gas/i386/sse4_1.d, gas/i386/sse4_1-intel.d, gas/i386/x86-64-sse4_1.d, gas/i386/x86-64-sse4_1-intel.d: Adjust, making last/first operand of blendvps, blendvpd, and pblendvb optional. opcodes/ 2007-09-12 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Add two-operand forms of blendvps, blendvpd, and pblendvb. * i386-tbl.h: Regenerate.
This commit is contained in:
Jan Beulich
parent
01a3c21322
commit
ae91ad40e9
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@ -1,3 +1,11 @@
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2007-09-12 Jan Beulich <jbeulich@novell.com>
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* gas/i386/sse4_1.s, gas/i386/x86-64-sse4_1.s: Add two-operand forms
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of blendvps, blendvpd, and pblendvb.
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* gas/i386/sse4_1.d, gas/i386/sse4_1-intel.d,
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gas/i386/x86-64-sse4_1.d, gas/i386/x86-64-sse4_1-intel.d: Adjust,
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making last/first operand of blendvps, blendvpd, and pblendvb
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optional.
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2007-09-12 Jan Beulich <jbeulich@novell.com>
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* gas/i386/amdfam10.s, gas/i386/x86-64-amdfam10.s: Add Intel syntax
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code.
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@ -11,10 +11,14 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 3a 0d c1 00 blendpd xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 3a 0c 01 00 blendps xmm0,XMMWORD PTR \[ecx\],0x0
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[ ]*[a-f0-9]+: 66 0f 3a 0c c1 00 blendps xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 38 15 01 blendvpd xmm0,XMMWORD PTR \[ecx\],xmm0
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd xmm0,xmm1,xmm0
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[ ]*[a-f0-9]+: 66 0f 38 14 01 blendvps xmm0,XMMWORD PTR \[ecx\],xmm0
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[ ]*[a-f0-9]+: 66 0f 38 14 c1 blendvps xmm0,xmm1,xmm0
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[ ]*[a-f0-9]+: 66 0f 38 15 01 blendvpd xmm0,XMMWORD PTR \[ecx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 15 01 blendvpd xmm0,XMMWORD PTR \[ecx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 01 blendvps xmm0,XMMWORD PTR \[ecx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 c1 blendvps xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 01 blendvps xmm0,XMMWORD PTR \[ecx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 c1 blendvps xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 3a 41 01 00 dppd xmm0,XMMWORD PTR \[ecx\],0x0
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[ ]*[a-f0-9]+: 66 0f 3a 41 c1 00 dppd xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 3a 40 01 00 dpps xmm0,XMMWORD PTR \[ecx\],0x0
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@ -28,8 +32,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 3a 42 c1 00 mpsadbw xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 38 2b 01 packusdw xmm0,XMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+: 66 0f 38 2b c1 packusdw xmm0,xmm1
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[ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[ecx\],xmm0
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[ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
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[ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[ecx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[ecx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 3a 0e 01 00 pblendw xmm0,XMMWORD PTR \[ecx\],0x0
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[ ]*[a-f0-9]+: 66 0f 3a 0e c1 00 pblendw xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 38 29 c1 pcmpeqq xmm0,xmm1
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@ -10,10 +10,14 @@ Disassembly of section .text:
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[ ]*[0-9a-f]+: 66 0f 3a 0d c1 00 blendpd \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0c 01 00 blendps \$0x0,\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0c c1 00 blendps \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd %xmm0,\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd %xmm0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps %xmm0,\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps %xmm0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd (%xmm0,)?\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd (%xmm0,)?\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps (%xmm0,)?\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps (%xmm0,)?\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 41 01 00 dppd \$0x0,\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 41 c1 00 dppd \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 40 01 00 dpps \$0x0,\(%ecx\),%xmm0
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@ -27,8 +31,10 @@ Disassembly of section .text:
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[ ]*[0-9a-f]+: 66 0f 3a 42 c1 00 mpsadbw \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 2b 01 packusdw \(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 2b c1 packusdw %xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb %xmm0,\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb (%xmm0,)?\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb (%xmm0,)?\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0e 01 00 pblendw \$0x0,\(%ecx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0e c1 00 pblendw \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 29 c1 pcmpeqq %xmm1,%xmm0
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@ -8,8 +8,12 @@ foo:
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blendps $0,%xmm1,%xmm0
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blendvpd %xmm0,(%ecx),%xmm0
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blendvpd %xmm0,%xmm1,%xmm0
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blendvpd (%ecx),%xmm0
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blendvpd %xmm1,%xmm0
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blendvps %xmm0,(%ecx),%xmm0
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blendvps %xmm0,%xmm1,%xmm0
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blendvps (%ecx),%xmm0
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blendvps %xmm1,%xmm0
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dppd $0,(%ecx),%xmm0
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dppd $0,%xmm1,%xmm0
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dpps $0,(%ecx),%xmm0
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@ -25,6 +29,8 @@ foo:
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packusdw %xmm1,%xmm0
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pblendvb %xmm0,(%ecx),%xmm0
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pblendvb %xmm0,%xmm1,%xmm0
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pblendvb (%ecx),%xmm0
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pblendvb %xmm1,%xmm0
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pblendw $0,(%ecx),%xmm0
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pblendw $0,%xmm1,%xmm0
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pcmpeqq %xmm1,%xmm0
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@ -11,10 +11,14 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 3a 0d c1 00 blendpd xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 3a 0c 01 00 blendps xmm0,XMMWORD PTR \[rcx\],0x0
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[ ]*[a-f0-9]+: 66 0f 3a 0c c1 00 blendps xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 38 15 01 blendvpd xmm0,XMMWORD PTR \[rcx\],xmm0
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd xmm0,xmm1,xmm0
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[ ]*[a-f0-9]+: 66 0f 38 14 01 blendvps xmm0,XMMWORD PTR \[rcx\],xmm0
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[ ]*[a-f0-9]+: 66 0f 38 14 c1 blendvps xmm0,xmm1,xmm0
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[ ]*[a-f0-9]+: 66 0f 38 15 01 blendvpd xmm0,XMMWORD PTR \[rcx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 15 01 blendvpd xmm0,XMMWORD PTR \[rcx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 01 blendvps xmm0,XMMWORD PTR \[rcx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 c1 blendvps xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 01 blendvps xmm0,XMMWORD PTR \[rcx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 14 c1 blendvps xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 3a 41 01 00 dppd xmm0,XMMWORD PTR \[rcx\],0x0
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[ ]*[a-f0-9]+: 66 0f 3a 41 c1 00 dppd xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 3a 40 01 00 dpps xmm0,XMMWORD PTR \[rcx\],0x0
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@ -29,8 +33,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 3a 42 c1 00 mpsadbw xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 38 2b 01 packusdw xmm0,XMMWORD PTR \[rcx\]
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[ ]*[a-f0-9]+: 66 0f 38 2b c1 packusdw xmm0,xmm1
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[ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\],xmm0
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[ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1,xmm0
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[ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 10 01 pblendvb xmm0,XMMWORD PTR \[rcx\](,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 38 10 c1 pblendvb xmm0,xmm1(,xmm0)?
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[ ]*[a-f0-9]+: 66 0f 3a 0e 01 00 pblendw xmm0,XMMWORD PTR \[rcx\],0x0
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[ ]*[a-f0-9]+: 66 0f 3a 0e c1 00 pblendw xmm0,xmm1,0x0
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[ ]*[a-f0-9]+: 66 0f 38 29 c1 pcmpeqq xmm0,xmm1
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@ -10,10 +10,14 @@ Disassembly of section .text:
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[ ]*[0-9a-f]+: 66 0f 3a 0d c1 00 blendpd \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0c 01 00 blendps \$0x0,\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0c c1 00 blendps \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd %xmm0,\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd %xmm0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps %xmm0,\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps %xmm0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd (%xmm0,)?\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd (%xmm0,)?\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps (%xmm0,)?\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps (%xmm0,)?\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 41 01 00 dppd \$0x0,\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 41 c1 00 dppd \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 40 01 00 dpps \$0x0,\(%rcx\),%xmm0
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@ -28,8 +32,10 @@ Disassembly of section .text:
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[ ]*[0-9a-f]+: 66 0f 3a 42 c1 00 mpsadbw \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 2b 01 packusdw \(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 2b c1 packusdw %xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb (%xmm0,)?\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb (%xmm0,)?\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb (%xmm0,)?%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0e 01 00 pblendw \$0x0,\(%rcx\),%xmm0
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[ ]*[0-9a-f]+: 66 0f 3a 0e c1 00 pblendw \$0x0,%xmm1,%xmm0
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[ ]*[0-9a-f]+: 66 0f 38 29 c1 pcmpeqq %xmm1,%xmm0
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@ -8,8 +8,12 @@ foo:
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blendps $0x0,%xmm1,%xmm0
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blendvpd %xmm0,(%rcx),%xmm0
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blendvpd %xmm0,%xmm1,%xmm0
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blendvpd (%rcx),%xmm0
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blendvpd %xmm1,%xmm0
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blendvps %xmm0,(%rcx),%xmm0
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blendvps %xmm0,%xmm1,%xmm0
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blendvps (%rcx),%xmm0
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blendvps %xmm1,%xmm0
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dppd $0x0,(%rcx),%xmm0
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dppd $0x0,%xmm1,%xmm0
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dpps $0x0,(%rcx),%xmm0
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@ -26,6 +30,8 @@ foo:
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packusdw %xmm1,%xmm0
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pblendvb %xmm0,(%rcx),%xmm0
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pblendvb %xmm0,%xmm1,%xmm0
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pblendvb (%rcx),%xmm0
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pblendvb %xmm1,%xmm0
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pblendw $0x0,(%rcx),%xmm0
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pblendw $0x0,%xmm1,%xmm0
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pcmpeqq %xmm1,%xmm0
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@ -1,3 +1,9 @@
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2007-09-12 Jan Beulich <jbeulich@novell.com>
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* i386-opc.tbl: Add two-operand forms of blendvps, blendvpd, and
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pblendvb.
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* i386-tbl.h: Regenerate.
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2007-09-09 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (main): Remove the local variable, unused.
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@ -1361,7 +1361,9 @@ pabsd, 2, 0x660f381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N
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blendpd, 3, 0x660f3a0d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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blendps, 3, 0x660f3a0c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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blendvpd, 3, 0x660f3815, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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blendvpd, 2, 0x660f3815, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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blendvps, 3, 0x660f3814, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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blendvps, 2, 0x660f3814, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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dppd, 3, 0x660f3a41, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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dpps, 3, 0x660f3a40, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
extractps, 3, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
|
@ -1370,6 +1372,7 @@ movntdqa, 2, 0x660f382a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lS
|
|||
mpsadbw, 3, 0x660f3a42, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
packusdw, 2, 0x660f382b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
pblendvb, 3, 0x660f3810, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
pblendvb, 2, 0x660f3810, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
pblendw, 3, 0x660f3a0e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
pcmpeqq, 2, 0x660f3829, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
pextrb, 3, 0x660f3a14, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
|
|
|||
|
|
@ -8648,6 +8648,15 @@ const template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "blendvpd", 2, 0x660f3815, None,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1,
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "blendvps", 3, 0x660f3814, None,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
|
|
@ -8659,6 +8668,15 @@ const template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "blendvps", 2, 0x660f3814, None,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1,
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "dppd", 3, 0x660f3a41, None,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
|
|
@ -8743,6 +8761,15 @@ const template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "pblendvb", 2, 0x660f3810, None,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1,
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "pblendw", 3, 0x660f3a0e, None,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
|
|
|
|||
Loading…
Reference in New Issue