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Fix unexpected failures in the linker testsuite for ARM VxWorks targets. 

PR ld/19455
	* elf32-arm.c (elf32_arm_create_dynamic_sections): Set the ELF
	class of the linker stub bfd.
	(elf32_arm_check_relocs): Skip check for pic format after
	processing a vxWorks R_ARM_ABS12 reloc.
	* elflink.c (bfd_elf_final_link): Check for ELFCLASSNONE when
	reporting a class mismatch.

	* testsuite/ld-arm/vxworks1-lib.dd: Update for current
	disassmebler output.
	* testsuite/ld-arm/vxworks1-lib.rd: Likewise.
	* testsuite/ld-arm/vxworks1.dd: Likewise.
	* testsuite/ld-arm/vxworks1.rd: Likewise.
	* testsuite/ld-arm/vxworks1.ld: Set the output format.
This commit is contained in:
Nick Clifton 2016-01-21 10:51:25 +00:00
parent 305e13e67f
commit aebf9be708
9 changed files with 56 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
bfd/ChangeLog
View File

@ -1,3 +1,13 @@
2016-01-21 Nick Clifton <nickc@redhat.com>
PR ld/19455
* elf32-arm.c (elf32_arm_create_dynamic_sections): Set the ELF
class of the linker stub bfd.
(elf32_arm_check_relocs): Skip check for pic format after
processing a vxWorks R_ARM_ABS12 reloc.
* elflink.c (bfd_elf_final_link): Check for ELFCLASSNONE when
reporting a class mismatch.
2016-01-21 Jiong Wang <jiong.wang@arm.com>
* elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch

6
bfd/elf32-arm.c
View File

@ -3575,6 +3575,9 @@ elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
htab->plt_entry_size
= 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
}
if (elf_elfheader (dynobj))
elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
}
else
{
@ -13613,6 +13616,8 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
may_need_local_target_p = TRUE;
break;
}
else goto jump_over;
/* Fall through. */
case R_ARM_MOVW_ABS_NC:
@ -13632,6 +13637,7 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
/* Fall through. */
case R_ARM_ABS32:
case R_ARM_ABS32_NOI:
jump_over:
if (h != NULL && bfd_link_executable (info))
{
h->pointer_equality_needed = 1;

17
bfd/elflink.c
View File

@ -11395,15 +11395,20 @@ bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
{
const char *iclass, *oclass;
if (bed->s->elfclass == ELFCLASS64)
switch (bed->s->elfclass)
{
iclass = "ELFCLASS32";
oclass = "ELFCLASS64";
case ELFCLASS64: oclass = "ELFCLASS64"; break;
case ELFCLASS32: oclass = "ELFCLASS32"; break;
case ELFCLASSNONE: oclass = "ELFCLASSNONE"; break;
default: abort ();
}
else
switch (elf_elfheader (sub)->e_ident[EI_CLASS])
{
iclass = "ELFCLASS64";
oclass = "ELFCLASS32";
case ELFCLASS64: iclass = "ELFCLASS64"; break;
case ELFCLASS32: iclass = "ELFCLASS32"; break;
case ELFCLASSNONE: iclass = "ELFCLASSNONE"; break;
default: abort ();
}
bfd_set_error (bfd_error_wrong_format);

10
ld/ChangeLog
View File

@ -1,3 +1,13 @@
2016-01-21 Nick Clifton <nickc@redhat.com>
PR ld/19455
* testsuite/ld-arm/vxworks1-lib.dd: Update for current
disassmebler output.
* testsuite/ld-arm/vxworks1-lib.rd: Likewise.
* testsuite/ld-arm/vxworks1.dd: Likewise.
* testsuite/ld-arm/vxworks1.rd: Likewise.
* testsuite/ld-arm/vxworks1.ld: Set the output format.
2016-01-20 Jiong Wang <jiong.wang@arm.com>
* testsuite/ld-aarch64/farcall-section.d: Delete.

10
ld/testsuite/ld-arm/vxworks1-lib.dd
View File

@ -4,16 +4,16 @@
Disassembly of section \.plt:
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e59fc000 ldr ip, \[pc, #0\] ; 80808 <.*>
80800: e59fc000 ldr ip, \[pc] ; 80808 <.*>
80804: e79cf009 ldr pc, \[ip, r9\]
80808: 0000000c .word 0x0000000c
8080c: e59fc000 ldr ip, \[pc, #0\] ; 80814 <.*>
8080c: e59fc000 ldr ip, \[pc] ; 80814 <.*>
80810: e599f008 ldr pc, \[r9, #8\]
80814: 00000000 .word 0x00000000
80818: e59fc000 ldr ip, \[pc, #0\] ; 80820 <.*>
80818: e59fc000 ldr ip, \[pc] ; 80820 <.*>
8081c: e79cf009 ldr pc, \[ip, r9\]
80820: 00000010 .word 0x00000010
80824: e59fc000 ldr ip, \[pc, #0\] ; 8082c <.*>
80824: e59fc000 ldr ip, \[pc] ; 8082c <.*>
80828: e599f008 ldr pc, \[r9, #8\]
8082c: 0000000c .word 0x0000000c
Disassembly of section \.text:
@ -25,7 +25,7 @@ Disassembly of section \.text:
80c0c: e5999000 ldr r9, \[r9\]
80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <.*>
80c14: e7991000 ldr r1, \[r9, r0\]
80c18: e2811001 add r1, r1, #1 ; 0x1
80c18: e2811001 add r1, r1, #1
80c1c: e7891000 str r1, \[r9, r0\]
80c20: eb000004 bl 80c38 <slocal>
80c24: ebfffefb bl 80818 <.*>

2
ld/testsuite/ld-arm/vxworks1-lib.rd
View File

@ -6,7 +6,7 @@ Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Relocation section '\.rela\.dyn' at offset .* contains 4 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
00081800 00000017 R_ARM_RELATIVE * 00080c38
00081800 00000017 R_ARM_RELATIVE * 80c38
00080c0c .*06 R_ARM_ABS12 00000000 __GOTT_INDEX__ \+ 0
00080c30 .*02 R_ARM_ABS32 00000000 __GOTT_BASE__ \+ 0
00081414 .*15 R_ARM_GLOB_DAT 00081c00 x \+ 0

12
ld/testsuite/ld-arm/vxworks1.dd
View File

@ -5,22 +5,22 @@ Disassembly of section \.plt:
00080800 <_PROCEDURE_LINKAGE_TABLE_>:
80800: e52dc008 str ip, \[sp, #-8\]!
80804: e59fc000 ldr ip, \[pc, #0\] ; 8080c <.*>
80804: e59fc000 ldr ip, \[pc] ; 8080c <.*>
80808: e59cf008 ldr pc, \[ip, #8\]
8080c: 00081400 .word 0x00081400
8080c: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_
80810: e59fc000 ldr ip, \[pc, #0\] ; 80818 <.*>
80810: e59fc000 ldr ip, \[pc] ; 80818 <.*>
80814: e59cf000 ldr pc, \[ip\]
80818: 0008140c .word 0x0008140c
80818: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0xc
8081c: e59fc000 ldr ip, \[pc, #0\] ; 80824 <.*>
8081c: e59fc000 ldr ip, \[pc] ; 80824 <.*>
80820: eafffff6 b 80800 <.*>
80824: 00000000 .word 0x00000000
80828: e59fc000 ldr ip, \[pc, #0\] ; 80830 <.*>
80828: e59fc000 ldr ip, \[pc] ; 80830 <.*>
8082c: e59cf000 ldr pc, \[ip\]
80830: 00081410 .word 0x00081410
80830: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0x10
80834: e59fc000 ldr ip, \[pc, #0\] ; 8083c <.*>
80834: e59fc000 ldr ip, \[pc] ; 8083c <.*>
80838: eafffff0 b 80800 <.*>
8083c: 0000000c .word 0x0000000c
Disassembly of section \.text:
@ -29,7 +29,7 @@ Disassembly of section \.text:
80c00: ebffff08 bl 80828 <.*>
80c00: R_ARM_PC24 \.plt\+0x20
80c04: eb000000 bl 80c0c <sexternal>
80c04: R_ARM_PC24 sexternal\+0xfffffff8
80c04: R_ARM_PC24 sexternal-0x8
80c08: eaffff00 b 80810 <.*>
80c08: R_ARM_PC24 \.plt\+0x8

4
ld/testsuite/ld-arm/vxworks1.ld
View File

@ -1,3 +1,7 @@
OUTPUT_FORMAT("elf32-littlearm-vxworks", "elf32-bigarm-vxworks",
"elf32-littlearm-vxworks")
OUTPUT_ARCH(arm)
SECTIONS
{
. = 0x80000;

6
ld/testsuite/ld-arm/vxworks1.rd
View File

@ -1,13 +1,13 @@
Relocation section '\.rela\.plt' at offset .* contains 2 entries:
Offset Info Type Sym\.Value Sym\. Name \+ Addend
0008140c .*16 R_ARM_JUMP_SLOT 00080810 sglobal \+ 0
00081410 .*16 R_ARM_JUMP_SLOT 00080828 foo \+ 0
0008140c .*16 R_ARM_JUMP_SLOT 000..... sglobal \+ 0
00081410 .*16 R_ARM_JUMP_SLOT 000..... foo \+ 0
Relocation section '\.rela\.text' at offset .* contains 3 entries:
Offset Info Type Sym.Value Sym. Name \+ Addend
00080c00 .*01 R_ARM_PC24 00080800 \.plt \+ 20
00080c04 .*01 R_ARM_PC24 00080c0c sexternal \+ fffffff8
00080c04 .*01 R_ARM_PC24 000..... sexternal - 8
00080c08 .*01 R_ARM_PC24 00080800 \.plt \+ 8
Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries: