[ gas/ChangeLog ]
2003-04-02 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro2): Adjust implementation of
M_ULH, M_ULHU, M_ULW, and M_ULD so that they work properly
in the case where the source and destination registers
are the same.
[ gas/testsuite/ChangeLog ]
2003-04-02 Chris Demetriou <cgd@broadcom.com>
* gas/mips/ulh.d: Adjust for ulh and ulhu macro assembly changes.
* gas/mips/mips.exp: Define new "gpr_ilocks" architecture
property, and add it to mips2 (and later) chips and r3900.
* gas/mips/uld2.s: New test source file.
* gas/mips/ulh2.s: Likewise.
* gas/mips/ulw2.s: Likewise.
* gas/mips/uld2.l: New test stderr listing.
* gas/mips/ulh2.l: Likewise.
* gas/mips/ulw2.l: Likewise.
* gas/mips/uld2-eb.d: New test.
* gas/mips/uld2-el.d: Likewise.
* gas/mips/ulh2-eb.d: Likewise.
* gas/mips/ulh2-el.d: Likewise.
* gas/mips/ulw2-eb-ilocks.d: Likewise.
* gas/mips/ulw2-eb.d: Likewise.
* gas/mips/ulw2-el-ilocks.d: Likewise.
* gas/mips/ulw2-el.d: Likewise.
* gas/mips/mips.exp: Run new tests for appropriate architectures.
This commit is contained in:
Chris Demetriou
parent
8fdeb6e3c5
commit
af22f5b24a
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@ -1,3 +1,10 @@
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2003-04-02 Chris Demetriou <cgd@broadcom.com>
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* config/tc-mips.c (macro2): Adjust implementation of
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M_ULH, M_ULHU, M_ULW, and M_ULD so that they work properly
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in the case where the source and destination registers
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are the same.
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2003-04-01 Bob Wilson <bob.wilson@acm.org>
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* Makefile.am (CPU_TYPES): Add xtensa.
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@ -7554,19 +7554,18 @@ macro2 (ip)
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ulh:
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if (offset_expr.X_add_number >= 0x7fff)
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as_bad (_("operand overflow"));
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/* avoid load delay */
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if (! target_big_endian)
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++offset_expr.X_add_number;
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macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
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macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
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(int) BFD_RELOC_LO16, breg);
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if (! target_big_endian)
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--offset_expr.X_add_number;
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else
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++offset_expr.X_add_number;
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macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
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macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
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(int) BFD_RELOC_LO16, breg);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
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treg, treg, 8);
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AT, AT, 8);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
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treg, treg, AT);
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break;
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@ -7583,17 +7582,29 @@ macro2 (ip)
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ulw:
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if (offset_expr.X_add_number >= 0x8000 - off)
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as_bad (_("operand overflow"));
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if (treg != breg)
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tempreg = treg;
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else
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tempreg = AT;
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if (! target_big_endian)
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offset_expr.X_add_number += off;
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macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
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macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
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(int) BFD_RELOC_LO16, breg);
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if (! target_big_endian)
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offset_expr.X_add_number -= off;
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else
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offset_expr.X_add_number += off;
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macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
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macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
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(int) BFD_RELOC_LO16, breg);
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return;
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/* If necessary, move the result in tempreg the final destination. */
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if (treg == tempreg)
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return;
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/* Protect second load's delay slot. */
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if (!gpr_interlocks)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
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move_register (&icnt, treg, tempreg);
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break;
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case M_ULD_A:
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s = "ldl";
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@ -1,3 +1,25 @@
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2003-04-02 Chris Demetriou <cgd@broadcom.com>
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* gas/mips/ulh.d: Adjust for ulh and ulhu macro assembly changes.
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* gas/mips/mips.exp: Define new "gpr_ilocks" architecture
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property, and add it to mips2 (and later) chips and r3900.
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* gas/mips/uld2.s: New test source file.
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* gas/mips/ulh2.s: Likewise.
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* gas/mips/ulw2.s: Likewise.
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* gas/mips/uld2.l: New test stderr listing.
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* gas/mips/ulh2.l: Likewise.
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* gas/mips/ulw2.l: Likewise.
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* gas/mips/uld2-eb.d: New test.
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* gas/mips/uld2-el.d: Likewise.
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* gas/mips/ulh2-eb.d: Likewise.
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* gas/mips/ulh2-el.d: Likewise.
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* gas/mips/ulw2-eb-ilocks.d: Likewise.
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* gas/mips/ulw2-eb.d: Likewise.
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* gas/mips/ulw2-el-ilocks.d: Likewise.
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* gas/mips/ulw2-el.d: Likewise.
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* gas/mips/mips.exp: Run new tests for appropriate architectures.
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2003-04-01 Bob Wilson <bob.wilson@acm.org>
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* gas/xtensa/all.exp: New file.
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@ -55,6 +55,10 @@
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# The architecture includes the instructions defined
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# by that MIPS ISA.
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#
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# gpr_ilocks
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# The architecture interlocks GPRs accesses. (That is,
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# there are no load delay slots.)
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#
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# mips3d The architecture includes the MIPS-3D ASE.
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#
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# ror The architecture includes hardware rotate instructions.
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@ -332,7 +336,7 @@ proc run_list_test_arches { name opts arch_list } {
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# to any architecture.
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mips_arch_create mips1 32 {} {} \
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{ -march=mips1 -mtune=mips1 } { -mmips:3000 }
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mips_arch_create mips2 32 mips1 {} \
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mips_arch_create mips2 32 mips1 { gpr_ilocks } \
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{ -march=mips2 -mtune=mips2 } { -mmips:6000 }
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mips_arch_create mips3 64 mips2 {} \
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{ -march=mips3 -mtune=mips3 } { -mmips:4000 }
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@ -352,7 +356,7 @@ mips_arch_create mips64 64 mips5 { mips32 } \
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{ mipsisa64-*-* mipsisa64el-*-* }
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mips_arch_create r3000 32 mips1 {} \
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{ -march=r3000 -mtune=r3000 } { -mmips:3000 }
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mips_arch_create r3900 32 mips1 {} \
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mips_arch_create r3900 32 mips1 { gpr_ilocks } \
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{ -march=r3900 -mtune=r3900 } { -mmips:3900 } \
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{ mipstx39-*-* mipstx39el-*-* }
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mips_arch_create r4000 64 mips3 {} \
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@ -492,6 +496,8 @@ if { [istarget mips*-*-*] } then {
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if !$aout { run_dump_test "sb" }
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run_dump_test "trunc"
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if !$aout { run_dump_test "ulh" }
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run_dump_test_arches "ulh2-eb" [mips_arch_list_matching mips1]
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run_dump_test_arches "ulh2-el" [mips_arch_list_matching mips1]
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if $elf { run_dump_test "ulh-svr4pic" }
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if $elf { run_dump_test "ulh-xgot" }
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if $ecoff { run_dump_test "ulh-empic" }
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@ -502,6 +508,14 @@ if { [istarget mips*-*-*] } then {
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run_dump_test "usw"
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run_dump_test "usd"
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}
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run_dump_test_arches "ulw2-eb" [mips_arch_list_matching !gpr_ilocks]
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run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks]
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run_dump_test_arches "ulw2-el" [mips_arch_list_matching !gpr_ilocks]
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run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks]
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run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3]
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run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3]
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# The mips16 test can only be run on ELF, because only ELF
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# supports the necessary mips16 reloc.
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if { $elf && !$no_mips16 } {
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@ -0,0 +1,26 @@
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#as: -EB
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#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
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#name: uld2 -EB
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#source: uld2.s
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#stderr: uld2.l
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# Further checks of uld macro.
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# XXX: note: when 'move' is changed to use 'or' rather than daddu, the
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# XXX: 'move' opcodes shown here (whose raw instruction fields are daddu)
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# XXX: should be changed to be 'or' instructions and this comment should be
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# XXX: removed.
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 68a40000 ldl \$4,0\(\$5\)
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0+0004 <[^>]*> 6ca40007 ldr \$4,7\(\$5\)
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0+0008 <[^>]*> 68a40001 ldl \$4,1\(\$5\)
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0+000c <[^>]*> 6ca40008 ldr \$4,8\(\$5\)
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0+0010 <[^>]*> 68a10000 ldl \$1,0\(\$5\)
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0+0014 <[^>]*> 6ca10007 ldr \$1,7\(\$5\)
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0+0018 <[^>]*> 0020282d move \$5,\$1
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0+001c <[^>]*> 68a10001 ldl \$1,1\(\$5\)
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0+0020 <[^>]*> 6ca10008 ldr \$1,8\(\$5\)
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0+0024 <[^>]*> 0020282d move \$5,\$1
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\.\.\.
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@ -0,0 +1,26 @@
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#as: -EL
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#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
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#name: uld2 -EL
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#source: uld2.s
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#stderr: uld2.l
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# Further checks of uld macro.
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# XXX: note: when 'move' is changed to use 'or' rather than daddu, the
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# XXX: 'move' opcodes shown here (whose raw instruction fields are daddu)
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# XXX: should be changed to be 'or' instructions and this comment should be
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# XXX: removed.
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 68a40007 ldl \$4,7\(\$5\)
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0+0004 <[^>]*> 6ca40000 ldr \$4,0\(\$5\)
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0+0008 <[^>]*> 68a40008 ldl \$4,8\(\$5\)
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0+000c <[^>]*> 6ca40001 ldr \$4,1\(\$5\)
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0+0010 <[^>]*> 68a10007 ldl \$1,7\(\$5\)
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0+0014 <[^>]*> 6ca10000 ldr \$1,0\(\$5\)
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0+0018 <[^>]*> 0020282d move \$5,\$1
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0+001c <[^>]*> 68a10008 ldl \$1,8\(\$5\)
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0+0020 <[^>]*> 6ca10001 ldr \$1,1\(\$5\)
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0+0024 <[^>]*> 0020282d move \$5,\$1
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\.\.\.
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@ -0,0 +1,3 @@
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.*: Assembler messages:
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.*:11: Warning: Macro used \$at after "\.set noat"
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.*:12: Warning: Macro used \$at after "\.set noat"
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@ -0,0 +1,15 @@
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# Source file used to test the uld macro (harder).
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.set noat
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.text
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text_label:
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uld $4,0($5)
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uld $4,1($5)
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uld $5,0($5) # warns
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uld $5,1($5) # warns
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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@ -7,22 +7,22 @@
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> lb a0,[01]\(zero\)
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0+0004 <[^>]*> lbu at,[01]\(zero\)
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0+0008 <[^>]*> sll a0,a0,0x8
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0+0000 <[^>]*> lb at,[01]\(zero\)
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0+0004 <[^>]*> lbu a0,[01]\(zero\)
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0+0008 <[^>]*> sll at,at,0x8
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0+000c <[^>]*> or a0,a0,at
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0+0010 <[^>]*> lb a0,[12]\(zero\)
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0+0014 <[^>]*> lbu at,[12]\(zero\)
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0+0018 <[^>]*> sll a0,a0,0x8
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0+0010 <[^>]*> lb at,[12]\(zero\)
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0+0014 <[^>]*> lbu a0,[12]\(zero\)
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0+0018 <[^>]*> sll at,at,0x8
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0+001c <[^>]*> or a0,a0,at
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0+0020 <[^>]*> li at,0x8000
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0+0024 <[^>]*> lb a0,[01]\(at\)
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0+0028 <[^>]*> lbu at,[01]\(at\)
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0+002c <[^>]*> sll a0,a0,0x8
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0+0030 <[^>]*> or a0,a0,at
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0+0034 <[^>]*> lb a0,-3276[78]\(zero\)
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0+0038 <[^>]*> lbu at,-3276[78]\(zero\)
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0+003c <[^>]*> sll a0,a0,0x8
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0+0034 <[^>]*> lb at,-3276[78]\(zero\)
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0+0038 <[^>]*> lbu a0,-3276[78]\(zero\)
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0+003c <[^>]*> sll at,at,0x8
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0+0040 <[^>]*> or a0,a0,at
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0+0044 <[^>]*> lui at,0x1
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0+0048 <[^>]*> lb a0,[01]\(at\)
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@ -35,13 +35,13 @@ Disassembly of section .text:
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0+0064 <[^>]*> lbu at,[01]\(at\)
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0+0068 <[^>]*> sll a0,a0,0x8
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0+006c <[^>]*> or a0,a0,at
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0+0070 <[^>]*> lb a0,[01]\(a1\)
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0+0074 <[^>]*> lbu at,[01]\(a1\)
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0+0078 <[^>]*> sll a0,a0,0x8
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0+0070 <[^>]*> lb at,[01]\(a1\)
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0+0074 <[^>]*> lbu a0,[01]\(a1\)
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0+0078 <[^>]*> sll at,at,0x8
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0+007c <[^>]*> or a0,a0,at
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0+0080 <[^>]*> lb a0,[12]\(a1\)
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0+0084 <[^>]*> lbu at,[12]\(a1\)
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0+0088 <[^>]*> sll a0,a0,0x8
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0+0080 <[^>]*> lb at,[12]\(a1\)
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0+0084 <[^>]*> lbu a0,[12]\(a1\)
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0+0088 <[^>]*> sll at,at,0x8
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0+008c <[^>]*> or a0,a0,at
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0+0090 <[^>]*> lui at,[-0-9x]+
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[ ]*90: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
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@ -367,8 +367,8 @@ Disassembly of section .text:
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0+045c <[^>]*> lbu at,[01]\(at\)
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0+0460 <[^>]*> sll a0,a0,0x8
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0+0464 <[^>]*> or a0,a0,at
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0+0468 <[^>]*> lbu a0,[01]\(zero\)
|
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0+046c <[^>]*> lbu at,[01]\(zero\)
|
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0+0470 <[^>]*> sll a0,a0,0x8
|
||||
0+0468 <[^>]*> lbu at,[01]\(zero\)
|
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0+046c <[^>]*> lbu a0,[01]\(zero\)
|
||||
0+0470 <[^>]*> sll at,at,0x8
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0+0474 <[^>]*> or a0,a0,at
|
||||
...
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|
|
|
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|
|
@ -0,0 +1,44 @@
|
|||
#as: -EB
|
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#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
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#name: ulh2 -EB
|
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#source: ulh2.s
|
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#stderr: ulh2.l
|
||||
|
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# Further checks of ulh/ulhu macros.
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|
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.*: +file format .*mips.*
|
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|
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Disassembly of section .text:
|
||||
0+0000 <[^>]*> 80a10000 lb \$1,0\(\$5\)
|
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0+0004 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
|
||||
0+0008 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+000c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0010 <[^>]*> 80a10001 lb \$1,1\(\$5\)
|
||||
0+0014 <[^>]*> 90a40002 lbu \$4,2\(\$5\)
|
||||
0+0018 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+001c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0020 <[^>]*> 80a10000 lb \$1,0\(\$5\)
|
||||
0+0024 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
|
||||
0+0028 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+002c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
0+0030 <[^>]*> 80a10001 lb \$1,1\(\$5\)
|
||||
0+0034 <[^>]*> 90a50002 lbu \$5,2\(\$5\)
|
||||
0+0038 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+003c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
0+0040 <[^>]*> 90a10000 lbu \$1,0\(\$5\)
|
||||
0+0044 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
|
||||
0+0048 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+004c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0050 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
|
||||
0+0054 <[^>]*> 90a40002 lbu \$4,2\(\$5\)
|
||||
0+0058 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+005c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0060 <[^>]*> 90a10000 lbu \$1,0\(\$5\)
|
||||
0+0064 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
|
||||
0+0068 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+006c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
0+0070 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
|
||||
0+0074 <[^>]*> 90a50002 lbu \$5,2\(\$5\)
|
||||
0+0078 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+007c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#as: -EL
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
||||
#name: ulh2 -EL
|
||||
#source: ulh2.s
|
||||
#stderr: ulh2.l
|
||||
|
||||
# Further checks of ulh/ulhu macros.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 80a10001 lb \$1,1\(\$5\)
|
||||
0+0004 <[^>]*> 90a40000 lbu \$4,0\(\$5\)
|
||||
0+0008 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+000c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0010 <[^>]*> 80a10002 lb \$1,2\(\$5\)
|
||||
0+0014 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
|
||||
0+0018 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+001c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0020 <[^>]*> 80a10001 lb \$1,1\(\$5\)
|
||||
0+0024 <[^>]*> 90a50000 lbu \$5,0\(\$5\)
|
||||
0+0028 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+002c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
0+0030 <[^>]*> 80a10002 lb \$1,2\(\$5\)
|
||||
0+0034 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
|
||||
0+0038 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+003c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
0+0040 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
|
||||
0+0044 <[^>]*> 90a40000 lbu \$4,0\(\$5\)
|
||||
0+0048 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+004c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0050 <[^>]*> 90a10002 lbu \$1,2\(\$5\)
|
||||
0+0054 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
|
||||
0+0058 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+005c <[^>]*> 00812025 or \$4,\$4,\$1
|
||||
0+0060 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
|
||||
0+0064 <[^>]*> 90a50000 lbu \$5,0\(\$5\)
|
||||
0+0068 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+006c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
0+0070 <[^>]*> 90a10002 lbu \$1,2\(\$5\)
|
||||
0+0074 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
|
||||
0+0078 <[^>]*> 00010a00 sll \$1,\$1,0x8
|
||||
0+007c <[^>]*> 00a12825 or \$5,\$5,\$1
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
.*: Assembler messages:
|
||||
.*:8: Warning: Macro used \$at after "\.set noat"
|
||||
.*:9: Warning: Macro used \$at after "\.set noat"
|
||||
.*:11: Warning: Macro used \$at after "\.set noat"
|
||||
.*:12: Warning: Macro used \$at after "\.set noat"
|
||||
.*:14: Warning: Macro used \$at after "\.set noat"
|
||||
.*:15: Warning: Macro used \$at after "\.set noat"
|
||||
.*:17: Warning: Macro used \$at after "\.set noat"
|
||||
.*:18: Warning: Macro used \$at after "\.set noat"
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# Source file used to test the ulh and ulhu macros (harder).
|
||||
|
||||
.set noat
|
||||
|
||||
.text
|
||||
text_label:
|
||||
|
||||
ulh $4,0($5) # warns
|
||||
ulh $4,1($5) # warns
|
||||
|
||||
ulh $5,0($5) # warns
|
||||
ulh $5,1($5) # warns
|
||||
|
||||
ulhu $4,0($5) # warns
|
||||
ulhu $4,1($5) # warns
|
||||
|
||||
ulhu $5,0($5) # warns
|
||||
ulhu $5,1($5) # warns
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#as: -EB
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
||||
#name: ulw2 -EB interlocked
|
||||
#source: ulw2.s
|
||||
#stderr: ulw2.l
|
||||
|
||||
# Further checks of ulw macro.
|
||||
# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
|
||||
# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
|
||||
# XXX: should be changed to be 'or' instructions and this comment should be
|
||||
# XXX: removed.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 88a40000 lwl \$4,0\(\$5\)
|
||||
0+0004 <[^>]*> 98a40003 lwr \$4,3\(\$5\)
|
||||
0+0008 <[^>]*> 88a40001 lwl \$4,1\(\$5\)
|
||||
0+000c <[^>]*> 98a40004 lwr \$4,4\(\$5\)
|
||||
0+0010 <[^>]*> 88a10000 lwl \$1,0\(\$5\)
|
||||
0+0014 <[^>]*> 98a10003 lwr \$1,3\(\$5\)
|
||||
0+0018 <[^>]*> 0020282[1d] move \$5,\$1
|
||||
0+001c <[^>]*> 88a10001 lwl \$1,1\(\$5\)
|
||||
0+0020 <[^>]*> 98a10004 lwr \$1,4\(\$5\)
|
||||
0+0024 <[^>]*> 0020282[1d] move \$5,\$1
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#as: -EB
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
||||
#name: ulw2 -EB non-interlocked
|
||||
#source: ulw2.s
|
||||
#stderr: ulw2.l
|
||||
|
||||
# Further checks of ulw macro.
|
||||
# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
|
||||
# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
|
||||
# XXX: should be changed to be 'or' instructions and this comment should be
|
||||
# XXX: removed.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 88a40000 lwl \$4,0\(\$5\)
|
||||
0+0004 <[^>]*> 98a40003 lwr \$4,3\(\$5\)
|
||||
0+0008 <[^>]*> 88a40001 lwl \$4,1\(\$5\)
|
||||
0+000c <[^>]*> 98a40004 lwr \$4,4\(\$5\)
|
||||
0+0010 <[^>]*> 88a10000 lwl \$1,0\(\$5\)
|
||||
0+0014 <[^>]*> 98a10003 lwr \$1,3\(\$5\)
|
||||
0+0018 <[^>]*> 00000000 nop
|
||||
0+001c <[^>]*> 0020282[1d] move \$5,\$1
|
||||
0+0020 <[^>]*> 88a10001 lwl \$1,1\(\$5\)
|
||||
0+0024 <[^>]*> 98a10004 lwr \$1,4\(\$5\)
|
||||
0+0028 <[^>]*> 00000000 nop
|
||||
0+002c <[^>]*> 0020282[1d] move \$5,\$1
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#as: -EL
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
||||
#name: ulw2 -EL interlocked
|
||||
#source: ulw2.s
|
||||
#stderr: ulw2.l
|
||||
|
||||
# Further checks of ulw macro.
|
||||
# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
|
||||
# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
|
||||
# XXX: should be changed to be 'or' instructions and this comment should be
|
||||
# XXX: removed.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 88a40003 lwl \$4,3\(\$5\)
|
||||
0+0004 <[^>]*> 98a40000 lwr \$4,0\(\$5\)
|
||||
0+0008 <[^>]*> 88a40004 lwl \$4,4\(\$5\)
|
||||
0+000c <[^>]*> 98a40001 lwr \$4,1\(\$5\)
|
||||
0+0010 <[^>]*> 88a10003 lwl \$1,3\(\$5\)
|
||||
0+0014 <[^>]*> 98a10000 lwr \$1,0\(\$5\)
|
||||
0+0018 <[^>]*> 0020282[1d] move \$5,\$1
|
||||
0+001c <[^>]*> 88a10004 lwl \$1,4\(\$5\)
|
||||
0+0020 <[^>]*> 98a10001 lwr \$1,1\(\$5\)
|
||||
0+0024 <[^>]*> 0020282[1d] move \$5,\$1
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#as: -EL
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
|
||||
#name: ulw2 -EL non-interlocked
|
||||
#source: ulw2.s
|
||||
#stderr: ulw2.l
|
||||
|
||||
# Further checks of ulw macro.
|
||||
# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
|
||||
# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
|
||||
# XXX: should be changed to be 'or' instructions and this comment should be
|
||||
# XXX: removed.
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+0000 <[^>]*> 88a40003 lwl \$4,3\(\$5\)
|
||||
0+0004 <[^>]*> 98a40000 lwr \$4,0\(\$5\)
|
||||
0+0008 <[^>]*> 88a40004 lwl \$4,4\(\$5\)
|
||||
0+000c <[^>]*> 98a40001 lwr \$4,1\(\$5\)
|
||||
0+0010 <[^>]*> 88a10003 lwl \$1,3\(\$5\)
|
||||
0+0014 <[^>]*> 98a10000 lwr \$1,0\(\$5\)
|
||||
0+0018 <[^>]*> 00000000 nop
|
||||
0+001c <[^>]*> 0020282[1d] move \$5,\$1
|
||||
0+0020 <[^>]*> 88a10004 lwl \$1,4\(\$5\)
|
||||
0+0024 <[^>]*> 98a10001 lwr \$1,1\(\$5\)
|
||||
0+0028 <[^>]*> 00000000 nop
|
||||
0+002c <[^>]*> 0020282[1d] move \$5,\$1
|
||||
\.\.\.
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
.*: Assembler messages:
|
||||
.*:11: Warning: Macro used \$at after "\.set noat"
|
||||
.*:12: Warning: Macro used \$at after "\.set noat"
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Source file used to test the ulw macro (harder).
|
||||
|
||||
.set noat
|
||||
|
||||
.text
|
||||
text_label:
|
||||
|
||||
ulw $4,0($5)
|
||||
ulw $4,1($5)
|
||||
|
||||
ulw $5,0($5) # warns
|
||||
ulw $5,1($5) # warns
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
Loading…
Reference in New Issue