* mmix-dis.c, mmix-opc.c: New files.
This commit is contained in:
Hans-Peter Nilsson
parent
9b19141a7d
commit
afd3097320
523
opcodes/mmix-dis.c
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523
opcodes/mmix-dis.c
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/* mmix-dis.c -- Disassemble MMIX instructions.
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Copyright (C) 2000, 2001 Free Software Foundation, Inc.
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Written by Hans-Peter Nilsson (hp@bitrange.com)
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This file is part of GDB and the GNU binutils.
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GDB and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 2,
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or (at your option) any later version.
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GDB and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "opcode/mmix.h"
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#include "dis-asm.h"
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#include "libiberty.h"
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#include "bfd.h"
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#include "opintl.h"
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#define BAD_CASE(x) \
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do \
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{ \
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fprintf (stderr, \
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_("Bad case %d (%s) in %s:%d\n"), \
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x, #x, __FILE__, __LINE__); \
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abort (); \
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} \
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while (0)
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#define FATAL_DEBUG \
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do \
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{ \
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fprintf (stderr, \
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_("Internal: Non-debugged code (test-case missing): %s:%d"), \
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__FILE__, __LINE__); \
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abort (); \
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} \
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while (0)
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#define ROUND_MODE(n) \
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((n) == 1 ? "ROUND_OFF" : (n) == 2 ? "ROUND_UP" : \
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(n) == 3 ? "ROUND_DOWN" : (n) == 4 ? "ROUND_NEAR" : \
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_("(unknown)"))
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#define INSN_IMMEDIATE_BIT (IMM_OFFSET_BIT << 24)
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#define INSN_BACKWARD_OFFSET_BIT (1 << 24)
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struct mmix_dis_info
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{
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const char *reg_name[256];
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const char *spec_reg_name[32];
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/* Waste a little memory so we don't have to allocate each separately.
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We could have an array with static contents for these, but on the
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other hand, we don't have to. */
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char basic_reg_name[256][sizeof ("$255")];
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};
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static boolean initialize_mmix_dis_info PARAMS ((struct disassemble_info *));
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static const struct mmix_opcode *get_opcode PARAMS ((unsigned long));
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/* Initialize a target-specific array in INFO. */
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static boolean
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initialize_mmix_dis_info (info)
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struct disassemble_info *info;
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{
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struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info));
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int i;
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if (minfop == NULL)
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return false;
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memset (minfop, 0, sizeof (*minfop));
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/* Initialize register names from register symbols. If there's no
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register section, then there are no register symbols. */
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if ((info->section != NULL && info->section->owner != NULL)
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|| (info->symbols != NULL
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&& info->symbols[0] != NULL
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&& bfd_asymbol_bfd (info->symbols[0]) != NULL))
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{
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bfd *abfd = info->section && info->section->owner != NULL
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? info->section->owner
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: bfd_asymbol_bfd (info->symbols[0]);
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asection *reg_section = bfd_get_section_by_name (abfd, "*REG*");
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if (reg_section != NULL)
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{
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/* The returned symcount *does* include the ending NULL. */
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long symsize = bfd_get_symtab_upper_bound (abfd);
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asymbol **syms = malloc (symsize);
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long nsyms;
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long i;
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if (syms == NULL)
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{ FATAL_DEBUG;
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free (minfop);
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return false;
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}
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nsyms = bfd_canonicalize_symtab (abfd, syms);
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/* We use the first name for a register. If this is MMO, then
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it's the name with the first sequence number, presumably the
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first in the source. */
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for (i = 0; i < nsyms && syms[i] != NULL; i++)
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{
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if (syms[i]->section == reg_section
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&& syms[i]->value < 256
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&& minfop->reg_name[syms[i]->value] == NULL)
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minfop->reg_name[syms[i]->value] = syms[i]->name;
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}
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}
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}
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/* Fill in the rest with the canonical names. */
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for (i = 0; i < 256; i++)
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if (minfop->reg_name[i] == NULL)
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{
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sprintf (minfop->basic_reg_name[i], "$%d", i);
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minfop->reg_name[i] = minfop->basic_reg_name[i];
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}
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/* We assume it's actually a one-to-one mapping of number-to-name. */
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for (i = 0; mmix_spec_regs[i].name != NULL; i++)
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minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name;
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info->private_data = (PTR) minfop;
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return true;
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}
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/* A table indexed by the first byte is constructed as we disassemble each
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tetrabyte. The contents is a pointer into mmix_insns reflecting the
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first found entry with matching match-bits and lose-bits. Further
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entries are considered one after one until the operand constraints
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match or the match-bits and lose-bits do not match. Normally a
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"further entry" will just show that there was no other match. */
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static const struct mmix_opcode *
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get_opcode (insn)
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unsigned long insn;
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{
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static const struct mmix_opcode **opcodes = NULL;
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const struct mmix_opcode *opcodep = mmix_opcodes;
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unsigned int opcode_part = (insn >> 24) & 255;
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if (opcodes == NULL)
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opcodes = xcalloc (256, sizeof (struct mmix_opcode *));
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opcodep = opcodes[opcode_part];
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if (opcodep == NULL
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|| (opcodep->match & insn) != opcodep->match
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|| (opcodep->lose & insn) != 0)
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{
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/* Search through the table. */
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for (opcodep = mmix_opcodes; opcodep->name != NULL; opcodep++)
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{
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/* FIXME: Break out this into an initialization function. */
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if ((opcodep->match & (opcode_part << 24)) == opcode_part
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&& (opcodep->lose & (opcode_part << 24)) == 0)
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opcodes[opcode_part] = opcodep;
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if ((opcodep->match & insn) == opcodep->match
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&& (opcodep->lose & insn) == 0)
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break;
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}
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}
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if (opcodep->name == NULL)
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return NULL;
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/* Check constraints. If they don't match, loop through the next opcode
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entries. */
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do
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{
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switch (opcodep->operands)
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{
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/* These have no restraint on what can be in the lower three
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bytes. */
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case mmix_operands_regs:
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case mmix_operands_reg_yz:
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case mmix_operands_regs_z_opt:
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case mmix_operands_regs_z:
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case mmix_operands_jmp:
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case mmix_operands_pushgo:
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case mmix_operands_pop:
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case mmix_operands_sync:
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case mmix_operands_x_regs_z:
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case mmix_operands_neg:
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case mmix_operands_pushj:
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case mmix_operands_regaddr:
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case mmix_operands_get:
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case mmix_operands_set:
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case mmix_operands_save:
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case mmix_operands_unsave:
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case mmix_operands_xyz_opt:
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return opcodep;
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/* For a ROUND_MODE, the middle byte must be 0..4. */
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case mmix_operands_roundregs_z:
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case mmix_operands_roundregs:
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{
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int midbyte = (insn >> 8) & 255;
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if (midbyte <= 4)
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return opcodep;
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}
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break;
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case mmix_operands_put:
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/* A "PUT". If it is "immediate", then no restrictions,
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otherwise we have to make sure the register number is < 32. */
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if ((insn & INSN_IMMEDIATE_BIT)
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|| ((insn >> 16) & 255) < 32)
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return opcodep;
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break;
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case mmix_operands_resume:
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/* Middle bytes must be zero. */
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if ((insn & 0x00ffff00) == 0)
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return opcodep;
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break;
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default:
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BAD_CASE (opcodep->operands);
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}
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opcodep++;
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}
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while ((opcodep->match & insn) == opcodep->match
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&& (opcodep->lose & insn) == 0);
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/* If we got here, we had no match. */
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return NULL;
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}
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/* The main disassembly function. */
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int
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print_insn_mmix (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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unsigned char buffer[4];
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unsigned long insn;
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unsigned int x, y, z;
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const struct mmix_opcode *opcodep;
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int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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struct mmix_dis_info *minfop;
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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/* FIXME: Is -1 suitable? */
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if (info->private_data == NULL
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&& ! initialize_mmix_dis_info (info))
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return -1;
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minfop = (struct mmix_dis_info *) info->private_data;
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x = buffer[1];
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y = buffer[2];
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z = buffer[3];
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insn = bfd_getb32 (buffer);
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opcodep = get_opcode (insn);
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if (opcodep == NULL)
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{
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(*info->fprintf_func) (info->stream, _("*unknown*"));
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return 4;
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}
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(*info->fprintf_func) (info->stream, "%s ", opcodep->name);
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/* Present bytes in the order they are laid out in memory. */
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info->display_endian = BFD_ENDIAN_BIG;
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info->insn_info_valid = 1;
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info->bytes_per_chunk = 4;
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info->branch_delay_insns = 0;
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info->target = 0;
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switch (opcodep->type)
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{
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case mmix_type_normal:
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case mmix_type_memaccess_block:
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info->insn_type = dis_nonbranch;
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break;
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case mmix_type_branch:
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info->insn_type = dis_branch;
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break;
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case mmix_type_condbranch:
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info->insn_type = dis_condbranch;
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break;
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case mmix_type_memaccess_octa:
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info->insn_type = dis_dref;
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info->data_size = 8;
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break;
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case mmix_type_memaccess_tetra:
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info->insn_type = dis_dref;
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info->data_size = 4;
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break;
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case mmix_type_memaccess_wyde:
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info->insn_type = dis_dref;
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info->data_size = 2;
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break;
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case mmix_type_memaccess_byte:
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info->insn_type = dis_dref;
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info->data_size = 1;
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break;
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case mmix_type_jsr:
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info->insn_type = dis_jsr;
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break;
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default:
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BAD_CASE(opcodep->type);
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}
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switch (opcodep->operands)
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{
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case mmix_operands_regs:
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/* All registers: "$X,$Y,$Z". */
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(*info->fprintf_func) (info->stream, "%s,%s,%s",
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minfop->reg_name[x],
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minfop->reg_name[y],
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minfop->reg_name[z]);
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break;
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case mmix_operands_reg_yz:
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/* Like SETH - "$X,YZ". */
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(*info->fprintf_func) (info->stream, "%s,0x%x",
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minfop->reg_name[x], y * 256 + z);
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break;
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case mmix_operands_regs_z_opt:
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case mmix_operands_regs_z:
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case mmix_operands_pushgo:
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/* The regular "$X,$Y,$Z|Z". */
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if (insn & INSN_IMMEDIATE_BIT)
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(*info->fprintf_func) (info->stream, "%s,%s,%d",
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minfop->reg_name[x], minfop->reg_name[y], z);
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else
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(*info->fprintf_func) (info->stream, "%s,%s,%s",
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minfop->reg_name[x],
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minfop->reg_name[y],
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minfop->reg_name[z]);
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break;
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case mmix_operands_jmp:
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/* Address; only JMP. */
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{
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bfd_signed_vma offset = (x * 65536 + y * 256 + z) * 4;
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if (insn & INSN_BACKWARD_OFFSET_BIT)
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offset -= (256 * 65536) * 4;
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info->target = memaddr + offset;
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(*info->print_address_func) (memaddr + offset, info);
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}
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break;
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case mmix_operands_roundregs_z:
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/* Two registers, like FLOT, possibly with rounding: "$X,$Z|Z"
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"$X,ROUND_MODE,$Z|Z". */
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if (y != 0)
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{
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if (insn & INSN_IMMEDIATE_BIT)
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(*info->fprintf_func) (info->stream, "%s,%s,%d",
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minfop->reg_name[x],
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ROUND_MODE (y), z);
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else
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(*info->fprintf_func) (info->stream, "%s,%s,%s",
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minfop->reg_name[x],
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ROUND_MODE (y),
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minfop->reg_name[z]);
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}
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else
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{
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if (insn & INSN_IMMEDIATE_BIT)
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(*info->fprintf_func) (info->stream, "%s,%d",
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minfop->reg_name[x], z);
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else
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(*info->fprintf_func) (info->stream, "%s,%s",
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minfop->reg_name[x],
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minfop->reg_name[z]);
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}
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break;
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case mmix_operands_pop:
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/* Like POP - "X,YZ". */
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(*info->fprintf_func) (info->stream, "%d,%d", x, y*256 + z);
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break;
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case mmix_operands_roundregs:
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/* Two registers, possibly with rounding: "$X,$Z" or
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"$X,ROUND_MODE,$Z". */
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if (y != 0)
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(*info->fprintf_func) (info->stream, "%s,%s,%s",
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minfop->reg_name[x],
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ROUND_MODE (y),
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minfop->reg_name[z]);
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else
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(*info->fprintf_func) (info->stream, "%s,%s",
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minfop->reg_name[x],
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minfop->reg_name[z]);
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break;
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case mmix_operands_sync:
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/* Like SYNC - "XYZ". */
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(*info->fprintf_func) (info->stream, "%u",
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x * 65536 + y * 256 + z);
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break;
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case mmix_operands_x_regs_z:
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/* Like SYNCD - "X,$Y,$Z|Z". */
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if (insn & INSN_IMMEDIATE_BIT)
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(*info->fprintf_func) (info->stream, "%d,%s,%d",
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x, minfop->reg_name[y], z);
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else
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(*info->fprintf_func) (info->stream, "%d,%s,%s",
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x, minfop->reg_name[y],
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minfop->reg_name[z]);
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break;
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case mmix_operands_neg:
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/* Like NEG and NEGU - "$X,Y,$Z|Z". */
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if (insn & INSN_IMMEDIATE_BIT)
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(*info->fprintf_func) (info->stream, "%s,%d,%d",
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minfop->reg_name[x], y, z);
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else
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(*info->fprintf_func) (info->stream, "%s,%d,%s",
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minfop->reg_name[x], y,
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minfop->reg_name[z]);
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break;
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case mmix_operands_pushj:
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case mmix_operands_regaddr:
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/* Like GETA or branches - "$X,Address". */
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{
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bfd_signed_vma offset = (y * 256 + z) * 4;
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if (insn & INSN_BACKWARD_OFFSET_BIT)
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offset -= 65536 * 4;
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info->target = memaddr + offset;
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(*info->fprintf_func) (info->stream, "%s,", minfop->reg_name[x]);
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(*info->print_address_func) (memaddr + offset, info);
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}
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break;
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case mmix_operands_get:
|
||||
/* GET - "X,spec_reg". */
|
||||
(*info->fprintf_func) (info->stream, "%s,%s",
|
||||
minfop->reg_name[x],
|
||||
minfop->spec_reg_name[z]);
|
||||
break;
|
||||
|
||||
case mmix_operands_put:
|
||||
/* PUT - "spec_reg,$Z|Z". */
|
||||
if (insn & INSN_IMMEDIATE_BIT)
|
||||
(*info->fprintf_func) (info->stream, "%s,%d",
|
||||
minfop->spec_reg_name[x], z);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%s,%s",
|
||||
minfop->spec_reg_name[x],
|
||||
minfop->reg_name[z]);
|
||||
break;
|
||||
|
||||
case mmix_operands_set:
|
||||
/* Two registers, "$X,$Y". */
|
||||
(*info->fprintf_func) (info->stream, "%s,%s",
|
||||
minfop->reg_name[x],
|
||||
minfop->reg_name[y]);
|
||||
break;
|
||||
|
||||
case mmix_operands_save:
|
||||
/* SAVE - "$X,0". */
|
||||
(*info->fprintf_func) (info->stream, "%s,0", minfop->reg_name[x]);
|
||||
break;
|
||||
|
||||
case mmix_operands_unsave:
|
||||
/* UNSAVE - "0,$Z". */
|
||||
(*info->fprintf_func) (info->stream, "0,%s", minfop->reg_name[z]);
|
||||
break;
|
||||
|
||||
case mmix_operands_xyz_opt:
|
||||
/* Like SWYM or TRAP - "X,Y,Z". */
|
||||
(*info->fprintf_func) (info->stream, "%d,%d,%d", x, y, z);
|
||||
break;
|
||||
|
||||
case mmix_operands_resume:
|
||||
/* Just "Z", like RESUME. */
|
||||
(*info->fprintf_func) (info->stream, "%d", z);
|
||||
break;
|
||||
|
||||
default:
|
||||
(*info->fprintf_func) (info->stream, _("*unknown operands type: %d*"),
|
||||
opcodep->operands);
|
||||
break;
|
||||
}
|
||||
|
||||
return 4;
|
||||
}
|
||||
340
opcodes/mmix-opc.c
Normal file
340
opcodes/mmix-opc.c
Normal file
@ -0,0 +1,340 @@
|
||||
/* mmix-opc.c -- MMIX opcode table
|
||||
Copyright (C) 2001 Free Software Foundation, Inc.
|
||||
Written by Hans-Peter Nilsson (hp@bitrange.com)
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version 2,
|
||||
or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#include <stdio.h>
|
||||
#include "opcode/mmix.h"
|
||||
#include "symcat.h"
|
||||
|
||||
/* Register-name-table for special registers. */
|
||||
const struct mmix_spec_reg mmix_spec_regs[] =
|
||||
{
|
||||
/* Keep rJ at top; it's the most frequently used one. */
|
||||
{"rJ", 4},
|
||||
{"rA", 21},
|
||||
{"rB", 0},
|
||||
{"rC", 8},
|
||||
{"rD", 1},
|
||||
{"rE", 2},
|
||||
{"rF", 22},
|
||||
{"rG", 19},
|
||||
{"rH", 3},
|
||||
{"rI", 12},
|
||||
{"rK", 15},
|
||||
{"rL", 20},
|
||||
{"rM", 5},
|
||||
{"rN", 9},
|
||||
{"rO", 10},
|
||||
{"rP", 23},
|
||||
{"rQ", 16},
|
||||
{"rR", 6},
|
||||
{"rS", 11},
|
||||
{"rT", 13},
|
||||
{"rU", 17},
|
||||
{"rV", 18},
|
||||
{"rW", 24},
|
||||
{"rX", 25},
|
||||
{"rY", 26},
|
||||
{"rZ", 27},
|
||||
{"rBB", 7},
|
||||
{"rTT", 14},
|
||||
{"rWW", 28},
|
||||
{"rXX", 29},
|
||||
{"rYY", 30},
|
||||
{"rZZ", 31},
|
||||
{NULL, 0}
|
||||
};
|
||||
|
||||
/* Opcode-table. In order to cut down on redundant contents, we use helper
|
||||
macros. */
|
||||
|
||||
/* All bits in the opcode-byte are significant. Add "| ..." expressions
|
||||
to add zero-bits. */
|
||||
#undef O
|
||||
#define O(m) ((m) << 24), ((~(m) & 255) << 24)
|
||||
|
||||
/* Bits 7..1 of the opcode are significant. */
|
||||
#undef Z
|
||||
#define Z(m) ((m) << 24), ((~(m) & 254) << 24)
|
||||
|
||||
/* For easier overview of the table. */
|
||||
#define N mmix_type_normal
|
||||
#define B mmix_type_branch
|
||||
#define C mmix_type_condbranch
|
||||
#define MB mmix_type_memaccess_byte
|
||||
#define MW mmix_type_memaccess_wyde
|
||||
#define MT mmix_type_memaccess_tetra
|
||||
#define MO mmix_type_memaccess_octa
|
||||
#define M mmix_type_memaccess_block
|
||||
#define J mmix_type_jsr
|
||||
#define P mmix_type_pseudo
|
||||
|
||||
#define OP(y) XCONCAT2 (mmix_operands_,y)
|
||||
|
||||
/* Groups of instructions specified here must, if all are matching the
|
||||
same instruction, be consecutive, in order more-specific to
|
||||
less-specific match. */
|
||||
|
||||
const struct mmix_opcode mmix_opcodes[] =
|
||||
{
|
||||
{"trap", O (0), OP (xyz_opt), J},
|
||||
{"fcmp", O (1), OP (regs), N},
|
||||
{"flot", Z (8), OP (roundregs_z), N},
|
||||
|
||||
{"fun", O (2), OP (regs), N},
|
||||
{"feql", O (3), OP (regs), N},
|
||||
{"flotu", Z (10), OP (roundregs_z), N},
|
||||
|
||||
{"fadd", O (4), OP (regs), N},
|
||||
{"fix", O (5), OP (roundregs), N},
|
||||
{"sflot", Z (12), OP (roundregs_z), N},
|
||||
|
||||
{"fsub", O (6), OP (regs), N},
|
||||
{"fixu", O (7), OP (roundregs), N},
|
||||
{"sflotu", Z (14), OP (roundregs_z), N},
|
||||
|
||||
{"fmul", O (16), OP (regs), N},
|
||||
{"fcmpe", O (17), OP (regs), N},
|
||||
{"mul", Z (24), OP (regs_z), N},
|
||||
|
||||
{"fune", O (18), OP (regs), N},
|
||||
{"feqle", O (19), OP (regs), N},
|
||||
{"mulu", Z (26), OP (regs_z), N},
|
||||
|
||||
{"fdiv", O (20), OP (regs), N},
|
||||
{"fsqrt", O (21), OP (roundregs), N},
|
||||
{"div", Z (28), OP (regs_z), N},
|
||||
|
||||
{"frem", O (22), OP (regs), N},
|
||||
{"fint", O (23), OP (roundregs), N},
|
||||
{"divu", Z (30), OP (regs_z), N},
|
||||
|
||||
{"add", Z (0x20), OP (regs_z), N},
|
||||
{"2addu", Z (0x28), OP (regs_z), N},
|
||||
|
||||
{"addu", Z (0x22), OP (regs_z), N},
|
||||
/* Synonym for ADDU. Put after ADDU, since we don't prefer it for
|
||||
disassembly. It's supposed to be used for addresses, so we make it
|
||||
a memory block reference for purposes of assembly. */
|
||||
{"lda", Z (0x22), OP (regs_z_opt), M},
|
||||
{"4addu", Z (0x2a), OP (regs_z), N},
|
||||
|
||||
{"sub", Z (0x24), OP (regs_z), N},
|
||||
{"8addu", Z (0x2c), OP (regs_z), N},
|
||||
|
||||
{"subu", Z (0x26), OP (regs_z), N},
|
||||
{"16addu", Z (0x2e), OP (regs_z), N},
|
||||
|
||||
{"cmp", Z (0x30), OP (regs_z), N},
|
||||
{"sl", Z (0x38), OP (regs_z), N},
|
||||
|
||||
{"cmpu", Z (0x32), OP (regs_z), N},
|
||||
{"slu", Z (0x3a), OP (regs_z), N},
|
||||
|
||||
{"neg", Z (0x34), OP (neg), N},
|
||||
{"sr", Z (0x3c), OP (regs_z), N},
|
||||
|
||||
{"negu", Z (0x36), OP (neg), N},
|
||||
{"sru", Z (0x3e), OP (regs_z), N},
|
||||
|
||||
{"bn", Z (0x40), OP (regaddr), C},
|
||||
{"bnn", Z (0x48), OP (regaddr), C},
|
||||
|
||||
{"bz", Z (0x42), OP (regaddr), C},
|
||||
{"bnz", Z (0x4a), OP (regaddr), C},
|
||||
|
||||
{"bp", Z (0x44), OP (regaddr), C},
|
||||
{"bnp", Z (0x4c), OP (regaddr), C},
|
||||
|
||||
{"bod", Z (0x46), OP (regaddr), C},
|
||||
{"bev", Z (0x4e), OP (regaddr), C},
|
||||
|
||||
{"pbn", Z (0x50), OP (regaddr), C},
|
||||
{"pbnn", Z (0x58), OP (regaddr), C},
|
||||
|
||||
{"pbz", Z (0x52), OP (regaddr), C},
|
||||
{"pbnz", Z (0x5a), OP (regaddr), C},
|
||||
|
||||
{"pbp", Z (0x54), OP (regaddr), C},
|
||||
{"pbnp", Z (0x5c), OP (regaddr), C},
|
||||
|
||||
{"pbod", Z (0x56), OP (regaddr), C},
|
||||
{"pbev", Z (0x5e), OP (regaddr), C},
|
||||
|
||||
{"csn", Z (0x60), OP (regs_z), N},
|
||||
{"csnn", Z (0x68), OP (regs_z), N},
|
||||
|
||||
{"csz", Z (0x62), OP (regs_z), N},
|
||||
{"csnz", Z (0x6a), OP (regs_z), N},
|
||||
|
||||
{"csp", Z (0x64), OP (regs_z), N},
|
||||
{"csnp", Z (0x6c), OP (regs_z), N},
|
||||
|
||||
{"csod", Z (0x66), OP (regs_z), N},
|
||||
{"csev", Z (0x6e), OP (regs_z), N},
|
||||
|
||||
{"zsn", Z (0x70), OP (regs_z), N},
|
||||
{"zsnn", Z (0x78), OP (regs_z), N},
|
||||
|
||||
{"zsz", Z (0x72), OP (regs_z), N},
|
||||
{"zsnz", Z (0x7a), OP (regs_z), N},
|
||||
|
||||
{"zsp", Z (0x74), OP (regs_z), N},
|
||||
{"zsnp", Z (0x7c), OP (regs_z), N},
|
||||
|
||||
{"zsod", Z (0x76), OP (regs_z), N},
|
||||
{"zsev", Z (0x7e), OP (regs_z), N},
|
||||
|
||||
{"ldb", Z (0x80), OP (regs_z_opt), MB},
|
||||
{"ldt", Z (0x88), OP (regs_z_opt), MT},
|
||||
|
||||
{"ldbu", Z (0x82), OP (regs_z_opt), MB},
|
||||
{"ldtu", Z (0x8a), OP (regs_z_opt), MT},
|
||||
|
||||
{"ldw", Z (0x84), OP (regs_z_opt), MW},
|
||||
{"ldo", Z (0x8c), OP (regs_z_opt), MO},
|
||||
|
||||
{"ldwu", Z (0x86), OP (regs_z_opt), MW},
|
||||
{"ldou", Z (0x8e), OP (regs_z_opt), MO},
|
||||
|
||||
{"ldsf", Z (0x90), OP (regs_z_opt), MT},
|
||||
|
||||
/* This doesn't seem to access memory, just the TLB. */
|
||||
{"ldvts", Z (0x98), OP (regs_z_opt), M},
|
||||
|
||||
{"ldht", Z (0x92), OP (regs_z_opt), MT},
|
||||
|
||||
/* Neither does this per-se. */
|
||||
{"preld", Z (0x9a), OP (x_regs_z), N},
|
||||
|
||||
{"cswap", Z (0x94), OP (regs_z_opt), MO},
|
||||
{"prego", Z (0x9c), OP (x_regs_z), N},
|
||||
|
||||
{"ldunc", Z (0x96), OP (regs_z_opt), MO},
|
||||
{"go", Z (0x9e), OP (regs_z_opt), B},
|
||||
|
||||
{"stb", Z (0xa0), OP (regs_z_opt), MB},
|
||||
{"stt", Z (0xa8), OP (regs_z_opt), MT},
|
||||
|
||||
{"stbu", Z (0xa2), OP (regs_z_opt), MB},
|
||||
{"sttu", Z (0xaa), OP (regs_z_opt), MT},
|
||||
|
||||
{"stw", Z (0xa4), OP (regs_z_opt), MW},
|
||||
{"sto", Z (0xac), OP (regs_z_opt), MO},
|
||||
|
||||
{"stwu", Z (0xa6), OP (regs_z_opt), MW},
|
||||
{"stou", Z (0xae), OP (regs_z_opt), MO},
|
||||
|
||||
{"stsf", Z (0xb0), OP (regs_z_opt), MT},
|
||||
{"syncd", Z (0xb8), OP (x_regs_z), M},
|
||||
|
||||
{"stht", Z (0xb2), OP (regs_z_opt), MT},
|
||||
{"prest", Z (0xba), OP (x_regs_z), M},
|
||||
|
||||
{"stco", Z (0xb4), OP (x_regs_z), MO},
|
||||
{"syncid", Z (0xbc), OP (x_regs_z), M},
|
||||
|
||||
{"stunc", Z (0xb6), OP (regs_z_opt), MO},
|
||||
{"pushgo", Z (0xbe), OP (pushgo), J},
|
||||
|
||||
/* Synonym for OR with a zero Z. */
|
||||
{"set", O (0xc1)
|
||||
| 0xff, OP (set), N},
|
||||
|
||||
{"or", Z (0xc0), OP (regs_z), N},
|
||||
{"and", Z (0xc8), OP (regs_z), N},
|
||||
|
||||
{"orn", Z (0xc2), OP (regs_z), N},
|
||||
{"andn", Z (0xca), OP (regs_z), N},
|
||||
|
||||
{"nor", Z (0xc4), OP (regs_z), N},
|
||||
{"nand", Z (0xcc), OP (regs_z), N},
|
||||
|
||||
{"xor", Z (0xc6), OP (regs_z), N},
|
||||
{"nxor", Z (0xce), OP (regs_z), N},
|
||||
|
||||
{"bdif", Z (0xd0), OP (regs_z), N},
|
||||
{"mux", Z (0xd8), OP (regs_z), N},
|
||||
|
||||
{"wdif", Z (0xd2), OP (regs_z), N},
|
||||
{"sadd", Z (0xda), OP (regs_z), N},
|
||||
|
||||
{"tdif", Z (0xd4), OP (regs_z), N},
|
||||
{"mor", Z (0xdc), OP (regs_z), N},
|
||||
|
||||
{"odif", Z (0xd6), OP (regs_z), N},
|
||||
{"mxor", Z (0xde), OP (regs_z), N},
|
||||
|
||||
{"seth", O (0xe0), OP (reg_yz), N},
|
||||
{"setmh", O (0xe1), OP (reg_yz), N},
|
||||
{"orh", O (0xe8), OP (reg_yz), N},
|
||||
{"ormh", O (0xe9), OP (reg_yz), N},
|
||||
|
||||
{"setml", O (0xe2), OP (reg_yz), N},
|
||||
{"setl", O (0xe3), OP (reg_yz), N},
|
||||
{"orml", O (0xea), OP (reg_yz), N},
|
||||
{"orl", O (0xeb), OP (reg_yz), N},
|
||||
|
||||
{"inch", O (0xe4), OP (reg_yz), N},
|
||||
{"incmh", O (0xe5), OP (reg_yz), N},
|
||||
{"andnh", O (0xec), OP (reg_yz), N},
|
||||
{"andnmh", O (0xed), OP (reg_yz), N},
|
||||
|
||||
{"incml", O (0xe6), OP (reg_yz), N},
|
||||
{"incl", O (0xe7), OP (reg_yz), N},
|
||||
{"andnml", O (0xee), OP (reg_yz), N},
|
||||
{"andnl", O (0xef), OP (reg_yz), N},
|
||||
|
||||
{"jmp", Z (0xf0), OP (jmp), B},
|
||||
{"pop", O (0xf8), OP (pop), B},
|
||||
{"resume", O (0xf9)
|
||||
| 0xffff00, OP (resume), B},
|
||||
|
||||
{"pushj", Z (0xf2), OP (pushj), J},
|
||||
{"save", O (0xfa)
|
||||
| 0xffff, OP (save), M},
|
||||
{"unsave", O (0xfb)
|
||||
| 0xffff00, OP (unsave), M},
|
||||
|
||||
{"geta", Z (0xf4), OP (regaddr), N},
|
||||
{"sync", O (0xfc), OP (sync), N},
|
||||
{"swym", O (0xfd), OP (xyz_opt), N},
|
||||
|
||||
{"put", Z (0xf6) | 0xff00, OP (put), N},
|
||||
{"get", O (0xfe) | 0xffe0, OP (get), N},
|
||||
{"trip", O (0xff), OP (xyz_opt), J},
|
||||
|
||||
/* We have mmixal pseudos in the ordinary instruction table so we can
|
||||
avoid the "set" vs. ".set" ambiguity that would be the effect if we
|
||||
had pseudos handled "normally" and defined NO_PSEUDO_DOT.
|
||||
|
||||
Note that IS and GREG are handled fully by md_start_line_hook, so
|
||||
they're not here. */
|
||||
{"loc", ~0, ~0, OP (loc), P},
|
||||
{"prefix", ~0, ~0, OP (prefix), P},
|
||||
{"byte", ~0, ~0, OP (byte), P},
|
||||
{"wyde", ~0, ~0, OP (wyde), P},
|
||||
{"tetra", ~0, ~0, OP (tetra), P},
|
||||
{"octa", ~0, ~0, OP (octa), P},
|
||||
{"local", ~0, ~0, OP (local), P},
|
||||
{"bspec", ~0, ~0, OP (bspec), P},
|
||||
{"espec", ~0, ~0, OP (espec), P},
|
||||
|
||||
{NULL, ~0, ~0, OP (none), N}
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user