* Makefile.am (CGENFILES): Update.
* Makefile.in: Regenerate.
* cgen-asm.in (insert_normal): Result is error message now.
Validate value to be inserted.
(insert_insn_normal): Result is error message now.
(@arch@_cgen_assemble_insn): Update.
* cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max
arguments. Don't perform validation here.
* m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate.
This commit is contained in:
Doug Evans
parent
652af042db
commit
b02643b554
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@ -1,3 +1,15 @@
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Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com>
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* Makefile.am (CGENFILES): Update.
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* Makefile.in: Regenerate.
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* cgen-asm.in (insert_normal): Result is error message now.
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Validate value to be inserted.
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(insert_insn_normal): Result is error message now.
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(@arch@_cgen_assemble_insn): Update.
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* cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max
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arguments. Don't perform validation here.
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* m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate.
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Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com>
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* cgen-opc.in (@arch@_cgen_get_insn_operands): Handle empty
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@ -119,7 +119,8 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
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If non-null INS is the insn table entry.
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Otherwise INSN_VALUE is examined to compute it.
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LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
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INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
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INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
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in.
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The result a pointer to the insn table entry, or NULL if the instruction
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wasn't recognized. */
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@ -711,7 +712,7 @@ static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
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};
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static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
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{ INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
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{ INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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{ 0 }
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};
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@ -732,7 +733,7 @@ static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
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static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
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{ 0 }
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};
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@ -858,14 +859,14 @@ static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
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};
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static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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{ 0 }
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};
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static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
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{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
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{ INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
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{ OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
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{ 0 }
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};
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@ -1011,8 +1012,6 @@ static const CGEN_SYNTAX syntax_table[] =
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/* 51 */ { OP, ' ', '#', 137, 0 },
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/* <op> $uimm4 */
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/* 52 */ { OP, ' ', 137, 0 },
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/* <op> $dr,$src2 */
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/* 53 */ { OP, ' ', 130, ',', 132, 0 },
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};
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#undef OP
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@ -1115,13 +1114,13 @@ static const CGEN_FORMAT format_table[] =
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/* 46 */ { 16, 16, 0xf0ff },
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
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/* 47 */ { 16, 16, 0xf0f3 },
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr SI)(dr SI) */
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr USI)(dr SI) */
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/* 48 */ { 16, 16, 0xf0f0 },
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/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
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/* 49 */ { 16, 16, 0xf0ff },
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/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
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/* 50 */ { 16, 16, 0xf0f3 },
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/* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr SI) */
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/* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr USI) */
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/* 51 */ { 16, 16, 0xf0f0 },
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/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
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/* 52 */ { 16, 16, 0xffff },
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@ -1167,9 +1166,9 @@ static const CGEN_FORMAT format_table[] =
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/* 72 */ { 16, 16, 0xf0ff },
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
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/* 73 */ { 16, 16, 0xf0ff },
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(src2 SI)(dr SI) */
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(sr SI)(dr SI) */
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/* 74 */ { 32, 32, 0xf0f0ffff },
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(condbit UBI)(src2 SI)(dr SI) */
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/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */
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/* 75 */ { 32, 32, 0xf0f0ffff },
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/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
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/* 76 */ { 16, 16, 0xffff },
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@ -2466,28 +2465,28 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
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{ 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
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},
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/* start-sanitize-m32rx */
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/* satb $dr,$src2 */
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/* satb $dr,$sr */
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{
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{ 1, 1, 1, 1 },
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"satb", "satb", SYN (53), FMT (74), 0x80000100,
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"satb", "satb", SYN (0), FMT (74), 0x80000100,
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& fmt_74_satb_ops[0],
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{ 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
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},
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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/* sath $dr,$src2 */
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/* sath $dr,$sr */
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{
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{ 1, 1, 1, 1 },
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"sath", "sath", SYN (53), FMT (74), 0x80000200,
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"sath", "sath", SYN (0), FMT (74), 0x80000200,
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& fmt_74_satb_ops[0],
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{ 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
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},
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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/* sat $dr,$src2 */
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/* sat $dr,$sr */
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{
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{ 1, 1, 1, 1 },
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"sat", "sat", SYN (53), FMT (75), 0x80000000,
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"sat", "sat", SYN (0), FMT (75), 0x80000000,
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& fmt_75_sat_ops[0],
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{ 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
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},
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