opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific dmfc2 and dmtc2 before the architecture-level variants. gas/testsuite/ * gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2. * gas/mips/octeon.d: Update. * gas/mips/octeon-ill.l: Update error message.
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@ -1,3 +1,9 @@
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2009-02-18 Adam Nemet <anemet@caviumnetworks.com>
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* gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2.
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* gas/mips/octeon.d: Update.
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* gas/mips/octeon-ill.l: Update error message.
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2009-02-16 Nick Clifton <nickc@redhat.com>
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* gas/mips/e32-rel2.d: Adjust expected output to remove the 0x4000
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@ -28,11 +28,11 @@
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.*:41: Error: opcode not supported on this processor.*
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.*:42: Error: opcode not supported on this processor.*
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.*:43: Error: opcode not supported on this processor.*
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.*:45: Error: expression out of range
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.*:46: Error: expression out of range
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.*:47: Error: register value used as expression
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.*:45: Error: illegal operands `dmfc2 \$2,0x10000'
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.*:46: Error: illegal operands `dmtc2 \$2,0x12345'
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.*:47: Error: illegal operands `dmfc2 \$9,\$12'
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.*:48: Error: illegal operands `dmfc2 \$4,\$15,4'
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.*:49: Error: register value used as expression
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.*:49: Error: illegal operands `dmtc2 \$16,\$8'
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.*:50: Error: illegal operands `dmtc2 \$22,\$7,\$4'
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.*:52: Error: Improper size \(32\)
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.*:54: Error: Improper position \(32\)
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@ -46,7 +46,11 @@ Disassembly of section .text:
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.*: 41606000 di
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.*: 41606020 ei
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.*: 48230084 dmfc2 \$3,0x84
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.*: 48260800 dmfc2 \$6,0x800
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.*: 482c0001 dmfc2 \$12,0x1
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.*: 48a84200 dmtc2 \$8,0x4200
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.*: 48a72000 dmtc2 \$7,0x2000
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.*: 48a20004 dmtc2 \$2,0x4
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.*: 73400008 mtm0 \$26
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.*: 7260000c mtm1 \$19
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.*: 7240000d mtm2 \$18
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@ -47,7 +47,11 @@ foo:
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di
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ei
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dmfc2 $3,0x84
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dmfc2 $6,0x800
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dmfc2 $12,0x1
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dmtc2 $8,0x4200
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dmtc2 $7,0x2000
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dmtc2 $2,0x4
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mtm0 $26
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mtm1 $19
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@ -1,3 +1,8 @@
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2009-02-18 Adam Nemet <anemet@caviumnetworks.com>
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* mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific
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dmfc2 and dmtc2 before the architecture-level variants.
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2009-02-18 Pierre Muller <muller@ics.u-strasbg.fr>
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* fr30-opc.c: Regenerate.
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@ -1506,12 +1506,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
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{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
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{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
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{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
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{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
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{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
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{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
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{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
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{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
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{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
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{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
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{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
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{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
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{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
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