opcodes:
From Robin Getz <robin.getz@analog.com> * bfin-dis.c (bu32): Typedef. (enum const_forms_t): Add c_uimm32 and c_huimm32. (constant_formats[]): Add uimm32 and huimm16. (fmtconst_val): New. (uimm32): Define. (huimm32): Define. (imm16_val): Define. (luimm16_val): Define. (struct saved_state): Define. (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. (get_allreg): New. (decode_LDIMMhalf_0): Print out the whole register value. gas/testsuite: From Jie Zhang <jie.zhang@analog.com> * gas/bfin/load.d: Update.
This commit is contained in:
Bernd Schmidt
parent
a5defcdc21
commit
b21c9cb440
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@ -1,3 +1,8 @@
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2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
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From Jie Zhang <jie.zhang@analog.com>
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* gas/bfin/load.d: Update.
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2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
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* gas/s390/zarch-z10.d: New file.
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@ -5,17 +5,17 @@
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Disassembly of section .text:
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00000000 <load_immediate>:
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0: 17 e1 ff ff M3.L=ffff.*
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4: 1a e1 fe ff B2.L=fffe.*
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0: 17 e1 ff ff M3.L=0xffff.*
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4: 1a e1 fe ff B2.L=0xfffe.*
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8: 0e e1 00 00 SP.L=0.*
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c: 0f e1 dc fe FP.L=fedc.*
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10: 40 e1 02 00 R0.H=0x2;
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14: 4d e1 20 00 P5.H=20.*
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18: 52 e1 04 f2 I2.H=f204.*
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1c: 59 e1 40 00 B1.H=40.*
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20: 5c e1 ff ff L0.H=ffff.*
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24: 45 e1 00 00 R5.H=0x0;
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28: 5a e1 00 00 B2.H=0 <load_immediate>;
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c: 0f e1 dc fe FP.L=0xfedc.*
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10: 40 e1 02 00 R0.H=0x2.*
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14: 4d e1 20 00 P5.H=0x20.*
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18: 52 e1 04 f2 I2.H=0xf204.*
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1c: 59 e1 40 00 B1.H=0x40.*
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20: 5c e1 ff ff L0.H=0xffff.*
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24: 45 e1 00 00 R5.H=0x0.*
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28: 5a e1 00 00 B2.H=0x0.*
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2c: 8f e1 20 ff FP=ff20.*
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30: 9e e1 20 00 L2=20.*
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34: 85 e1 00 00 R5=0 <load_immediate>\(Z\);
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@ -1,3 +1,21 @@
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2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
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From Robin Getz <robin.getz@analog.com>
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* bfin-dis.c (bu32): Typedef.
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(enum const_forms_t): Add c_uimm32 and c_huimm32.
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(constant_formats[]): Add uimm32 and huimm16.
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(fmtconst_val): New.
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(uimm32): Define.
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(huimm32): Define.
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(imm16_val): Define.
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(luimm16_val): Define.
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(struct saved_state): Define.
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(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
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A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
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LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
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(get_allreg): New.
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(decode_LDIMMhalf_0): Print out the whole register value.
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2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
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* aclocal.m4: Regenerate.
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@ -51,13 +51,15 @@ typedef long TIword;
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#include "dis-asm.h"
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typedef unsigned int bu32;
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typedef enum
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{
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c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
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c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6,
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c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
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c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
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c_uimm16, c_pcrel24,
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c_uimm16, c_pcrel24, c_uimm32, c_huimm32,
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} const_forms_t;
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static struct
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@ -106,7 +108,9 @@ static struct
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{ "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0},
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{ "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0},
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{ "uimm16", 16, 0, 0, 0, 0, 0, 0, 0},
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{ "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0}
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{ "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0},
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{ "uimm32", 32, 0, 0, 0, 0, 0, 0, 0},
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{ "huimm16", 32, 1, 0, 0, 0, 0, 0, 0}
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};
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int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
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@ -153,6 +157,37 @@ fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
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return buf;
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}
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static bu32
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fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
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{
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if (0 && constant_formats[cf].reloc)
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{
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bu32 ea = (((constant_formats[cf].pcrel
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? SIGNEXTEND (x, constant_formats[cf].nbits)
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: x) + constant_formats[cf].offset)
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<< constant_formats[cf].scale);
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if (constant_formats[cf].pcrel)
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ea += pc;
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return ea;
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}
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/* Negative constants have an implied sign bit. */
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if (constant_formats[cf].negative)
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{
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int nb = constant_formats[cf].nbits + 1;
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x = x | (1 << constant_formats[cf].nbits);
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x = SIGNEXTEND (x, nb);
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}
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else if (constant_formats[cf].issigned)
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x = SIGNEXTEND (x, constant_formats[cf].nbits);
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x += constant_formats[cf].offset;
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x <<= constant_formats[cf].scale;
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return x;
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}
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enum machine_registers
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{
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REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
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@ -396,6 +431,10 @@ static enum machine_registers decode_allregs[] =
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#define imm8(x) fmtconst (c_imm8, x, 0, outf)
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#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
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#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
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#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
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#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
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#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
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#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
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/* (arch.pm)arch_disassembler_functions. */
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#ifndef OUTS
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@ -565,6 +604,95 @@ decode_optmode (int mod, int MM, disassemble_info *outf)
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OUTS (outf, ")");
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}
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struct saved_state
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{
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bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
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bu32 a0x, a0w, a1x, a1w;
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bu32 lt[2], lc[2], lb[2];
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int ac0, ac0_copy, ac1, an, aq;
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int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
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int rnd_mod;
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int v_internal;
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bu32 pc, rets;
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int ticks;
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int insts;
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int exception;
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int end_of_registers;
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int msize;
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unsigned char *memory;
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unsigned long bfd_mach;
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} saved_state;
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#define DREG(x) (saved_state.dpregs[x])
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#define GREG(x,i) DPREG ((x) | (i << 3))
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#define DPREG(x) (saved_state.dpregs[x])
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#define DREG(x) (saved_state.dpregs[x])
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#define PREG(x) (saved_state.dpregs[x + 8])
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#define SPREG PREG (6)
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#define FPREG PREG (7)
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#define IREG(x) (saved_state.iregs[x])
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#define MREG(x) (saved_state.mregs[x])
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#define BREG(x) (saved_state.bregs[x])
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#define LREG(x) (saved_state.lregs[x])
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#define A0XREG (saved_state.a0x)
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#define A0WREG (saved_state.a0w)
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#define A1XREG (saved_state.a1x)
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#define A1WREG (saved_state.a1w)
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#define CCREG (saved_state.cc)
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#define LC0REG (saved_state.lc[0])
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#define LT0REG (saved_state.lt[0])
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#define LB0REG (saved_state.lb[0])
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#define LC1REG (saved_state.lc[1])
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#define LT1REG (saved_state.lt[1])
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#define LB1REG (saved_state.lb[1])
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#define RETSREG (saved_state.rets)
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#define PCREG (saved_state.pc)
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static bu32 *
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get_allreg (int grp, int reg)
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{
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int fullreg = (grp << 3) | reg;
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/* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
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REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
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REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
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, , , , , , , ,
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REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
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REG_CYCLES2,
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REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
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REG_LASTREG */
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switch (fullreg >> 2)
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{
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case 0: case 1: return &DREG (reg); break;
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case 2: case 3: return &PREG (reg); break;
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case 4: return &IREG (reg & 3); break;
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case 5: return &MREG (reg & 3); break;
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case 6: return &BREG (reg & 3); break;
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case 7: return &LREG (reg & 3); break;
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default:
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switch (fullreg)
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{
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case 32: return &saved_state.a0x;
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case 33: return &saved_state.a0w;
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case 34: return &saved_state.a1x;
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case 35: return &saved_state.a1w;
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case 39: return &saved_state.rets;
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case 48: return &LC0REG;
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case 49: return <0REG;
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case 50: return &LB0REG;
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case 51: return &LC1REG;
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case 52: return <1REG;
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case 53: return &LB1REG;
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}
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return 0;
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}
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}
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static int
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decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
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{
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@ -2344,6 +2472,35 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
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int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
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bu32 *pval = get_allreg (grp, reg);
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/* Since we don't have 32-bit immediate loads, we allow the disassembler
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to combine them, so it prints out the right values.
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Here we keep track of the registers. */
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if (H == 0 && S == 1 && Z == 0)
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{
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/* regs = imm16 (x) */
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*pval = imm16_val (hword);
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}
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else if (H == 0 && S == 0 && Z == 1)
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{
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/* regs = luimm16 (Z) */
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*pval = luimm16_val (hword);
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}
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else if (H == 0 && S == 0 && Z == 0)
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{
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/* regs_lo = luimm16 */
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*pval &= 0xFFFF0000;
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*pval |= luimm16_val (hword);
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}
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else if (H == 1 && S == 0 && Z == 0)
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{
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/* regs_hi = huimm16 */
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*pval &= 0xFFFF;
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*pval |= luimm16_val (hword) << 16;
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}
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/* Here we do the disassembly */
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if (grp == 0 && H == 0 && S == 0 && Z == 0)
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{
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OUTS (outf, dregs_lo (reg));
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@ -2381,17 +2538,30 @@ decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
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{
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OUTS (outf, regs_lo (reg, grp));
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OUTS (outf, "=");
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OUTS (outf, luimm16 (hword));
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OUTS (outf, uimm16 (hword));
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}
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else if (H == 1 && S == 0 && Z == 0)
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{
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OUTS (outf, regs_hi (reg, grp));
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OUTS (outf, "=");
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OUTS (outf, huimm16 (hword));
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OUTS (outf, uimm16 (hword));
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}
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else
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return 0;
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/* And we print out the 32-bit value if it is a pointer. */
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if ( S == 0 && Z == 0 && grp != 0 )
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{
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OUTS (outf, "\t/* ");
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/* If it is an MMR, don't print the symbol. */
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if ( *pval < 0xFFC00000 )
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OUTS (outf, huimm32(*pval));
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else
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OUTS (outf, uimm32(*pval));
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OUTS (outf, " */");
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}
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return 4;
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}
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