[PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup, M_MNEM_viwdup): New instruction encodings. (NEON_SHAPE_DEF): New shapes. (do_mve_viddup): New encoding function. (do_neon_dup): Change to support new MVE variants. (insns): Change existing to accept MVE variants and add new. * testsuite/gas/arm/mve-vddup-bad.d: New test. * testsuite/gas/arm/mve-vddup-bad.l: New test. * testsuite/gas/arm/mve-vddup-bad.s: New test. * testsuite/gas/arm/mve-vdup-bad.d: New test. * testsuite/gas/arm/mve-vdup-bad.l: New test. * testsuite/gas/arm/mve-vdup-bad.s: New test. * testsuite/gas/arm/mve-vidup-bad.d: New test. * testsuite/gas/arm/mve-vidup-bad.l: New test. * testsuite/gas/arm/mve-vidup-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
f30ee27c15
commit
b409bdb60e
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@ -1,3 +1,21 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,
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M_MNEM_viwdup): New instruction encodings.
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(NEON_SHAPE_DEF): New shapes.
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(do_mve_viddup): New encoding function.
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(do_neon_dup): Change to support new MVE variants.
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(insns): Change existing to accept MVE variants and add new.
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* testsuite/gas/arm/mve-vddup-bad.d: New test.
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* testsuite/gas/arm/mve-vddup-bad.l: New test.
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* testsuite/gas/arm/mve-vddup-bad.s: New test.
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* testsuite/gas/arm/mve-vdup-bad.d: New test.
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* testsuite/gas/arm/mve-vdup-bad.l: New test.
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* testsuite/gas/arm/mve-vdup-bad.s: New test.
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* testsuite/gas/arm/mve-vidup-bad.d: New test.
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* testsuite/gas/arm/mve-vidup-bad.l: New test.
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* testsuite/gas/arm/mve-vidup-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vfmas): New encoding function.
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@ -14154,6 +14154,10 @@ do_t_loloop (void)
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#define M_MNEM_vaddlva 0xee890f20
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#define M_MNEM_vaddv 0xeef10f00
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#define M_MNEM_vaddva 0xeef10f20
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#define M_MNEM_vddup 0xee011f6e
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#define M_MNEM_vdwdup 0xee011f60
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#define M_MNEM_vidup 0xee010f6e
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#define M_MNEM_viwdup 0xee010f60
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/* Neon instruction encoder helpers. */
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@ -14318,8 +14322,10 @@ NEON_ENC_TAB
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- a table used to drive neon_select_shape. */
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#define NEON_SHAPE_DEF \
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X(4, (Q, R, R, I), QUAD), \
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X(4, (R, R, S, S), QUAD), \
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X(4, (S, S, R, R), QUAD), \
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X(3, (Q, R, I), QUAD), \
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X(3, (I, Q, Q), QUAD), \
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X(3, (I, Q, R), QUAD), \
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X(3, (R, Q, Q), QUAD), \
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@ -15605,6 +15611,49 @@ do_mve_vfmas (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_viddup (void)
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{
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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unsigned imm = inst.relocs[0].exp.X_add_number;
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constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
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_("immediate must be either 1, 2, 4 or 8"));
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enum neon_shape rs;
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struct neon_type_el et;
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unsigned Rm;
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if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
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{
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rs = neon_select_shape (NS_QRI, NS_NULL);
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et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
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Rm = 7;
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}
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else
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{
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constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
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if (inst.operands[2].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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else if (inst.operands[2].reg == REG_PC)
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first_error (BAD_PC);
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rs = neon_select_shape (NS_QRRI, NS_NULL);
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et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
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Rm = inst.operands[2].reg >> 1;
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}
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= neon_logbits (et.size) << 20;
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inst.instruction |= inst.operands[1].reg << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= (imm > 2) << 7;
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inst.instruction |= Rm << 1;
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inst.instruction |= (imm == 2 || imm == 8);
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inst.is_neon = 1;
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}
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static void
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do_mve_vcmul (void)
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{
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@ -18404,6 +18453,8 @@ do_neon_dup (void)
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{
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if (inst.operands[1].isscalar)
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
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BAD_FPU);
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enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs,
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N_EQK, N_8 | N_16 | N_32 | N_KEY);
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@ -18431,6 +18482,23 @@ do_neon_dup (void)
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enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs,
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N_8 | N_16 | N_32 | N_KEY, N_EQK);
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if (rs == NS_QR)
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{
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH))
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return;
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}
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else
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
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BAD_FPU);
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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if (inst.operands[1].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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else if (inst.operands[1].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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}
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/* Duplicate ARM register to lanes of vector. */
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NEON_ENCODE (ARMREG, inst);
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switch (et.size)
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@ -23656,7 +23724,6 @@ static const struct asm_opcode insns[] =
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NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
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NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
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/* Vector replicate. Sizes 8 16 32. */
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nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
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nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
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/* VMOVL. Types S8 S16 S32 U8 U16 U32. */
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NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
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@ -24218,6 +24285,10 @@ static const struct asm_opcode insns[] =
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mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
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mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
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mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
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mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
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mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
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mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
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mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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@ -24280,6 +24351,7 @@ static const struct asm_opcode insns[] =
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mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
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MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
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MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
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mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,6 @@
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#name: bad MVE VDDUP and VDWDUP instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vddup-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,33 @@
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[^:]*: Assembler messages:
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[^:]*:16: Error: bad type in SIMD instruction -- `vddup.s16 q0,r0,#1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vddup.u64 q0,r0,#1'
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[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#3'
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[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#0'
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[^:]*:20: Error: bad type in SIMD instruction -- `vdwdup.s16 q0,r0,r1,#1'
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[^:]*:21: Error: bad type in SIMD instruction -- `vdwdup.u64 q0,r0,r1,#1'
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[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#3'
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[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#0'
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[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:25: Error: r15 not allowed here -- `vdwdup.u32 q0,r0,pc,#1'
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
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[^:]*:30: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
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[^:]*:32: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
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[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vddupt.u32 q0,r0,#1'
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[^:]*:35: Error: instruction missing MVE vector predication code -- `vddup.u32 q0,r0,#1'
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[^:]*:37: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
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[^:]*:38: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
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[^:]*:40: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
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[^:]*:41: Error: vector predicated instruction should be in VPT/VPST block -- `vdwdupt.u32 q0,r0,r1,#1'
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[^:]*:43: Error: instruction missing MVE vector predication code -- `vdwdup.u32 q0,r0,r1,#1'
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@ -0,0 +1,43 @@
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.macro cond1
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vddup.u32 q0, r2, #1
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.endr
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.endm
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.macro cond2
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vdwdup.u32 q0, r2, r1, #1
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.endr
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.endm
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.syntax unified
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.thumb
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vddup.s16 q0, r0, #1
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vddup.u64 q0, r0, #1
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vddup.u32 q0, r0, #3
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vddup.u32 q0, r0, #0
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vdwdup.s16 q0, r0, r1, #1
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vdwdup.u64 q0, r0, r1, #1
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vdwdup.u32 q0, r0, r1, #3
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vdwdup.u32 q0, r0, r1, #0
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vdwdup.u32 q0, r0, sp, #1
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vdwdup.u32 q0, r0, pc, #1
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cond1
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cond2
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it eq
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vddupeq.u32 q0, r0, #1
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vddupeq.u32 q0, r0, #1
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vpst
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vddupeq.u32 q0, r0, #1
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vddupt.u32 q0, r0, #1
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vpst
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vddup.u32 q0, r0, #1
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it eq
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vdwdupeq.u32 q0, r0, r1, #1
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vdwdupeq.u32 q0, r0, r1, #1
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vpst
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vdwdupeq.u32 q0, r0, r1, #1
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vdwdupt.u32 q0, r0, r1, #1
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vpst
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vdwdup.u32 q0, r0, r1, #1
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@ -0,0 +1,5 @@
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#name: bad MVE VDUP instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vdup-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,16 @@
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[^:]*: Assembler messages:
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[^:]*:11: Error: bad type in SIMD instruction -- `vdup.64 q0,r1'
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[^:]*:12: Error: selected FPU does not support instruction -- `vdup.32 q0,d0\[1\]'
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[^:]*:13: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Error: syntax error -- `vdupeq.32 q0,r2'
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[^:]*:18: Error: syntax error -- `vdupeq.32 q0,r2'
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[^:]*:20: Error: syntax error -- `vdupeq.32 q0,r2'
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[^:]*:21: Error: incorrect condition in VPT/VPST block -- `vdupt.32 q0,r2'
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[^:]*:23: Error: instruction missing MVE vector predication code -- `vdup.32 q0,r2'
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@ -0,0 +1,23 @@
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.macro cond
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vdup.32 q0, r2
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.endr
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.endm
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.syntax unified
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.thumb
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vdup.f16 q0, r1
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vdup.64 q0, r1
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vdup.32 q0, d0[1]
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vdup.32 q0, sp
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vdup.32 q0, pc
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cond
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it eq
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vdupeq.32 q0, r2
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vdupeq.32 q0, r2
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vpste
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vdupeq.32 q0, r2
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vdupt.32 q0, r2
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vpst
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vdup.32 q0, r2
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@ -0,0 +1,5 @@
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#name: bad MVE VIDUP and VIWDUP instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vidup-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,34 @@
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[^:]*: Assembler messages:
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[^:]*:16: Error: bad type in SIMD instruction -- `vidup.s16 q0,r0,#1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vidup.u64 q0,r0,#1'
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[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#3'
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[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vidup.u32 q0,r0,#0'
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[^:]*:20: Error: bad type in SIMD instruction -- `viwdup.s16 q0,r0,r1,#1'
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[^:]*:21: Error: bad type in SIMD instruction -- `viwdup.u64 q0,r0,r1,#1'
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[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#3'
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[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `viwdup.u32 q0,r0,r1,#0'
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[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:25: Error: r15 not allowed here -- `viwdup.u32 q0,r0,pc,#1'
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
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[^:]*:30: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
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[^:]*:32: Error: syntax error -- `vidupeq.u32 q0,r0,#1'
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||||
[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vidupt.u32 q0,r0,#1'
|
||||
[^:]*:35: Error: instruction missing MVE vector predication code -- `vidup.u32 q0,r0,#1'
|
||||
[^:]*:37: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
|
||||
[^:]*:38: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
|
||||
[^:]*:40: Error: syntax error -- `viwdupeq.u32 q0,r0,r1,#1'
|
||||
[^:]*:41: Error: vector predicated instruction should be in VPT/VPST block -- `viwdupt.u32 q0,r0,r1,#1'
|
||||
[^:]*:43: Error: instruction missing MVE vector predication code -- `viwdup.u32 q0,r0,r1,#1'
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
.macro cond1
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vidup.u32 q0, r2, #1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.macro cond2
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
viwdup.u32 q0, r2, r1, #1
|
||||
.endr
|
||||
.endm
|
||||
.syntax unified
|
||||
.thumb
|
||||
vidup.s16 q0, r0, #1
|
||||
vidup.u64 q0, r0, #1
|
||||
vidup.u32 q0, r0, #3
|
||||
vidup.u32 q0, r0, #0
|
||||
viwdup.s16 q0, r0, r1, #1
|
||||
viwdup.u64 q0, r0, r1, #1
|
||||
viwdup.u32 q0, r0, r1, #3
|
||||
viwdup.u32 q0, r0, r1, #0
|
||||
viwdup.u32 q0, r0, sp, #1
|
||||
viwdup.u32 q0, r0, pc, #1
|
||||
cond1
|
||||
cond2
|
||||
it eq
|
||||
vidupeq.u32 q0, r0, #1
|
||||
vidupeq.u32 q0, r0, #1
|
||||
vpst
|
||||
vidupeq.u32 q0, r0, #1
|
||||
vidupt.u32 q0, r0, #1
|
||||
vpst
|
||||
vidup.u32 q0, r0, #1
|
||||
it eq
|
||||
viwdupeq.u32 q0, r0, r1, #1
|
||||
viwdupeq.u32 q0, r0, r1, #1
|
||||
vpst
|
||||
viwdupeq.u32 q0, r0, r1, #1
|
||||
viwdupt.u32 q0, r0, r1, #1
|
||||
vpst
|
||||
viwdup.u32 q0, r0, r1, #1
|
||||
Loading…
Reference in New Issue