From b417536f2350881ad28952b3906a025a54d241bd Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 26 Jun 2017 19:20:50 +0100 Subject: [PATCH] MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core (for an odd reason referred to as LSI R4010 across our code base) as a MIPS II processor in BFD as well, fixing a bug that has been there since forever and addressing linker warnings like: $ as -m4010 empty.s -o 4010.o $ ld -r 4010.o -o 4010-r.o ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags $ due to the ISA level being recorded as MIPS III in ELF file header's `e_flags' vs MIPS II in the MIPS ABI Flags section: $ readelf -Ah 4010.o ELF Header: Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, big endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: REL (Relocatable file) Machine: MIPS R3000 Version: 0x1 Entry point address: 0x0 Start of program headers: 0 (bytes into file) Start of section headers: 348 (bytes into file) Flags: 0x20821000, 4010, o32, mips3 Size of this header: 52 (bytes) Size of program headers: 0 (bytes) Number of program headers: 0 Size of section headers: 40 (bytes) Number of section headers: 11 Section header string table index: 10 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float (double precision) MIPS ABI Flags Version: 0 ISA: MIPS2 GPR size: 32 CPR1 size: 32 CPR2 size: 0 FP ABI: Hard float (double precision) ISA Extension: LSI R4010 ASEs: None FLAGS 1: 00000000 FLAGS 2: 00000000 $ Available documentation[1][2] clearly indicates the LSI CW4010 processor is only backwards compatible with the MIPS R4000 processor as far as the latter's 32-bit instructions are concerned and consequently can only be considered a MIPS II ISA implementation (with vendor extensions). This fixes an LD testsuite failure: FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32" triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets. References: [1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995, presented at Hot Chips VII, Stanford University, Stanford, California, August 1995 [2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017 bfd/ * cpu-mips.c (arch_info_struct): Mark the 4010 32-bit. * elfxx-mips.c (mips_set_isa_flags) : Set E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'. (mips_mach_extensions): Mark `bfd_mach_mips4010' as extending `bfd_mach_mips6000' rather than `bfd_mach_mips4000'. ld/ * testsuite/ld-mips-elf/lsi-4010-isa.d: New test. * ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test. --- bfd/ChangeLog | 8 ++++++++ bfd/cpu-mips.c | 2 +- bfd/elfxx-mips.c | 10 +++++----- ld/ChangeLog | 5 +++++ ld/testsuite/ld-mips-elf/lsi-4010-isa.d | 23 +++++++++++++++++++++++ ld/testsuite/ld-mips-elf/mips-elf.exp | 3 +++ 6 files changed, 45 insertions(+), 6 deletions(-) create mode 100644 ld/testsuite/ld-mips-elf/lsi-4010-isa.d diff --git a/bfd/ChangeLog b/bfd/ChangeLog index e088cdcad2..cd5cb579d1 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,11 @@ +2017-06-26 Maciej W. Rozycki + + * cpu-mips.c (arch_info_struct): Mark the 4010 32-bit. + * elfxx-mips.c (mips_set_isa_flags) : Set + E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'. + (mips_mach_extensions): Mark `bfd_mach_mips4010' as extending + `bfd_mach_mips6000' rather than `bfd_mach_mips4000'. + 2017-06-26 H.J. Lu PR binutils/21665 diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c index b9ecdd6e55..70a8aa71cc 100644 --- a/bfd/cpu-mips.c +++ b/bfd/cpu-mips.c @@ -114,7 +114,7 @@ static const bfd_arch_info_type arch_info_struct[] = N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)), N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)), N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)), - N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)), + N (32, 32, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)), N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)), N (64, 64, bfd_mach_mips4111, "mips:4111", FALSE, NN(I_mips4111)), N (64, 64, bfd_mach_mips4120, "mips:4120", FALSE, NN(I_mips4120)), diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index 830207ad6a..e326edd325 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -11863,6 +11863,10 @@ mips_set_isa_flags (bfd *abfd) val = E_MIPS_ARCH_2; break; + case bfd_mach_mips4010: + val = E_MIPS_ARCH_2 | E_MIPS_MACH_4010; + break; + case bfd_mach_mips4000: case bfd_mach_mips4300: case bfd_mach_mips4400: @@ -11870,10 +11874,6 @@ mips_set_isa_flags (bfd *abfd) val = E_MIPS_ARCH_3; break; - case bfd_mach_mips4010: - val = E_MIPS_ARCH_3 | E_MIPS_MACH_4010; - break; - case bfd_mach_mips4100: val = E_MIPS_ARCH_3 | E_MIPS_MACH_4100; break; @@ -14024,7 +14024,6 @@ static const struct mips_mach_extension mips_mach_extensions[] = { bfd_mach_mips4400, bfd_mach_mips4000 }, { bfd_mach_mips4300, bfd_mach_mips4000 }, { bfd_mach_mips4100, bfd_mach_mips4000 }, - { bfd_mach_mips4010, bfd_mach_mips4000 }, { bfd_mach_mips5900, bfd_mach_mips4000 }, /* MIPS32 extensions. */ @@ -14033,6 +14032,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = /* MIPS II extensions. */ { bfd_mach_mips4000, bfd_mach_mips6000 }, { bfd_mach_mipsisa32, bfd_mach_mips6000 }, + { bfd_mach_mips4010, bfd_mach_mips6000 }, /* MIPS I extensions. */ { bfd_mach_mips6000, bfd_mach_mips3000 }, diff --git a/ld/ChangeLog b/ld/ChangeLog index 9b16d43724..b92a82bb0d 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,8 @@ +2017-06-26 Maciej W. Rozycki + + * testsuite/ld-mips-elf/lsi-4010-isa.d: New test. + * ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test. + 2017-06-26 Maciej W. Rozycki * testsuite/ld-elf/sizeofa.d: Also accept the OBJECT type for diff --git a/ld/testsuite/ld-mips-elf/lsi-4010-isa.d b/ld/testsuite/ld-mips-elf/lsi-4010-isa.d new file mode 100644 index 0000000000..5e7872338f --- /dev/null +++ b/ld/testsuite/ld-mips-elf/lsi-4010-isa.d @@ -0,0 +1,23 @@ +#readelf: -Ah +#name: LSI 4010 processor ISA level +#source: empty.s +#as: -EB -32 -m4010 +#ld: -EB -r + +ELF Header: +#... + Flags: 0x1082[01]000, 4010(?:, o32)?, mips2 +#... + +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: .* +ISA Extension: LSI R4010 +ASEs: + None +FLAGS 1: .* +FLAGS 2: .* diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp index e24c32cd80..66b2ae4677 100644 --- a/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -1176,3 +1176,6 @@ run_ld_link_tests [list \ {{objdump {-d --prefix-addresses} pr21334.dd} \ {readelf -A pr21334.gd}} \ "pr21334"]] + +# Check that the ISA level is consistently II for the LSI 4010. +run_dump_test "lsi-4010-isa" [list [list ld $abi_ldflags(o32)]]