x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter
that the SDM uses a nonstandard description of that fact.
PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode,
just like its AVX counterpart.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
931d03b75a
commit
b50c9f3166
@ -1,3 +1,13 @@
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2018-11-06 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/avx-wig.s,
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testsuite/gas/i386/x86-64-avx-wig.s: Add vpextrb, vpextrw,
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vpinsrb, and vpinsrw cases.
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* testsuite/gas/i386/evex-wig.s: Add vpextrd and vpinsrd cases.
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* testsuite/gas/i386/avx-wig.d, testsuite/gas/i386/evex-wig.d,
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testsuite/gas/i386/evex-wig1-intel.d,
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testsuite/gas/i386/x86-64-avx-wig.d: Adjust expectations.
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2018-11-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (build_vex_prefix, build_evex_prefix):
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@ -196,8 +196,13 @@ Disassembly of section .text:
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+[a-f0-9]+: c4 e1 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e3 f9 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
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+[a-f0-9]+: c4 e3 f9 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
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+[a-f0-9]+: c4 e3 f9 14 c0 00 vpextrb \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 f9 14 00 00 vpextrb \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c4 e3 f9 16 c0 00 vpextrd \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 f9 16 00 00 vpextrd \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c4 e1 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 f9 15 c0 00 vpextrw \$0x0,%xmm0,%eax
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+[a-f0-9]+: c4 e3 f9 15 00 00 vpextrw \$0x0,%xmm0,\(%eax\)
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+[a-f0-9]+: c4 e2 c9 02 d4 vphaddd %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 03 d4 vphaddsw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 01 d4 vphaddw %xmm4,%xmm6,%xmm2
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@ -205,8 +210,12 @@ Disassembly of section .text:
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+[a-f0-9]+: c4 e2 c9 06 d4 vphsubd %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 07 d4 vphsubsw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 05 d4 vphsubw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e3 f9 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 f9 20 00 00 vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 f9 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 f9 22 00 00 vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e1 f9 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e1 f9 c4 00 00 vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e2 c9 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e1 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2
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@ -191,8 +191,13 @@ _start:
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vpcmpgtw %xmm4,%xmm6,%xmm2
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vpcmpistri $7,%xmm4,%xmm6
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vpcmpistrm $7,%xmm4,%xmm6
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vpextrb $0, %xmm0, %eax
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vpextrb $0, %xmm0, (%eax)
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vpextrd $0, %xmm0, %eax
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vpextrd $0, %xmm0, (%eax)
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vpextrw $0, %xmm0, %eax
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{store} vpextrw $0, %xmm0, %eax
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vpextrw $0, %xmm0, (%eax)
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vphaddd %xmm4,%xmm6,%xmm2
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vphaddsw %xmm4,%xmm6,%xmm2
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vphaddw %xmm4,%xmm6,%xmm2
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@ -200,8 +205,12 @@ _start:
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vphsubd %xmm4,%xmm6,%xmm2
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vphsubsw %xmm4,%xmm6,%xmm2
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vphsubw %xmm4,%xmm6,%xmm2
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vpinsrb $0, %eax, %xmm0, %xmm0
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vpinsrb $0, (%eax), %xmm0, %xmm0
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vpinsrd $0, %eax, %xmm0, %xmm0
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vpinsrd $0, (%eax), %xmm0, %xmm0
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vpinsrw $0, %eax, %xmm0, %xmm0
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vpinsrw $0, (%eax), %xmm0, %xmm0
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vpmaddubsw %xmm4,%xmm6,%xmm2
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vpmaddwd %xmm4,%xmm6,%xmm2
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vpmaxsb %xmm4,%xmm6,%xmm2
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@ -38,6 +38,9 @@ _start:
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{evex} vpextrb $0, %xmm0, %eax
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{evex} vpextrb $0, %xmm0, 1(%eax)
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{evex} vpextrd $0, %xmm0, %eax
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{evex} vpextrd $0, %xmm0, 4(%eax)
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{evex} vpextrw $0, %xmm0, %eax
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{evex} {store} vpextrw $0, %xmm0, %eax
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{evex} vpextrw $0, %xmm0, 2(%eax)
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@ -45,6 +48,9 @@ _start:
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{evex} vpinsrb $0, %eax, %xmm0, %xmm0
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{evex} vpinsrb $0, 1(%eax), %xmm0, %xmm0
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{evex} vpinsrd $0, %eax, %xmm0, %xmm0
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{evex} vpinsrd $0, 4(%eax), %xmm0, %xmm0
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{evex} vpinsrw $0, %eax, %xmm0, %xmm0
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{evex} vpinsrw $0, 2(%eax), %xmm0, %xmm0
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@ -29,11 +29,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 62 f3 fd 08 17 40 01 00 vextractps DWORD PTR \[eax\+0x4\],xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb eax,xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 14 40 01 00 vpextrb BYTE PTR \[eax\+0x1\],xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 16 c0 00 vpextrd eax,xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 16 40 01 00 vpextrd DWORD PTR \[eax\+0x4\],xmm0,0x0
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[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw eax,xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw eax,xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 15 40 01 00 vpextrw WORD PTR \[eax\+0x2\],xmm0,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,eax,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 20 40 01 00 vpinsrb xmm0,xmm0,BYTE PTR \[eax\+0x1\],0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 22 c0 00 vpinsrd xmm0,xmm0,eax,0x0
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[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
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[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
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[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
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[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5
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@ -29,11 +29,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 62 f3 fd 08 17 40 01 00 vextractps \$0x0,%xmm0,0x4\(%eax\)
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[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
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[ ]*[a-f0-9]+: 62 f3 fd 08 14 40 01 00 vpextrb \$0x0,%xmm0,0x1\(%eax\)
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[ ]*[a-f0-9]+: 62 f3 fd 08 16 c0 00 vpextrd \$0x0,%xmm0,%eax
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[ ]*[a-f0-9]+: 62 f3 fd 08 16 40 01 00 vpextrd \$0x0,%xmm0,0x4\(%eax\)
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[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
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[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
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[ ]*[a-f0-9]+: 62 f3 fd 08 15 40 01 00 vpextrw \$0x0,%xmm0,0x2\(%eax\)
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[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f3 fd 08 20 40 01 00 vpinsrb \$0x0,0x1\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f3 fd 08 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
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[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}
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@ -157,6 +157,11 @@ Disassembly of section .text:
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+[a-f0-9]+: c4 e1 c9 65 d4 vpcmpgtw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e3 f9 63 f4 07 vpcmpistri \$0x7,%xmm4,%xmm6
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+[a-f0-9]+: c4 e3 f9 62 f4 07 vpcmpistrm \$0x7,%xmm4,%xmm6
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+[a-f0-9]+: c4 e3 f9 14 c0 00 vpextrb \$0x0,%xmm0,%rax
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+[a-f0-9]+: c4 e3 f9 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: c4 e1 f9 c5 c0 00 vpextrw \$0x0,%xmm0,%rax
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+[a-f0-9]+: c4 e3 f9 15 c0 00 vpextrw \$0x0,%xmm0,%rax
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+[a-f0-9]+: c4 e3 f9 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
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+[a-f0-9]+: c4 e2 c9 02 d4 vphaddd %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 03 d4 vphaddsw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 01 d4 vphaddw %xmm4,%xmm6,%xmm2
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@ -164,6 +169,10 @@ Disassembly of section .text:
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+[a-f0-9]+: c4 e2 c9 06 d4 vphsubd %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 07 d4 vphsubsw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 05 d4 vphsubw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e3 f9 20 c0 00 vpinsrb \$0x0,%rax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e3 f9 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e1 f9 c4 c0 00 vpinsrw \$0x0,%rax,%xmm0,%xmm0
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+[a-f0-9]+: c4 e1 f9 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
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+[a-f0-9]+: c4 e2 c9 04 d4 vpmaddubsw %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e1 c9 f5 d4 vpmaddwd %xmm4,%xmm6,%xmm2
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+[a-f0-9]+: c4 e2 c9 3c d4 vpmaxsb %xmm4,%xmm6,%xmm2
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@ -152,6 +152,11 @@ _start:
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vpcmpgtw %xmm4,%xmm6,%xmm2
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vpcmpistri $7,%xmm4,%xmm6
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vpcmpistrm $7,%xmm4,%xmm6
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vpextrb $0, %xmm0, %eax
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vpextrb $0, %xmm0, (%rax)
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vpextrw $0, %xmm0, %eax
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{store} vpextrw $0, %xmm0, %eax
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vpextrw $0, %xmm0, (%rax)
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vphaddd %xmm4,%xmm6,%xmm2
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vphaddsw %xmm4,%xmm6,%xmm2
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vphaddw %xmm4,%xmm6,%xmm2
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@ -159,6 +164,10 @@ _start:
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vphsubd %xmm4,%xmm6,%xmm2
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vphsubsw %xmm4,%xmm6,%xmm2
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vphsubw %xmm4,%xmm6,%xmm2
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vpinsrb $0, %eax, %xmm0, %xmm0
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vpinsrb $0, (%rax), %xmm0, %xmm0
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vpinsrw $0, %eax, %xmm0, %xmm0
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vpinsrw $0, (%rax), %xmm0, %xmm0
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vpmaddubsw %xmm4,%xmm6,%xmm2
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vpmaddwd %xmm4,%xmm6,%xmm2
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vpmaxsb %xmm4,%xmm6,%xmm2
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@ -1,3 +1,18 @@
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2018-11-06 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
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VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
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EVEX_W_0F3A22_P_2): Delete.
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(vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
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entries up one level in the hierarchy.
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(OP_E_memory): Handle dq_mode when determining Disp8 shift
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value.
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* i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
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entries up one level in the hierarchy.
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* i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
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VexWIG for AVX flavors.
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* i386-tbl.h: Re-generate.
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2018-11-06 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
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@ -2663,7 +2663,7 @@ static const struct dis386 evex_table[][256] = {
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3A16_P_2) },
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{ "vpextrK", { Edq, XM, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A17 */
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{
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@ -2729,7 +2729,7 @@ static const struct dis386 evex_table[][256] = {
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3A22_P_2) },
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{ "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A23 */
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{
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@ -3892,11 +3892,6 @@ static const struct dis386 evex_table[][256] = {
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{ Bad_Opcode },
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{ "vrndscalesd", { XMScalar, VexScalar, EXxmm_mq, EXxEVexS, Ib }, 0 },
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},
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/* EVEX_W_0F3A16_P_2 */
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{
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{ "vpextrd", { Edqd, XM, Ib }, 0 },
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{ "vpextrq", { Eq, XM, Ib }, 0 },
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},
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/* EVEX_W_0F3A18_P_2 */
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{
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{ "vinsertf32x4", { XM, Vex, EXxmm, Ib }, 0 },
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@ -3925,11 +3920,6 @@ static const struct dis386 evex_table[][256] = {
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{
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{ "vinsertps", { XMM, Vex, EXxmm_md, Ib }, 0 },
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},
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/* EVEX_W_0F3A22_P_2 */
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{
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{ "vpinsrd", { XM, Vex128, Edqd, Ib }, 0 },
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{ "vpinsrq", { XM, Vex128, Eq, Ib }, 0 },
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},
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/* EVEX_W_0F3A23_P_2 */
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{
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{ "vshuff32x4", { XM, Vex, EXx, Ib }, 0 },
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@ -1971,8 +1971,6 @@ enum
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VEX_W_0F98_P_2_LEN_0,
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VEX_W_0F99_P_0_LEN_0,
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VEX_W_0F99_P_2_LEN_0,
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VEX_W_0FC4_P_2,
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VEX_W_0FC5_P_2,
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VEX_W_0F380C_P_2,
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VEX_W_0F380D_P_2,
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VEX_W_0F380E_P_2,
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@ -1999,11 +1997,8 @@ enum
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VEX_W_0F3A04_P_2,
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VEX_W_0F3A05_P_2,
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VEX_W_0F3A06_P_2,
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VEX_W_0F3A14_P_2,
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VEX_W_0F3A15_P_2,
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VEX_W_0F3A18_P_2,
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VEX_W_0F3A19_P_2,
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VEX_W_0F3A20_P_2,
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VEX_W_0F3A30_P_2_LEN_0,
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VEX_W_0F3A31_P_2_LEN_0,
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VEX_W_0F3A32_P_2_LEN_0,
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@ -2238,14 +2233,12 @@ enum
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EVEX_W_0F3A09_P_2,
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EVEX_W_0F3A0A_P_2,
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EVEX_W_0F3A0B_P_2,
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EVEX_W_0F3A16_P_2,
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EVEX_W_0F3A18_P_2,
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EVEX_W_0F3A19_P_2,
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EVEX_W_0F3A1A_P_2,
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EVEX_W_0F3A1B_P_2,
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EVEX_W_0F3A1D_P_2,
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EVEX_W_0F3A21_P_2,
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EVEX_W_0F3A22_P_2,
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EVEX_W_0F3A23_P_2,
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EVEX_W_0F3A38_P_2,
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EVEX_W_0F3A39_P_2,
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@ -9543,12 +9536,12 @@ static const struct dis386 vex_len_table[][2] = {
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/* VEX_LEN_0FC4_P_2 */
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{
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{ VEX_W_TABLE (VEX_W_0FC4_P_2) },
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{ "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
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},
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/* VEX_LEN_0FC5_P_2 */
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{
|
||||
{ VEX_W_TABLE (VEX_W_0FC5_P_2) },
|
||||
{ "vpextrw", { Gdq, XS, Ib }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0FD6_P_2 */
|
||||
@ -9681,12 +9674,12 @@ static const struct dis386 vex_len_table[][2] = {
|
||||
|
||||
/* VEX_LEN_0F3A14_P_2 */
|
||||
{
|
||||
{ VEX_W_TABLE (VEX_W_0F3A14_P_2) },
|
||||
{ "vpextrb", { Edqb, XM, Ib }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A15_P_2 */
|
||||
{
|
||||
{ VEX_W_TABLE (VEX_W_0F3A15_P_2) },
|
||||
{ "vpextrw", { Edqw, XM, Ib }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A16_P_2 */
|
||||
@ -9713,7 +9706,7 @@ static const struct dis386 vex_len_table[][2] = {
|
||||
|
||||
/* VEX_LEN_0F3A20_P_2 */
|
||||
{
|
||||
{ VEX_W_TABLE (VEX_W_0F3A20_P_2) },
|
||||
{ "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F3A21_P_2 */
|
||||
@ -10044,14 +10037,6 @@ static const struct dis386 vex_w_table[][2] = {
|
||||
{ MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
|
||||
{ MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0FC4_P_2 */
|
||||
{ "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0FC5_P_2 */
|
||||
{ "vpextrw", { Gdq, XS, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F380C_P_2 */
|
||||
{ "vpermilps", { XM, Vex, EXx }, 0 },
|
||||
@ -10158,14 +10143,6 @@ static const struct dis386 vex_w_table[][2] = {
|
||||
/* VEX_W_0F3A06_P_2 */
|
||||
{ "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3A14_P_2 */
|
||||
{ "vpextrb", { Edqb, XM, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3A15_P_2 */
|
||||
{ "vpextrw", { Edqw, XM, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3A18_P_2 */
|
||||
{ "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
|
||||
@ -10174,10 +10151,6 @@ static const struct dis386 vex_w_table[][2] = {
|
||||
/* VEX_W_0F3A19_P_2 */
|
||||
{ "vextractf128", { EXxmm, XM, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3A20_P_2 */
|
||||
{ "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3A30_P_2_LEN_0 */
|
||||
{ MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
|
||||
@ -13967,6 +13940,13 @@ OP_E_memory (int bytemode, int sizeflag)
|
||||
case db_mode:
|
||||
shift = 0;
|
||||
break;
|
||||
case dq_mode:
|
||||
if (address_mode != mode_64bit)
|
||||
{
|
||||
shift = 2;
|
||||
break;
|
||||
}
|
||||
/* fall through */
|
||||
case vex_vsib_d_w_dq_mode:
|
||||
case vex_vsib_d_w_d_mode:
|
||||
case vex_vsib_q_w_dq_mode:
|
||||
|
||||
@ -2107,13 +2107,13 @@ vpermilpd, 3, 0x660d, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|Ch
|
||||
vpermilpd, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|VexW=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
|
||||
vpextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
vpextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphaddsw, 3, 0x6603, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphaddw, 3, 0x6601, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
@ -2121,12 +2121,12 @@ vphminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexWIG|No_bSuf|No
|
||||
vphsubd, 3, 0x6606, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphsubsw, 3, 0x6607, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphsubw, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrd, 4, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vpmaxsb, 3, 0x663c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
@ -37295,7 +37295,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
|
||||
1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37314,7 +37314,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37447,7 +37447,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37466,7 +37466,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
|
||||
1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37485,7 +37485,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37805,7 +37805,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37827,7 +37827,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -37981,7 +37981,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
@ -38003,7 +38003,7 @@ const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
|
||||
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Reference in New Issue
Block a user