sim: bfin: add GPIO device simulation
This takes care of the MMR interface and pushing up interrupts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
efeff6cf14
commit
b5215db0ff
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@ -1,3 +1,18 @@
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2011-03-15 Mike Frysinger <vapier@gentoo.org>
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* Makefile.in (dv-bfin_gpio.o): New target.
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* configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_gpio.
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* configure: Regenerate.
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* dv-bfin_gpio.c, dv-bfin_gpio.h: New files.
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* machs.c: Include dv-bfin_gpio.h.
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(bf50x_mem, bf51x_mem, bf52x_mem, bf531_mem, bf532_mem, bf533_mem,
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bf534_mem, bf536_mem, bf537_mem, bf538_mem, bf561_mem, bf592_mem):
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Delete GPIO memory stubs.
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(bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, bf533_dev,
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bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev): Add GPIO
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peripheral devices.
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(bfin_model_hw_tree_init): Hook up GPIO interrupts to SIC.
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2011-03-15 Mike Frysinger <vapier@gentoo.org>
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* bfroms/bf50x-0.0.h, bfroms/bf51x-0.0.h, bfroms/bf51x-0.1.h,
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@ -79,6 +79,7 @@ dv-bfin_ebiu_sdc.o: dv-bfin_ebiu_sdc.c devices.h $(INCLUDE)
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dv-bfin_emac.o: dv-bfin_emac.c devices.h $(INCLUDE)
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dv-bfin_eppi.o: dv-bfin_eppi.c devices.h $(INCLUDE)
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dv-bfin_evt.o: dv-bfin_evt.c devices.h $(INCLUDE)
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dv-bfin_gpio.o: dv-bfin_gpio.c devices.h $(INCLUDE)
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dv-bfin_gptimer.o: dv-bfin_gptimer.c devices.h $(INCLUDE)
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dv-bfin_jtag.o: dv-bfin_jtag.c devices.h $(INCLUDE)
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dv-bfin_mmu.o: dv-bfin_mmu.c devices.h $(INCLUDE)
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@ -5087,6 +5087,7 @@ hardware="$hardware \
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bfin_emac \
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bfin_eppi \
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bfin_evt \
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bfin_gpio \
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bfin_gptimer \
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bfin_jtag \
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bfin_mmu \
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@ -27,6 +27,7 @@ SIM_AC_OPTION_HARDWARE(yes,,\
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bfin_emac \
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bfin_eppi \
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bfin_evt \
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bfin_gpio \
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bfin_gptimer \
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bfin_jtag \
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bfin_mmu \
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@ -0,0 +1,287 @@
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/* Blackfin General Purpose Ports (GPIO) model
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Copyright (C) 2010-2011 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_gpio.h"
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struct bfin_gpio
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{
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bu32 base;
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(data);
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bu16 BFIN_MMR_16(clear);
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bu16 BFIN_MMR_16(set);
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bu16 BFIN_MMR_16(toggle);
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bu16 BFIN_MMR_16(maska);
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bu16 BFIN_MMR_16(maska_clear);
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bu16 BFIN_MMR_16(maska_set);
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bu16 BFIN_MMR_16(maska_toggle);
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bu16 BFIN_MMR_16(maskb);
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bu16 BFIN_MMR_16(maskb_clear);
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bu16 BFIN_MMR_16(maskb_set);
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bu16 BFIN_MMR_16(maskb_toggle);
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bu16 BFIN_MMR_16(dir);
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bu16 BFIN_MMR_16(polar);
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bu16 BFIN_MMR_16(edge);
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bu16 BFIN_MMR_16(both);
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bu16 BFIN_MMR_16(inen);
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};
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#define mmr_base() offsetof(struct bfin_gpio, data)
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#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"PORTIO", "PORTIO_CLEAR", "PORTIO_SET", "PORTIO_TOGGLE", "PORTIO_MASKA",
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"PORTIO_MASKA_CLEAR", "PORTIO_MASKA_SET", "PORTIO_MASKA_TOGGLE",
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"PORTIO_MASKB", "PORTIO_MASKB_CLEAR", "PORTIO_MASKB_SET",
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"PORTIO_MASKB_TOGGLE", "PORTIO_DIR", "PORTIO_POLAR", "PORTIO_EDGE",
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"PORTIO_BOTH", "PORTIO_INEN",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 mmr_off;
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bu16 value;
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bu16 *valuep;
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value = dv_load_2 (source);
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mmr_off = addr - port->base;
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valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
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switch (mmr_off)
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{
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case mmr_offset(data):
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case mmr_offset(maska):
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case mmr_offset(maskb):
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case mmr_offset(dir):
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case mmr_offset(polar):
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case mmr_offset(edge):
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case mmr_offset(both):
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case mmr_offset(inen):
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*valuep = value;
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break;
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case mmr_offset(clear):
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case mmr_offset(maska_clear):
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case mmr_offset(maskb_clear):
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dv_w1c_2 (valuep, value, 0);
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break;
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case mmr_offset(set):
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case mmr_offset(maska_set):
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case mmr_offset(maskb_set):
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*valuep |= value;
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break;
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case mmr_offset(toggle):
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case mmr_offset(maska_toggle):
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case mmr_offset(maskb_toggle):
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*valuep ^= value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 mmr_off;
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bu16 *valuep;
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mmr_off = addr - port->base;
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valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
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switch (mmr_off)
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{
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case mmr_offset(data):
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case mmr_offset(clear):
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case mmr_offset(set):
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case mmr_offset(toggle):
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dv_store_2 (dest, port->data);
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break;
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case mmr_offset(maska):
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case mmr_offset(maska_clear):
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case mmr_offset(maska_set):
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case mmr_offset(maska_toggle):
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dv_store_2 (dest, port->maska);
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break;
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case mmr_offset(maskb):
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case mmr_offset(maskb_clear):
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case mmr_offset(maskb_set):
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case mmr_offset(maskb_toggle):
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dv_store_2 (dest, port->maskb);
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break;
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case mmr_offset(dir):
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case mmr_offset(polar):
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case mmr_offset(edge):
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case mmr_offset(both):
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case mmr_offset(inen):
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dv_store_2 (dest, *valuep);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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break;
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}
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_gpio_ports[] =
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{
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{ "mask_a", 0, 0, output_port, },
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{ "mask_b", 1, 0, output_port, },
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{ "p0", 0, 0, input_port, },
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{ "p1", 1, 0, input_port, },
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{ "p2", 2, 0, input_port, },
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{ "p3", 3, 0, input_port, },
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{ "p4", 4, 0, input_port, },
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{ "p5", 5, 0, input_port, },
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{ "p6", 6, 0, input_port, },
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{ "p7", 7, 0, input_port, },
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{ "p8", 8, 0, input_port, },
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{ "p9", 9, 0, input_port, },
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{ "p10", 10, 0, input_port, },
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{ "p11", 11, 0, input_port, },
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{ "p12", 12, 0, input_port, },
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{ "p13", 13, 0, input_port, },
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{ "p14", 14, 0, input_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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struct bfin_gpio *port = hw_data (me);
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bool olvl, nlvl;
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bu32 bit = (1 << my_port);
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/* Only screw with state if this pin is set as an input. */
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if (!(port->dir & port->inen & bit))
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return;
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/* Get the old pin state for calculating an interrupt. */
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olvl = !!(port->data & bit);
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/* Update the new pin state. */
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port->data = (port->data & ~bit) | (level << bit);
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/* See if this state transition will generate an interrupt. */
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nlvl = !!(port->data & bit);
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if (port->edge & bit)
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{
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/* Pin is edge triggered. */
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if (!(port->both & bit))
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{
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/* Both edges. */
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if (olvl == nlvl)
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return;
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}
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else
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{
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/* Just one edge. */
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if (!(((port->polar & bit) && olvl > nlvl)
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|| (!(port->polar & bit) && olvl < nlvl)))
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return;
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}
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}
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else
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{
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/* Pin is level triggered. */
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if (nlvl == !!(port->polar & bit))
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return;
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}
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/* If the masks allow it, push the interrupt even higher. */
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if (port->maska & bit)
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hw_port_event (me, 0, 1);
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if (port->maskb & bit)
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hw_port_event (me, 1, 1);
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}
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static void
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attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_GPIO_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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port->base = attach_address;
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}
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static void
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bfin_gpio_finish (struct hw *me)
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{
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struct bfin_gpio *port;
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port = HW_ZALLOC (me, struct bfin_gpio);
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set_hw_data (me, port);
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set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
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set_hw_ports (me, bfin_gpio_ports);
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set_hw_port_event (me, bfin_gpio_port_event);
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attach_bfin_gpio_regs (me, port);
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}
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const struct hw_descriptor dv_bfin_gpio_descriptor[] =
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{
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{"bfin_gpio", bfin_gpio_finish,},
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{NULL, NULL},
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};
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@ -0,0 +1,27 @@
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/* Blackfin General Purpose Ports (GPIO) model
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Copyright (C) 2010-2011 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef DV_BFIN_GPIO_H
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#define DV_BFIN_GPIO_H
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/* XXX: This should be pushed into the model data. */
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#define BFIN_MMR_GPIO_SIZE (17 * 4)
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#endif
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@ -36,13 +36,14 @@
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#include "dv-bfin_emac.h"
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#include "dv-bfin_eppi.h"
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#include "dv-bfin_evt.h"
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#include "dv-bfin_gpio.h"
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#include "dv-bfin_gptimer.h"
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#include "dv-bfin_jtag.h"
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#include "dv-bfin_mmu.h"
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#include "dv-bfin_nfc.h"
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#include "dv-bfin_otp.h"
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#include "dv-bfin_ppi.h"
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#include "dv-bfin_pll.h"
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#include "dv-bfin_ppi.h"
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#include "dv-bfin_rtc.h"
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#include "dv-bfin_sic.h"
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#include "dv-bfin_spi.h"
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@ -96,11 +97,8 @@ static const struct bfin_dmac_layout bf000_dmac[] = {};
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#define bf506_chipid bf50x_chipid
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static const struct bfin_memory_layout bf50x_mem[] =
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{
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LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
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LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
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LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
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LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
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LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
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LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
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LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
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LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
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@ -124,9 +122,12 @@ static const struct bfin_dev_layout bf50x_dev[] =
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DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
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DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
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DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
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DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
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DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
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DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
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DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
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DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
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DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
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DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
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DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
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};
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@ -147,11 +148,8 @@ static const struct bfin_dmac_layout bf50x_dmac[] =
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static const struct bfin_memory_layout bf51x_mem[] =
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{
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LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
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LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
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LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
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LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
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LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
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LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
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LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
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LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
|
||||
LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
|
||||
|
|
@ -180,10 +178,13 @@ static const struct bfin_dev_layout bf512_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
|
||||
DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
|
||||
DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
|
||||
|
|
@ -203,10 +204,13 @@ static const struct bfin_dev_layout bf516_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
|
||||
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
|
||||
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
|
||||
|
|
@ -228,11 +232,8 @@ static const struct bfin_dev_layout bf516_dev[] =
|
|||
static const struct bfin_memory_layout bf52x_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
|
||||
LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
|
||||
LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
|
||||
LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
|
||||
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
|
||||
|
|
@ -263,10 +264,13 @@ static const struct bfin_dev_layout bf522_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
|
||||
DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
|
||||
DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
|
||||
|
|
@ -288,10 +292,13 @@ static const struct bfin_dev_layout bf526_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
|
||||
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
|
||||
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
|
||||
|
|
@ -312,7 +319,6 @@ static const struct bfin_dev_layout bf526_dev[] =
|
|||
static const struct bfin_memory_layout bf531_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
|
||||
|
|
@ -322,7 +328,6 @@ static const struct bfin_memory_layout bf531_mem[] =
|
|||
static const struct bfin_memory_layout bf532_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
|
||||
|
|
@ -334,7 +339,6 @@ static const struct bfin_memory_layout bf532_mem[] =
|
|||
static const struct bfin_memory_layout bf533_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
|
||||
|
|
@ -355,6 +359,7 @@ static const struct bfin_dev_layout bf533_dev[] =
|
|||
DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
|
||||
DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
|
||||
DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
|
|
@ -374,11 +379,8 @@ static const struct bfin_dmac_layout bf533_dmac[] =
|
|||
static const struct bfin_memory_layout bf534_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
|
||||
LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
|
||||
LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
|
||||
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
|
||||
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
|
||||
|
|
@ -391,11 +393,8 @@ static const struct bfin_memory_layout bf534_mem[] =
|
|||
static const struct bfin_memory_layout bf536_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
|
||||
LAYOUT (0xFFC01700, 0x50, read_write), /* PORTG stub */
|
||||
LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
|
||||
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
|
||||
LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
|
||||
|
|
@ -406,11 +405,8 @@ static const struct bfin_memory_layout bf536_mem[] =
|
|||
static const struct bfin_memory_layout bf537_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
|
||||
LAYOUT (0xFFC01700, 0x50, read_write), /* PORTG stub */
|
||||
LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
|
||||
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
|
||||
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
|
||||
|
|
@ -434,10 +430,13 @@ static const struct bfin_dev_layout bf534_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
|
||||
};
|
||||
static const struct bfin_dev_layout bf537_dev[] =
|
||||
|
|
@ -454,10 +453,13 @@ static const struct bfin_dev_layout bf537_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
|
||||
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
|
||||
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
|
||||
|
|
@ -471,7 +473,6 @@ static const struct bfin_dev_layout bf537_dev[] =
|
|||
#define bf539_chipid bf538_chipid
|
||||
static const struct bfin_memory_layout bf538_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
|
||||
|
|
@ -500,6 +501,7 @@ static const struct bfin_dev_layout bf538_dev[] =
|
|||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
_DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
|
||||
_DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
|
||||
DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
|
||||
|
|
@ -649,11 +651,8 @@ static const struct bfin_dmac_layout bf54x_dmac[] =
|
|||
#define bf561_chipid 0x27bb
|
||||
static const struct bfin_memory_layout bf561_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO0 stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x50, read_write), /* GPIO1 stub */
|
||||
LAYOUT (0xFFC01700, 0x50, read_write), /* GPIO2 stub */
|
||||
LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
|
||||
LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
|
||||
LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
|
||||
|
|
@ -675,15 +674,18 @@ static const struct bfin_dev_layout bf561_dev[] =
|
|||
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
|
||||
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
|
||||
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
|
||||
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
|
||||
_DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
|
||||
DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
|
||||
_DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
|
||||
DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
|
||||
DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
|
||||
DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
|
||||
DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
|
||||
};
|
||||
static const struct bfin_dmac_layout bf561_dmac[] =
|
||||
{
|
||||
|
|
@ -695,10 +697,8 @@ static const struct bfin_dmac_layout bf561_dmac[] =
|
|||
#define bf592_chipid 0x20cb
|
||||
static const struct bfin_memory_layout bf592_mem[] =
|
||||
{
|
||||
LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO0 stub */
|
||||
LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
|
||||
LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
|
||||
LAYOUT (0xFFC01500, 0x50, read_write), /* GPIO1 stub */
|
||||
LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
|
||||
LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
|
||||
LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
|
||||
|
|
@ -711,9 +711,11 @@ static const struct bfin_dev_layout bf592_dev[] =
|
|||
DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
|
||||
DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
|
||||
DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
|
||||
DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
|
||||
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
|
||||
DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
|
||||
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
|
||||
DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
|
||||
};
|
||||
static const struct bfin_dmac_layout bf592_dmac[] =
|
||||
{
|
||||
|
|
@ -854,6 +856,13 @@ bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
|
|||
sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
|
||||
sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
|
||||
}
|
||||
else if (!strncmp (dev->dev, "bfin_gpio", 9))
|
||||
{
|
||||
sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
|
||||
dev->dev, dev->dev[10]);
|
||||
sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
|
||||
dev->dev, dev->dev[10]);
|
||||
}
|
||||
}
|
||||
|
||||
done:
|
||||
|
|
|
|||
Loading…
Reference in New Issue