X86: Remove pcommit instruction
Remove x86 pcommit instruction support, which has been deprecated: https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction gas/ * config/tc-i386.c (cpu_arch): Remove .pcommit. * doc/c-i386.texi: Likewise. * testsuite/gas/i386/i386.exp: Remove pcommit tests. * testsuite/gas/i386/pcommit-intel.d: Removed. * testsuite/gas/i386/pcommit.d: Likewise. * testsuite/gas/i386/pcommit.s: Likewise. * testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise. * testsuite/gas/i386/x86-64-pcommit.d: Likewise. * testsuite/gas/i386/x86-64-pcommit.s: Likewise. opcodes/ * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry. (rm_table): Update the RM_0FAE_REG_7 entry. * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS. (cpu_flags): Remove CpuPCOMMIT. * i386-opc.h (CpuPCOMMIT): Removed. (i386_cpu_flags): Remove cpupcommit. * i386-opc.tbl: Remove pcommit. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
ac423761af
commit
b5cefccad8
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@ -1,3 +1,15 @@
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2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Remove .pcommit.
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* doc/c-i386.texi: Likewise.
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* testsuite/gas/i386/i386.exp: Remove pcommit tests.
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* testsuite/gas/i386/pcommit-intel.d: Removed.
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* testsuite/gas/i386/pcommit.d: Likewise.
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* testsuite/gas/i386/pcommit.s: Likewise.
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* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
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* testsuite/gas/i386/x86-64-pcommit.s: Likewise.
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2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/20705
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@ -958,8 +958,6 @@ static const arch_entry cpu_arch[] =
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CPU_SE1_FLAGS, 0 },
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{ STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
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CPU_CLWB_FLAGS, 0 },
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{ STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
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CPU_PCOMMIT_FLAGS, 0 },
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{ STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
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CPU_AVX512IFMA_FLAGS, 0 },
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{ STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
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@ -171,7 +171,6 @@ accept various extension mnemonics. For example,
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@code{clflushopt},
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@code{se1},
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@code{clwb},
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@code{pcommit},
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@code{avx512f},
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@code{avx512cd},
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@code{avx512er},
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@ -1191,7 +1190,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
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@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
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@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
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@item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
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@item @samp{.avx512vbmi} @tab @samp{.clwb}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@ -349,8 +349,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "avx512f-rcigrz"
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run_dump_test "clwb"
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run_dump_test "clwb-intel"
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run_dump_test "pcommit"
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run_dump_test "pcommit-intel"
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run_dump_test "avx512ifma"
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run_dump_test "avx512ifma-intel"
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run_dump_test "avx512ifma_vl"
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@ -753,8 +751,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-avx512f-rcigrz"
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run_dump_test "x86-64-clwb"
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run_dump_test "x86-64-clwb-intel"
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run_dump_test "x86-64-pcommit"
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run_dump_test "x86-64-pcommit-intel"
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run_dump_test "x86-64-avx512ifma"
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run_dump_test "x86-64-avx512ifma-intel"
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run_dump_test "x86-64-avx512ifma_vl"
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@ -1,14 +0,0 @@
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#as:
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#objdump: -dw -Mintel
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#name: i386 PCOMMIT insns (Intel disassembly)
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#source: pcommit.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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#pass
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@ -1,14 +0,0 @@
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#as:
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#objdump: -dw
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#name: i386 PCOMMIT insns
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#source: pcommit.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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#pass
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@ -1,10 +0,0 @@
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# Check 32bit PCOMMIT instructions
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.allow_index_reg
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.text
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_start:
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pcommit # PCOMMIT
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.intel_syntax noprefix
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pcommit # PCOMMIT
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@ -1,14 +0,0 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 PCOMMIT insns (Intel disassembly)
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#source: x86-64-pcommit.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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#pass
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@ -1,14 +0,0 @@
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#as:
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#objdump: -dw
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#name: x86_64 PCOMMIT insns
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#source: x86-64-pcommit.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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[ ]*[a-f0-9]+:[ ]*66 0f ae f8[ ]*pcommit
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#pass
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@ -1,10 +0,0 @@
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# Check 32bit PCOMMIT instructions
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.allow_index_reg
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.text
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_start:
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pcommit # PCOMMIT
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.intel_syntax noprefix
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pcommit # PCOMMIT
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@ -1,3 +1,16 @@
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2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
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(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
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(rm_table): Update the RM_0FAE_REG_7 entry.
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* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
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(cpu_flags): Remove CpuPCOMMIT.
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* i386-opc.h (CpuPCOMMIT): Removed.
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(i386_cpu_flags): Remove cpupcommit.
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* i386-opc.tbl: Remove pcommit.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/20705
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@ -988,7 +988,6 @@ enum
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PREFIX_MOD_3_0FAE_REG_4,
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PREFIX_0FAE_REG_6,
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PREFIX_0FAE_REG_7,
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PREFIX_RM_0_0FAE_REG_7,
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PREFIX_0FB8,
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PREFIX_0FBC,
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PREFIX_0FBD,
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@ -4094,13 +4093,6 @@ static const struct dis386 prefix_table[][4] = {
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{ "clflushopt", { Mb }, 0 },
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},
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/* PREFIX_RM_0_0FAE_REG_7 */
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{
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{ "sfence", { Skip_MODRM }, 0 },
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{ Bad_Opcode },
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{ "pcommit", { Skip_MODRM }, 0 },
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},
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/* PREFIX_0FB8 */
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{
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{ Bad_Opcode },
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@ -12484,7 +12476,8 @@ static const struct dis386 rm_table[][8] = {
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},
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{
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/* RM_0FAE_REG_7 */
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{ PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
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{ "sfence", { Skip_MODRM }, 0 },
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},
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};
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@ -247,8 +247,6 @@ static initializer cpu_flag_init[] =
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"CpuSE1" },
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{ "CPU_CLWB_FLAGS",
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"CpuCLWB" },
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{ "CPU_PCOMMIT_FLAGS",
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"CpuPCOMMIT" },
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{ "CPU_CLZERO_FLAGS",
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"CpuCLZERO" },
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{ "CPU_MWAITX_FLAGS",
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@ -501,7 +499,6 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuPREFETCHWT1),
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BITFIELD (CpuSE1),
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BITFIELD (CpuCLWB),
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BITFIELD (CpuPCOMMIT),
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BITFIELD (Cpu64),
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BITFIELD (CpuNo64),
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BITFIELD (CpuMPX),
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File diff suppressed because it is too large
Load Diff
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@ -188,8 +188,6 @@ enum
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CpuSE1,
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/* CLWB instruction required */
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CpuCLWB,
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/* PCOMMIT instruction required */
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CpuPCOMMIT,
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/* Intel AVX-512 IFMA Instructions support required. */
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CpuAVX512IFMA,
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/* Intel AVX-512 VBMI Instructions support required. */
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@ -315,7 +313,6 @@ typedef union i386_cpu_flags
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unsigned int cpuprefetchwt1:1;
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unsigned int cpuse1:1;
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unsigned int cpuclwb:1;
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unsigned int cpupcommit:1;
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unsigned int cpuavx512ifma:1;
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unsigned int cpuavx512vbmi:1;
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unsigned int cpumwaitx:1;
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@ -5891,12 +5891,6 @@ clwb, 1, 0x660fae, 0x6, 2, CpuCLWB, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_
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// CLWB instructions end.
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// PCOMMIT instructions.
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pcommit, 0, 0x660fae, 0xf8, 2, CpuPCOMMIT, IgnoreSize|ImmExt|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// PCOMMIT instructions end.
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// AVX512IFMA instructions
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vpmadd52huq, 3, 0x66B5, None, 1, CpuAVX512IFMA, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
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10447
opcodes/i386-tbl.h
10447
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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