x86: refine TPAUSE and UMWAIT
Allowing 64-bit registers is misleading here: Elsewhere these get allowed when there's no difference between either variant, because of 32-bit destination registers having their upper halves zeroed in 64-bit mode. Here, however, they're source registers, and hence specifying 64-bit registers would lead to the ambiguity of whether the upper 32 bits actually matter. Additionally, for proper code generation in 16-bit mode, IgnoreSize is needed on both. And finally, just like for e.g. MONITOR/MWAIT, add variants with all input registers explicitly specified.
This commit is contained in:
Jan Beulich
parent
e15a8da9c7
commit
b630c145c0
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@ -1,3 +1,15 @@
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_assemble): Also exclude tpause and umwait
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from having their operands swapped.
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* testsuite/gas/i386/waitpkg.s,
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testsuite/gas/i386/x86-64-waitpkg.s: Add tpause and umwait
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3-operand cases as well as testing of 16-bit code generation.
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* testsuite/gas/i386/waitpkg.d,
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testsuite/gas/i386/waitpkg-intel.d,
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testsuite/gas/i386/x86-64-waitpkg.d,
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testsuite/gas/i386/x86-64-waitpkg-intel.d: Adjust expectations.
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2020-03-04 Nelson Chu <nelson.chu@sifive.com>
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* config/tc-riscv.c (percent_op_utype): Support the modifier
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@ -4349,16 +4349,19 @@ md_assemble (char *line)
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/* Now we've parsed the mnemonic into a set of templates, and have the
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operands at hand. */
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/* All Intel opcodes have reversed operands except for "bound", "enter"
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"monitor*", and "mwait*". We also don't reverse intersegment "jmp"
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and "call" instructions with 2 immediate operands so that the immediate
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segment precedes the offset, as it does when in AT&T mode. */
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/* All Intel opcodes have reversed operands except for "bound", "enter",
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"monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
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intersegment "jmp" and "call" instructions with 2 immediate operands so
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that the immediate segment precedes the offset, as it does when in AT&T
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mode. */
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if (intel_syntax
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&& i.operands > 1
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&& (strcmp (mnemonic, "bound") != 0)
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&& (strcmp (mnemonic, "invlpga") != 0)
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&& (strncmp (mnemonic, "monitor", 7) != 0)
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&& (strncmp (mnemonic, "mwait", 5) != 0)
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&& (strcmp (mnemonic, "tpause") != 0)
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&& (strcmp (mnemonic, "umwait") != 0)
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&& !(operand_type_check (i.types[0], imm)
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&& operand_type_check (i.types[1], imm)))
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swap_operands ();
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@ -12,5 +12,17 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*f3 0f ae f0[ ]*umonitor eax
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[ ]*[a-f0-9]+:[ ]*67 f3 0f ae f1[ ]*umonitor cx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f3[ ]*umwait ebx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f3[ ]*tpause ebx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f7[ ]*umwait edi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f7[ ]*tpause edi
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[ ]*[a-f0-9]+:[ ]*67 f3 0f ae f0[ ]*umonitor ax
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[ ]*[a-f0-9]+:[ ]*f3 0f ae f1[ ]*umonitor ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f3[ ]*umwait ebx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f3[ ]*tpause ebx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f7[ ]*umwait edi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f7[ ]*tpause edi
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#pass
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@ -12,5 +12,17 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*f3 0f ae f0[ ]*umonitor %eax
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[ ]*[a-f0-9]+:[ ]*67 f3 0f ae f1[ ]*umonitor %cx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f3[ ]*umwait %ebx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f3[ ]*tpause %ebx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f7[ ]*umwait %edi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f7[ ]*tpause %edi
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[ ]*[a-f0-9]+:[ ]*67 f3 0f ae f0[ ]*umonitor %ax
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[ ]*[a-f0-9]+:[ ]*f3 0f ae f1[ ]*umonitor %ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f3[ ]*umwait %ebx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
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[ ]*[a-f0-9]+:[ ]*66 0f ae f3[ ]*tpause %ebx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f7[ ]*umwait %edi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f7[ ]*tpause %edi
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#pass
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@ -2,7 +2,19 @@
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.text
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_start:
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.rept 2
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umonitor %eax
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umonitor %cx
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umwait %ecx
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umwait %ebx, %edx, %eax
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tpause %ecx
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tpause %ebx, %edx, %eax
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.intel_syntax noprefix
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umwait edi, edx, eax
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tpause edi, edx, eax
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.att_syntax prefix
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.code16
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.endr
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@ -13,11 +13,11 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*f3 41 0f ae f2[ ]*umonitor r10
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[ ]*[a-f0-9]+:[ ]*67 f3 41 0f ae f2[ ]*umonitor r10d
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait ecx
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10d
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait r10d
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f7[ ]*umwait edi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause ecx
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10d
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause r10d
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[ ]*[a-f0-9]+:[ ]*66 0f ae f7[ ]*tpause edi
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f6[ ]*umwait esi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f6[ ]*tpause esi
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#pass
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@ -13,11 +13,11 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*f3 41 0f ae f2[ ]*umonitor %r10
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[ ]*[a-f0-9]+:[ ]*67 f3 41 0f ae f2[ ]*umonitor %r10d
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f1[ ]*umwait %ecx
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10d
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[ ]*[a-f0-9]+:[ ]*f2 41 0f ae f2[ ]*umwait %r10d
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f7[ ]*umwait %edi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f1[ ]*tpause %ecx
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10d
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[ ]*[a-f0-9]+:[ ]*66 41 0f ae f2[ ]*tpause %r10d
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[ ]*[a-f0-9]+:[ ]*66 0f ae f7[ ]*tpause %edi
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[ ]*[a-f0-9]+:[ ]*f2 0f ae f6[ ]*umwait %esi
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[ ]*[a-f0-9]+:[ ]*66 0f ae f6[ ]*tpause %esi
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#pass
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@ -6,10 +6,13 @@ _start:
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umonitor %r10
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umonitor %r10d
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umwait %ecx
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umwait %rcx
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umwait %r10
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umwait %r10d
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umwait %edi, %edx, %eax
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tpause %ecx
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tpause %rcx
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tpause %r10
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tpause %r10d
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tpause %edi, %edx, %eax
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.intel_syntax noprefix
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umwait esi, edx, eax
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tpause esi, edx, eax
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@ -1,3 +1,9 @@
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
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template.
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* i386-tbl.h: Re-generate.
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2020-03-04 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
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@ -4763,10 +4763,10 @@ pconfig, 0, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS
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// WAITPKG instructions.
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umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG, Modrm|AddrPrefixOpReg, { Reg16|Reg32|Reg64 }
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tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
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umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
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tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
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tpause, 3, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegD|Dword, Acc|Dword }
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umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
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umwait, 3, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegD|Dword, Acc|Dword }
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// WAITPKG instructions end.
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@ -58351,10 +58351,26 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "tpause", 0x660fae, 0x6, 2, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "umwait", 0xf20fae, 0x6, 2, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -58363,10 +58379,26 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "umwait", 0xf20fae, 0x6, 2, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "cldemote", 0x0f1c, 0x0, 2, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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