RISC-V: Correct printing of MSTATUS and MISA.
* riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add comment for SD field, and correct xlen calculation. For MISA, add comment for MXL field, add call to register_size, and correct base calculation.
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@ -1,3 +1,10 @@
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2018-12-13 Jim Wilson <jimw@sifive.com>
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* riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add
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comment for SD field, and correct xlen calculation. For MISA, add
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comment for MXL field, add call to register_size, and correct base
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calculation.
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2018-12-13 Stafford Horne <shorne@gmail.com>
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* NEWS(New targets): Add or1k*-*-linux*.
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@ -701,8 +701,10 @@ riscv_print_one_register_info (struct gdbarch *gdbarch,
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int size = register_size (gdbarch, regnum);
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unsigned xlen;
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/* The SD field is always in the upper bit of MSTATUS, regardless
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of the number of bits in MSTATUS. */
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d = value_as_long (val);
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xlen = size * 4;
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xlen = size * 8;
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fprintf_filtered (file,
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"\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
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"FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
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@ -731,9 +733,13 @@ riscv_print_one_register_info (struct gdbarch *gdbarch,
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int base;
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unsigned xlen, i;
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LONGEST d;
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int size = register_size (gdbarch, regnum);
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/* The MXL field is always in the upper two bits of MISA,
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regardless of the number of bits in MISA. Mask out other
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bits to ensure we have a positive value. */
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d = value_as_long (val);
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base = d >> 30;
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base = (d >> ((size * 8) - 2)) & 0x3;
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xlen = 16;
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for (; base > 0; base--)
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