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RISC-V: Correct printing of MSTATUS and MISA. 

* riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add
	comment for SD field, and correct xlen calculation.  For MISA, add
	comment for MXL field, add call to register_size, and correct base
	calculation.
This commit is contained in:
Jim Wilson 2018-12-13 10:48:23 -08:00
parent 0903806253
commit b7c8601a7f
2 changed files with 15 additions and 2 deletions
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7
gdb/ChangeLog
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@ -1,3 +1,10 @@
2018-12-13 Jim Wilson <jimw@sifive.com>
* riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add
comment for SD field, and correct xlen calculation. For MISA, add
comment for MXL field, add call to register_size, and correct base
calculation.
2018-12-13 Stafford Horne <shorne@gmail.com>
* NEWS(New targets): Add or1k*-*-linux*.

10
gdb/riscv-tdep.c
View File

@ -701,8 +701,10 @@ riscv_print_one_register_info (struct gdbarch *gdbarch,
int size = register_size (gdbarch, regnum);
unsigned xlen;
/* The SD field is always in the upper bit of MSTATUS, regardless
of the number of bits in MSTATUS. */
d = value_as_long (val);
xlen = size * 4;
xlen = size * 8;
fprintf_filtered (file,
"\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
"FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
@ -731,9 +733,13 @@ riscv_print_one_register_info (struct gdbarch *gdbarch,
int base;
unsigned xlen, i;
LONGEST d;
int size = register_size (gdbarch, regnum);
/* The MXL field is always in the upper two bits of MISA,
regardless of the number of bits in MISA. Mask out other
bits to ensure we have a positive value. */
d = value_as_long (val);
base = d >> 30;
base = (d >> ((size * 8) - 2)) & 0x3;
xlen = 16;
for (; base > 0; base--)