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MSP430: Fix simulator execution of RRUX instruction 

The MSP430X RRUX instruction (unsigned right shift) is synthesized as
the RRC (rotate right through carry) instruction, but with the ZC
(zero carry) bit of the opcode extention word set.

Ensure the carry flag is ignored when the ZC bit is set.

sim/msp430/ChangeLog:

2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
	an RRC instruction, if the ZC bit of the extension word is set.

sim/testsuite/sim/msp430/ChangeLog:

2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	* rrux.s: New test.
This commit is contained in:
Jozef Lawrynowicz 2020-01-22 21:44:54 +00:00
parent be4c5e58bd
commit b7dcc42dfd
4 changed files with 27 additions and 2 deletions
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5
sim/msp430/ChangeLog
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@ -1,3 +1,8 @@
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
an RRC instruction, if the ZC bit of the extension word is set.
2017-09-06 John Baldwin <jhb@FreeBSD.org>
* configure: Regenerate.

6
sim/msp430/msp430-sim.c
View File

@ -1292,8 +1292,10 @@ msp430_step_once (SIM_DESC sd)
u1 = SRC;
carry_to_use = u1 & 1;
uresult = u1 >> 1;
if (SR & MSP430_FLAG_C)
uresult |= (1 << (opcode->size - 1));
/* If the ZC bit of the opcode is set, it means we are synthesizing
RRUX, so the carry bit must be ignored. */
if (opcode->zc == 0 && (SR & MSP430_FLAG_C))
uresult |= (1 << (opcode->size - 1));
TRACE_ALU (MSP430_CPU (sd), "RRC: %#x >>= %#x",
u1, uresult);
DEST (uresult);

4
sim/testsuite/sim/msp430/ChangeLog
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@ -1,3 +1,7 @@
2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* rrux.s: New test.
2016-01-05 Nick Clifton <nickc@redhat.com>
* testutils.inc (__pass): Use the LMA addresses of the _passmsg

14
sim/testsuite/sim/msp430/rrux.s Normal file
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@ -0,0 +1,14 @@
# check that rrux (synthesized as rrc with ZC bit set) works.
# mach: msp430
.include "testutils.inc"
start
setc ; set the carry bit to ensure ZC bit is obeyed
mov.w #16, r10
rrux.w r10
cmp.w #8, r10
jeq 1f
fail
1: pass