* config/tc-xtensa.c (xg_assembly_relax): Comment termination rules.
(frag_format_size): Handle RELAX_IMMED_STEP3. (xtensa_relax_frag, md_convert_frag): Likewise. * config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_IMMED_STEP3. (RELAX_IMMED_MAXSTEPS): Adjust. * config/xtensa-relax.c (widen_spec_list): Add transitions from wide branches to branch-over-jumps. (build_transition): Handle wide branches in transition patterns.
This commit is contained in:
Bob Wilson
parent
184d813c13
commit
b81bf389ec
@ -1,3 +1,14 @@
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2007-06-22 Sterling Augustine <sterling@tensilica.com>
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* config/tc-xtensa.c (xg_assembly_relax): Comment termination rules.
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(frag_format_size): Handle RELAX_IMMED_STEP3.
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(xtensa_relax_frag, md_convert_frag): Likewise.
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* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_IMMED_STEP3.
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(RELAX_IMMED_MAXSTEPS): Adjust.
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* config/xtensa-relax.c (widen_spec_list): Add transitions from
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wide branches to branch-over-jumps.
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(build_transition): Handle wide branches in transition patterns.
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2007-06-22 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (disp_size): New.
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@ -3498,7 +3498,33 @@ xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
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/* Relax the assembly instruction at least "min_steps".
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Return the number of steps taken. */
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Return the number of steps taken.
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For relaxation to correctly terminate, every relaxation chain must
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terminate in one of two ways:
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1. If the chain from one instruction to the next consists entirely of
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single instructions, then the chain *must* handle all possible
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immediates without failing. It must not ever fail because an
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immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
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chain is one example. L32R loads 32 bits, and there cannot be an
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immediate larger than 32 bits, so it satisfies this condition.
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Single instruction relaxation chains are as defined by
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xg_is_single_relaxable_instruction.
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2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
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BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
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Strictly speaking, in most cases you can violate condition 1 and be OK
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-- in particular when the last two instructions have the same single
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size. But nevertheless, you should guarantee the above two conditions.
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We could fix this so that single-instruction expansions correctly
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terminate when they can't handle the range, but the error messages are
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worse, and it actually turns out that in every case but one (18-bit wide
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branches), you need a multi-instruction expansion to get the full range
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anyway. And because 18-bit branches are handled identically to 15-bit
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branches, there isn't any point in changing it. */
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static int
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xg_assembly_relax (IStack *istack,
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@ -3511,12 +3537,9 @@ xg_assembly_relax (IStack *istack,
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{
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int steps_taken = 0;
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/* assert (has no symbolic operands)
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Some of its immeds don't fit.
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Try to build a relaxed version.
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This may go through a couple of stages
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of single instruction transformations before
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we get there. */
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/* Some of its immeds don't fit. Try to build a relaxed version.
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This may go through a couple of stages of single instruction
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transformations before we get there. */
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TInsn single_target;
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TInsn current_insn;
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@ -4384,7 +4407,8 @@ frag_format_size (const fragS *fragP)
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/* If an instruction is about to grow, return the longer size. */
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if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
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|| fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
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|| fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
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|| fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
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return 3;
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if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
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@ -8324,6 +8348,7 @@ xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
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case RELAX_IMMED:
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case RELAX_IMMED_STEP1:
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case RELAX_IMMED_STEP2:
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case RELAX_IMMED_STEP3:
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/* Place the immediate. */
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new_stretch += relax_frag_immed
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(now_seg, fragP, stretch,
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@ -9041,6 +9066,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
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case RELAX_IMMED:
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case RELAX_IMMED_STEP1:
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case RELAX_IMMED_STEP2:
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case RELAX_IMMED_STEP3:
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/* Place the immediate. */
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convert_frag_immed
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(sec, fragp,
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@ -131,18 +131,20 @@ enum xtensa_relax_statesE
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RELAX_IMMED,
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/* The last instruction in this fragment (at->fr_opcode) contains
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the value defined by fr_symbol (fr_offset = 0). If the value
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does not fit, use the specified expansion. This is similar to
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"NARROW", except that these may not be expanded in order to align
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code. */
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an immediate or symbol. If the value does not fit, relax the
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opcode using expansions from the relax table. */
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RELAX_IMMED_STEP1,
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/* The last instruction in this fragment (at->fr_opcode) contains a
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literal. It has already been expanded at least 1 step. */
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literal. It has already been expanded 1 step. */
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RELAX_IMMED_STEP2,
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/* The last instruction in this fragment (at->fr_opcode) contains a
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literal. It has already been expanded at least 2 steps. */
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literal. It has already been expanded 2 steps. */
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RELAX_IMMED_STEP3,
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/* The last instruction in this fragment (at->fr_opcode) contains a
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literal. It has already been expanded 3 steps. */
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RELAX_SLOTS,
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/* There are instructions within the last VLIW instruction that need
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@ -179,7 +181,7 @@ enum xtensa_relax_statesE
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/* This is used as a stopper to bound the number of steps that
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can be taken. */
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#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP2 - RELAX_IMMED)
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#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP3 - RELAX_IMMED)
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struct xtensa_frag_type
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{
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@ -247,7 +247,10 @@ struct string_pattern_pair_struct
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addi.n a4, 0x1010
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=> addi a4, 0x1010
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=> addmi a4, 0x1010
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=> addmi a4, 0x1000, addi a4, 0x10. */
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=> addmi a4, 0x1000, addi a4, 0x10.
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See the comments in xg_assembly_relax for some important details
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regarding how these chains must be built. */
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static string_pattern_pair widen_spec_list[] =
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{
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@ -380,6 +383,10 @@ static string_pattern_pair widen_spec_list[] =
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{"bnez %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%LABEL;j %label;LABEL"},
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{"beqz %as,%label", "bnez %as,%LABEL;j %label;LABEL"},
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{"bnez %as,%label", "beqz %as,%LABEL;j %label;LABEL"},
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{"WIDE.beqz %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%LABEL;j %label;LABEL"},
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{"WIDE.bnez %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%LABEL;j %label;LABEL"},
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{"WIDE.beqz %as,%label", "bnez %as,%LABEL;j %label;LABEL"},
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{"WIDE.bnez %as,%label", "beqz %as,%LABEL;j %label;LABEL"},
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/* Widening expect-taken branches. */
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{"beqzt %as,%label ? IsaUsePredictedBranches", "bnez %as,%LABEL;j %label;LABEL"},
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@ -415,6 +422,29 @@ static string_pattern_pair widen_spec_list[] =
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{"bbc %as,%at,%label", "bbs %as,%at,%LABEL;j %label;LABEL"},
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{"bbs %as,%at,%label", "bbc %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bgez %as,%label", "bltz %as,%LABEL;j %label;LABEL"},
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{"WIDE.bltz %as,%label", "bgez %as,%LABEL;j %label;LABEL"},
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{"WIDE.beqi %as,%imm,%label", "bnei %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.bnei %as,%imm,%label", "beqi %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.bgei %as,%imm,%label", "blti %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.blti %as,%imm,%label", "bgei %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.bgeui %as,%imm,%label", "bltui %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.bltui %as,%imm,%label", "bgeui %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.bbci %as,%imm,%label", "bbsi %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.bbsi %as,%imm,%label", "bbci %as,%imm,%LABEL;j %label;LABEL"},
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{"WIDE.beq %as,%at,%label", "bne %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bne %as,%at,%label", "beq %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bge %as,%at,%label", "blt %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.blt %as,%at,%label", "bge %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bgeu %as,%at,%label", "bltu %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bltu %as,%at,%label", "bgeu %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bany %as,%at,%label", "bnone %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bnone %as,%at,%label", "bany %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.ball %as,%at,%label", "bnall %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bnall %as,%at,%label", "ball %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bbc %as,%at,%label", "bbs %as,%at,%LABEL;j %label;LABEL"},
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{"WIDE.bbs %as,%at,%label", "bbc %as,%at,%LABEL;j %label;LABEL"},
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/* Expanding calls with literals. */
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{"call0 %label,%ar0 ? IsaUseL32R",
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"LITERAL %label; l32r a0,%LITERAL; callx0 a0,%ar0"},
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@ -1571,7 +1601,10 @@ build_transition (insn_pattern *initial_insn,
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precond_e *precond;
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insn_repl_e *r;
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opcode = xtensa_opcode_lookup (isa, initial_insn->t.opcode_name);
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if (!wide_branch_opcode (initial_insn->t.opcode_name, ".w18", &opcode)
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&& !wide_branch_opcode (initial_insn->t.opcode_name, ".w15", &opcode))
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opcode = xtensa_opcode_lookup (isa, initial_insn->t.opcode_name);
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if (opcode == XTENSA_UNDEFINED)
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{
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/* It is OK to not be able to translate some of these opcodes. */
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