[BINUTILS, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
This commit is contained in:
Sudakshina Das
parent
2ecde2b632
commit
b83b4b1382
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@ -1,3 +1,15 @@
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2019-05-01 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_operands): Add case for
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AARCH64_OPND_TME_UIMM16.
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(aarch64_features): Add "tme".
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* doc/c-aarch64.texi: Document the same.
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* testsuite/gas/aarch64/tme-invalid.d: New test.
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* testsuite/gas/aarch64/tme-invalid.l: New test.
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* testsuite/gas/aarch64/tme-invalid.s: New test.
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* testsuite/gas/aarch64/tme.d: New test.
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* testsuite/gas/aarch64/tme.s: New test.
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2019-04-29 John Darrington <john@darrington.wattle.id.au>
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* testsuite/gas/s12z/truncated.d: New file.
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@ -5752,6 +5752,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_CCMP_IMM:
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case AARCH64_OPND_SIMM5:
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case AARCH64_OPND_FBITS:
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case AARCH64_OPND_TME_UIMM16:
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case AARCH64_OPND_UIMM4:
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case AARCH64_OPND_UIMM4_ADDG:
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case AARCH64_OPND_UIMM10:
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@ -8845,6 +8846,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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AARCH64_FEATURE (AARCH64_FEATURE_F16
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| AARCH64_FEATURE_SIMD
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| AARCH64_FEATURE_COMPNUM, 0)},
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{"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME, 0),
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AARCH64_ARCH_NONE},
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{"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_F16
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| AARCH64_FEATURE_SIMD, 0)},
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@ -194,6 +194,8 @@ automatically cause those extensions to be disabled.
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@tab Enable Speculative Store Bypassing Safe state read and write.
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@item @code{memtag} @tab ARMv8.5-A @tab No
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@tab Enable ARMv8.5-A Memory Tagging Extensions.
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@item @code{tme} @tab ARMv8-A @tab No
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@tab Enable Transactional Memory Extensions.
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@end multitable
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@node AArch64 Syntax
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@ -0,0 +1,4 @@
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#name: Invalid TME instructions
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#as: -march=armv8-a+tme
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#source: tme-invalid.s
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#error_output: tme-invalid.l
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@ -0,0 +1,26 @@
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[^:]*: Assembler messages:
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.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `tcancel -1'
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.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `tcancel 65536'
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.*: Error: immediate value out of range 0 to 65535 at operand 1 -- `tcancel 0x10000'
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.*: Error: constant expression required at operand 1 -- `tcancel 1b'
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.*: Error: immediate operand required at operand 1 -- `tcancel w1'
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.*: Error: immediate operand required at operand 1 -- `tcancel x1'
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.*: Error: immediate operand required at operand 1 -- `tcancel w23'
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.*: Error: immediate operand required at operand 1 -- `tcancel x23'
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.*: Error: immediate operand required at operand 1 -- `tcancel wzr'
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.*: Error: immediate operand required at operand 1 -- `tcancel xzr'
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.*: Error: constant expression required at operand 1 -- `tcancel wsp'
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.*: Error: constant expression required at operand 1 -- `tcancel xsp'
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.*: Error: constant expression required at operand 1 -- `tcancel sp'
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.*: Error: operand 1 must be an integer register -- `tstart'
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.*: Error: operand mismatch -- `tstart w1'
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.*: Info: did you mean this\?
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.*: Info: tstart x1
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.*: Error: operand mismatch -- `tstart w17'
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.*: Info: did you mean this\?
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.*: Info: tstart x17
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.*: Error: operand mismatch -- `tstart wzr'
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.*: Info: did you mean this\?
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.*: Info: tstart xzr
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.*: Error: operand 1 must be an integer register -- `tstart wsp'
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.*: Error: operand 1 must be an integer register -- `tstart xsp'
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@ -0,0 +1,28 @@
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// Instructions in this file are invalid.
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// Other files provide more extensive testing of valid instructions;
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# tcancel only accept 16bit unsigned constant immediate.
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1:
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tcancel -1
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tcancel 65536
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tcancel 0x10000
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tcancel 1b
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# tcancel doesn't accept any register.
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tcancel w1
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tcancel x1
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tcancel w23
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tcancel x23
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tcancel wzr
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tcancel xzr
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tcancel wsp
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tcancel xsp
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tcancel sp
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# tstart must has one X register operand.
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tstart
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tstart w1
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tstart w17
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tstart wzr
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tstart wsp
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tstart xsp
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@ -0,0 +1,22 @@
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#as: -march=armv8-a+tme
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#objdump: -dr
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.* file format .*
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Disassembly of section .*:
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.* <.*>:
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.*: d5233060 tstart x0
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.*: d5233060 tstart x0
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.*: d523306f tstart x15
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.*: d523306f tstart x15
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.*: d523307e tstart x30
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.*: d523307e tstart x30
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.*: d503307f tcommit
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.*: d503307f tcommit
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.*: d5233160 ttest x0
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.*: d523317e ttest x30
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.*: d4600000 tcancel #0
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.*: d47fffe0 tcancel #65535
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.*: d47fffe0 tcancel #65535
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.*: d4600140 tcancel #10
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@ -0,0 +1,14 @@
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tstart x0
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TSTART X0
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tstart x15
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TSTART X15
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tstart x30
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TSTART X30
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tcommit
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TCOMMIT
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ttest x0
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TTEST X30
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tcancel 0
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TCANCEL 65535
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tcancel 0xffff
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TCANCEL 0XA
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@ -1,3 +1,8 @@
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2019-05-01 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
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(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
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2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
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Faraz Shahbazker <fshahbazker@wavecomp.com>
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@ -86,7 +86,8 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_SSBS 0x800000000000ULL
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/* Memory Tagging Extension. */
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#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
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/* Transactional Memory Extension. */
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#define AARCH64_FEATURE_TME 0x2000000000000ULL
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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@ -409,6 +410,7 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
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AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
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AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
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AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
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AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
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};
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@ -1,3 +1,16 @@
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2019-05-01 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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* aarch64-opc.c (operand_general_constraint_met_p): Add case for
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AARCH64_OPND_TME_UIMM16.
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(aarch64_print_operand): Likewise.
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* aarch64-tbl.h (QL_IMM_NIL): New.
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(TME): New.
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(_TME_INSN): New.
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(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
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2019-04-29 John Darrington <john@darrington.wattle.id.au>
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* s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
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@ -426,165 +426,165 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1183: /* movz */
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value = 1183; /* --> movz. */
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break;
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case 1230: /* autibsp */
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case 1229: /* autibz */
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case 1228: /* autiasp */
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case 1227: /* autiaz */
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case 1226: /* pacibsp */
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case 1225: /* pacibz */
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case 1224: /* paciasp */
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case 1223: /* paciaz */
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case 1204: /* psb */
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case 1203: /* esb */
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case 1202: /* autib1716 */
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case 1201: /* autia1716 */
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case 1200: /* pacib1716 */
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case 1199: /* pacia1716 */
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case 1198: /* xpaclri */
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case 1197: /* sevl */
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case 1196: /* sev */
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case 1195: /* wfi */
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case 1194: /* wfe */
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case 1193: /* yield */
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case 1192: /* bti */
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case 1191: /* csdb */
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case 1190: /* nop */
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case 1189: /* hint */
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value = 1189; /* --> hint. */
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case 1234: /* autibsp */
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case 1233: /* autibz */
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case 1232: /* autiasp */
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case 1231: /* autiaz */
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case 1230: /* pacibsp */
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case 1229: /* pacibz */
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case 1228: /* paciasp */
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case 1227: /* paciaz */
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case 1208: /* psb */
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case 1207: /* esb */
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case 1206: /* autib1716 */
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case 1205: /* autia1716 */
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case 1204: /* pacib1716 */
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case 1203: /* pacia1716 */
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case 1202: /* xpaclri */
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case 1201: /* sevl */
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case 1200: /* sev */
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case 1199: /* wfi */
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case 1198: /* wfe */
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case 1197: /* yield */
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case 1196: /* bti */
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case 1195: /* csdb */
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case 1194: /* nop */
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case 1193: /* hint */
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value = 1193; /* --> hint. */
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break;
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case 1208: /* pssbb */
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case 1207: /* ssbb */
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case 1206: /* dsb */
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value = 1206; /* --> dsb. */
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case 1212: /* pssbb */
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case 1211: /* ssbb */
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case 1210: /* dsb */
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value = 1210; /* --> dsb. */
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break;
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case 1219: /* cpp */
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case 1218: /* dvp */
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case 1217: /* cfp */
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case 1216: /* tlbi */
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case 1215: /* ic */
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case 1214: /* dc */
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case 1213: /* at */
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case 1212: /* sys */
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value = 1212; /* --> sys. */
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case 1223: /* cpp */
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case 1222: /* dvp */
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case 1221: /* cfp */
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case 1220: /* tlbi */
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case 1219: /* ic */
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case 1218: /* dc */
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case 1217: /* at */
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case 1216: /* sys */
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value = 1216; /* --> sys. */
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break;
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case 2028: /* bic */
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case 1278: /* and */
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value = 1278; /* --> and. */
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case 2032: /* bic */
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case 1282: /* and */
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value = 1282; /* --> and. */
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break;
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case 1261: /* mov */
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case 1280: /* and */
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value = 1280; /* --> and. */
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case 1265: /* mov */
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case 1284: /* and */
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value = 1284; /* --> and. */
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break;
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case 1265: /* movs */
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case 1281: /* ands */
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value = 1281; /* --> ands. */
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case 1269: /* movs */
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case 1285: /* ands */
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value = 1285; /* --> ands. */
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break;
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case 2029: /* cmple */
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case 1316: /* cmpge */
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value = 1316; /* --> cmpge. */
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case 2033: /* cmple */
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case 1320: /* cmpge */
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value = 1320; /* --> cmpge. */
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break;
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case 2032: /* cmplt */
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case 1319: /* cmpgt */
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value = 1319; /* --> cmpgt. */
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case 2036: /* cmplt */
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case 1323: /* cmpgt */
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value = 1323; /* --> cmpgt. */
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break;
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case 2030: /* cmplo */
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case 1321: /* cmphi */
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value = 1321; /* --> cmphi. */
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case 2034: /* cmplo */
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case 1325: /* cmphi */
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value = 1325; /* --> cmphi. */
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break;
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case 2031: /* cmpls */
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case 1324: /* cmphs */
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value = 1324; /* --> cmphs. */
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break;
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case 1258: /* mov */
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case 1346: /* cpy */
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value = 1346; /* --> cpy. */
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break;
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case 1260: /* mov */
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case 1347: /* cpy */
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value = 1347; /* --> cpy. */
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break;
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case 2039: /* fmov */
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case 1263: /* mov */
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case 1348: /* cpy */
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value = 1348; /* --> cpy. */
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break;
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case 1253: /* mov */
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case 1360: /* dup */
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value = 1360; /* --> dup. */
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break;
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case 1255: /* mov */
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case 1252: /* mov */
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case 1361: /* dup */
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value = 1361; /* --> dup. */
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break;
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case 2038: /* fmov */
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case 1257: /* mov */
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case 1362: /* dup */
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value = 1362; /* --> dup. */
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break;
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case 1256: /* mov */
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case 1363: /* dupm */
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value = 1363; /* --> dupm. */
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break;
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case 2033: /* eon */
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case 1365: /* eor */
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value = 1365; /* --> eor. */
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break;
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case 1266: /* not */
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case 1367: /* eor */
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value = 1367; /* --> eor. */
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break;
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case 1267: /* nots */
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case 1368: /* eors */
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value = 1368; /* --> eors. */
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break;
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case 2034: /* facle */
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case 1373: /* facge */
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value = 1373; /* --> facge. */
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break;
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case 2035: /* faclt */
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case 1374: /* facgt */
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value = 1374; /* --> facgt. */
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break;
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case 2036: /* fcmle */
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case 1387: /* fcmge */
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value = 1387; /* --> fcmge. */
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break;
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case 2037: /* fcmlt */
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case 1389: /* fcmgt */
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value = 1389; /* --> fcmgt. */
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break;
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case 1250: /* fmov */
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case 1395: /* fcpy */
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value = 1395; /* --> fcpy. */
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break;
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case 1249: /* fmov */
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case 1418: /* fdup */
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value = 1418; /* --> fdup. */
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break;
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case 1251: /* mov */
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case 1749: /* orr */
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value = 1749; /* --> orr. */
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break;
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case 2040: /* orn */
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case 1750: /* orr */
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value = 1750; /* --> orr. */
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break;
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case 1254: /* mov */
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case 1752: /* orr */
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value = 1752; /* --> orr. */
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break;
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case 1264: /* movs */
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case 1753: /* orrs */
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value = 1753; /* --> orrs. */
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break;
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case 1259: /* mov */
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case 1815: /* sel */
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value = 1815; /* --> sel. */
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case 2035: /* cmpls */
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case 1328: /* cmphs */
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value = 1328; /* --> cmphs. */
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break;
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case 1262: /* mov */
|
||||
case 1816: /* sel */
|
||||
value = 1816; /* --> sel. */
|
||||
case 1350: /* cpy */
|
||||
value = 1350; /* --> cpy. */
|
||||
break;
|
||||
case 1264: /* mov */
|
||||
case 1351: /* cpy */
|
||||
value = 1351; /* --> cpy. */
|
||||
break;
|
||||
case 2043: /* fmov */
|
||||
case 1267: /* mov */
|
||||
case 1352: /* cpy */
|
||||
value = 1352; /* --> cpy. */
|
||||
break;
|
||||
case 1257: /* mov */
|
||||
case 1364: /* dup */
|
||||
value = 1364; /* --> dup. */
|
||||
break;
|
||||
case 1259: /* mov */
|
||||
case 1256: /* mov */
|
||||
case 1365: /* dup */
|
||||
value = 1365; /* --> dup. */
|
||||
break;
|
||||
case 2042: /* fmov */
|
||||
case 1261: /* mov */
|
||||
case 1366: /* dup */
|
||||
value = 1366; /* --> dup. */
|
||||
break;
|
||||
case 1260: /* mov */
|
||||
case 1367: /* dupm */
|
||||
value = 1367; /* --> dupm. */
|
||||
break;
|
||||
case 2037: /* eon */
|
||||
case 1369: /* eor */
|
||||
value = 1369; /* --> eor. */
|
||||
break;
|
||||
case 1270: /* not */
|
||||
case 1371: /* eor */
|
||||
value = 1371; /* --> eor. */
|
||||
break;
|
||||
case 1271: /* nots */
|
||||
case 1372: /* eors */
|
||||
value = 1372; /* --> eors. */
|
||||
break;
|
||||
case 2038: /* facle */
|
||||
case 1377: /* facge */
|
||||
value = 1377; /* --> facge. */
|
||||
break;
|
||||
case 2039: /* faclt */
|
||||
case 1378: /* facgt */
|
||||
value = 1378; /* --> facgt. */
|
||||
break;
|
||||
case 2040: /* fcmle */
|
||||
case 1391: /* fcmge */
|
||||
value = 1391; /* --> fcmge. */
|
||||
break;
|
||||
case 2041: /* fcmlt */
|
||||
case 1393: /* fcmgt */
|
||||
value = 1393; /* --> fcmgt. */
|
||||
break;
|
||||
case 1254: /* fmov */
|
||||
case 1399: /* fcpy */
|
||||
value = 1399; /* --> fcpy. */
|
||||
break;
|
||||
case 1253: /* fmov */
|
||||
case 1422: /* fdup */
|
||||
value = 1422; /* --> fdup. */
|
||||
break;
|
||||
case 1255: /* mov */
|
||||
case 1753: /* orr */
|
||||
value = 1753; /* --> orr. */
|
||||
break;
|
||||
case 2044: /* orn */
|
||||
case 1754: /* orr */
|
||||
value = 1754; /* --> orr. */
|
||||
break;
|
||||
case 1258: /* mov */
|
||||
case 1756: /* orr */
|
||||
value = 1756; /* --> orr. */
|
||||
break;
|
||||
case 1268: /* movs */
|
||||
case 1757: /* orrs */
|
||||
value = 1757; /* --> orrs. */
|
||||
break;
|
||||
case 1263: /* mov */
|
||||
case 1819: /* sel */
|
||||
value = 1819; /* --> sel. */
|
||||
break;
|
||||
case 1266: /* mov */
|
||||
case 1820: /* sel */
|
||||
value = 1820; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
|
@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 32:
|
||||
case 33:
|
||||
case 34:
|
||||
case 199:
|
||||
case 200:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 35:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
|
|
@ -704,6 +704,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 179:
|
||||
case 180:
|
||||
case 181:
|
||||
case 199:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 43:
|
||||
case 44:
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -223,6 +223,7 @@ const struct aarch64_operand aarch64_operands[] =
|
|||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
|
||||
};
|
||||
|
|
@ -301,17 +302,17 @@ static const unsigned op_enum_table [] =
|
|||
391,
|
||||
413,
|
||||
415,
|
||||
1254,
|
||||
1259,
|
||||
1252,
|
||||
1251,
|
||||
1258,
|
||||
1263,
|
||||
1256,
|
||||
1255,
|
||||
1262,
|
||||
1264,
|
||||
1265,
|
||||
1261,
|
||||
1267,
|
||||
1259,
|
||||
1266,
|
||||
1268,
|
||||
1269,
|
||||
1265,
|
||||
1271,
|
||||
1270,
|
||||
131,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2125,6 +2125,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
case AARCH64_OPND_NZCV:
|
||||
case AARCH64_OPND_CCMP_IMM:
|
||||
case AARCH64_OPND_EXCEPTION:
|
||||
case AARCH64_OPND_TME_UIMM16:
|
||||
case AARCH64_OPND_UIMM4:
|
||||
case AARCH64_OPND_UIMM4_ADDG:
|
||||
case AARCH64_OPND_UIMM7:
|
||||
|
|
@ -3326,6 +3327,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
case AARCH64_OPND_IMMR:
|
||||
case AARCH64_OPND_IMMS:
|
||||
case AARCH64_OPND_FBITS:
|
||||
case AARCH64_OPND_TME_UIMM16:
|
||||
case AARCH64_OPND_SIMM5:
|
||||
case AARCH64_OPND_SVE_SHLIMM_PRED:
|
||||
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
|
||||
|
|
|
|||
|
|
@ -74,6 +74,12 @@
|
|||
QLF2(X,NIL), \
|
||||
}
|
||||
|
||||
/* e.g. TCANCEL #<imm>. */
|
||||
#define QL_IMM_NIL \
|
||||
{ \
|
||||
QLF1(NIL), \
|
||||
}
|
||||
|
||||
/* e.g. B.<cond> <label>. */
|
||||
#define QL_PCREL_NIL \
|
||||
{ \
|
||||
|
|
@ -2198,6 +2204,8 @@ static const aarch64_feature_set aarch64_feature_bti =
|
|||
AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
|
||||
static const aarch64_feature_set aarch64_feature_memtag =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
|
||||
static const aarch64_feature_set aarch64_feature_tme =
|
||||
AARCH64_FEATURE (AARCH64_FEATURE_TME, 0);
|
||||
|
||||
|
||||
#define CORE &aarch64_feature_v8
|
||||
|
|
@ -2233,6 +2241,7 @@ static const aarch64_feature_set aarch64_feature_memtag =
|
|||
#define PREDRES &aarch64_feature_predres
|
||||
#define BTI &aarch64_feature_bti
|
||||
#define MEMTAG &aarch64_feature_memtag
|
||||
#define TME &aarch64_feature_tme
|
||||
|
||||
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
|
|
@ -2300,6 +2309,8 @@ static const aarch64_feature_set aarch64_feature_memtag =
|
|||
{ NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
|
||||
struct aarch64_opcode aarch64_opcode_table[] =
|
||||
{
|
||||
|
|
@ -3564,6 +3575,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
/* PC-rel. addressing. */
|
||||
CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
|
||||
CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
|
||||
/* TME Instructions. */
|
||||
_TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
|
||||
_TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
|
||||
_TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
|
||||
_TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
|
||||
/* System. */
|
||||
CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE),
|
||||
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
|
||||
|
|
@ -4919,5 +4935,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
"an SVE vector register") \
|
||||
Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
|
||||
"a list of SVE vector registers") \
|
||||
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
|
||||
"a 16-bit unsigned immediate for TME tcancel") \
|
||||
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
|
||||
"an indexed SM3 vector immediate")
|
||||
|
|
|
|||
Loading…
Reference in New Issue