* Makefile.in (m32r.o): Depend on cpu.h
(extract.o): Pass -DSCACHE_P.
* mloop.in (extract{16,32}): Update call to m32r_decode.
* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
* sim-main.h: #include "ansidecl.h".
Don't include cpu-opc.h, done by arch.h.
start-sanitize-m32rx
* Makefile.in (M32RX_OBJS): Build m32rx support now.
(m32rx.o): New rule.
* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
(m32rx_h_accums_get): New function.
* mloopx.in: Update call to m32rx_decode. Rewrite exec loop.
* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
end-sanitize-m32rx
This commit is contained in:
Doug Evans
parent
5bd5a5c7a2
commit
b8a9943dd4
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@ -1,3 +1,26 @@
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Thu Feb 5 12:44:31 1998 Doug Evans <devans@seba.cygnus.com>
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* Makefile.in (m32r.o): Depend on cpu.h
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(extract.o): Pass -DSCACHE_P.
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* mloop.in (extract{16,32}): Update call to m32r_decode.
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* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
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* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
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* sim-main.h: #include "ansidecl.h".
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Don't include cpu-opc.h, done by arch.h.
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start-sanitize-m32rx
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* Makefile.in (M32RX_OBJS): Build m32rx support now.
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(m32rx.o): New rule.
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* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
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* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
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(m32rx_h_accums_get): New function.
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* mloopx.in: Update call to m32rx_decode. Rewrite exec loop.
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* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
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end-sanitize-m32rx
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Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -66,48 +66,47 @@ OPS_INCLUDE_DEPS = \
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$(srcdir)/../common/cgen-ops.h
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sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h
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m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
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arch.o: arch.c $(INCLUDE_DEPS) cpu-opc.h
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# M32R objs
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m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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# FIXME: Use of `mono' is wip.
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mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
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rm -f mloop.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -scache -fast m32r $(srcdir)/mloop.in | sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
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-mono -scache -fast m32r $(srcdir)/mloop.in \
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| sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
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mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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decode.o: decode.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpu.h
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extract.o: extract.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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$(CC) -c $(srcdir)/extract.c $(ALL_CFLAGS) -DSCACHE_P
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sem.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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model.o: model.c $(INCLUDE_DEPS) cpu-opc.h cpu.h
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# wip
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#extr-cache.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
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# $(CC) -c $(srcdir)/extract.c -o extr-cache.o -DSCACHE_P $(ALL_CFLAGS)
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sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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$(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
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#sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
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# $(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
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# start-sanitize-m32rx
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# M32RX objs
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m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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# FIXME: Use of `mono' is wip.
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mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
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rm -f mloopx.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) -mono -no-scache -no-fast -parallel m32r $(srcdir)/mloopx.in | sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
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$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
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-mono -no-scache -no-fast -no-parallel \
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m32r $(srcdir)/mloopx.in \
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| sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
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mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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decodex.o: decodex.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu-opc.h cpux.h
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extractx.o: extractx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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semx.o: semx.c decodex.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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modelx.o: modelx.c $(INCLUDE_DEPS) cpu-opc.h cpux.h
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# wip
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#extr-cache.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS)
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# $(CC) -c $(srcdir)/extract.c -o extr-cache.o -DSCACHE_P $(ALL_CFLAGS)
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semx-cache.o: semx.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h
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$(CC) -c $(srcdir)/semx.c -o semx-cache.o -DSCACHE_P $(ALL_CFLAGS)
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# end-sanitize-m32rx
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m32r-clean:
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@ -1,5 +1,7 @@
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/* Simulator header for m32r.
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This file is machine generated with CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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@ -23,25 +25,19 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#ifndef M32R_ARCH_H
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#define M32R_ARCH_H
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#define MAX_INSNS 166
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#include "m32r-opc.h"
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#define TARGET_BIG_ENDIAN 1
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/* Shorthand macro for fetching registers. */
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#define CPU(x) (CPU_CGEN_HW (current_cpu)->x)
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/* Macros to determine which cpus are supported. */
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#define HAVE_CPU_M32R
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/* start-sanitize-m32rx */
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/*#define HAVE_CPU_M32RX*/
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/* end-sanitize-m32rx */
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/* Enum declaration for mode types. */
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typedef enum mode_type {
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MODE_VM, MODE_BI, MODE_QI, MODE_HI,
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MODE_SI, MODE_DI, MODE_UBI, MODE_UQI,
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MODE_UHI, MODE_USI, MODE_UDI, MODE_SF,
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MODE_DF, MODE_XF, MODE_TF, MODE_MAX
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MODE_VM, MODE_BI, MODE_QI, MODE_HI
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, MODE_SI, MODE_DI, MODE_UBI, MODE_UQI
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, MODE_UHI, MODE_USI, MODE_UDI, MODE_SF
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, MODE_DF, MODE_XF, MODE_TF, MODE_MAX
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} MODE_TYPE;
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#define MAX_MODES ((int) MODE_MAX)
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@ -58,8 +54,8 @@ typedef enum model_type {
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/* Enum declaration for unit types. */
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typedef enum unit_type {
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UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_EXEC,
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UNIT_TEST_U_EXEC, UNIT_M32RX_U_EXEC, UNIT_MAX
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UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_EXEC
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, UNIT_TEST_U_EXEC, UNIT_M32RX_U_EXEC, UNIT_MAX
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} UNIT_TYPE;
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#define MAX_UNITS (1)
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321
sim/m32r/cpux.h
321
sim/m32r/cpux.h
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@ -1,5 +1,7 @@
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/* CPU family header for m32rx.
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This file is machine generated with CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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@ -50,12 +52,16 @@ typedef struct {
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DI h_accum;
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#define GET_H_ACCUM() CPU (h_accum)
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#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
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/* start-sanitize-m32rx */
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/* accumulators */
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DI h_accums[2];
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/* end-sanitize-m32rx */
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#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
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#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
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/* start-sanitize-m32rx */
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/* abort flag */
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UBI h_abort;
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/* end-sanitize-m32rx */
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#define GET_H_ABORT() CPU (h_abort)
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#define SET_H_ABORT(x) (CPU (h_abort) = (x))
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/* condition bit */
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@ -96,8 +102,7 @@ typedef struct {
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#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
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} M32RX_CPU_DATA;
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/* FIXME: length parm to decode() is currently unneeded. */
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extern DECODE *m32rx_decode (SIM_CPU *, insn_t /*, int*/);
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extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
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/* The ARGBUF struct. */
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struct argbuf {
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@ -105,7 +110,9 @@ struct argbuf {
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unsigned int length;
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PCADDR addr;
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const struct cgen_insn *opcode;
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/* unsigned long insn; - no longer needed */
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#if ! defined (SCACHE_P)
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insn_t insn;
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#endif
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/* cpu specific data follows */
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union {
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struct { /* e.g. add $dr,$sr */
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@ -240,88 +247,83 @@ struct argbuf {
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UINT f_r1;
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HI f_simm16;
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} fmt_33_ldi16;
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struct { /* e.g. machi $src1,$src2 */
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UINT f_r1;
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UINT f_r2;
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} fmt_34_machi;
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struct { /* e.g. machi $src1,$src2,$acc */
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UINT f_r1;
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UINT f_acc;
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UINT f_r2;
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} fmt_35_machi_a;
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} fmt_34_machi_a;
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struct { /* e.g. mulhi $src1,$src2,$acc */
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UINT f_r1;
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UINT f_acc;
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UINT f_r2;
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} fmt_36_mulhi_a;
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} fmt_35_mulhi_a;
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struct { /* e.g. mv $dr,$sr */
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UINT f_r1;
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UINT f_r2;
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} fmt_37_mv;
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struct { /* e.g. mvfachi $dr */
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UINT f_r1;
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} fmt_38_mvfachi;
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} fmt_36_mv;
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struct { /* e.g. mvfachi $dr,$accs */
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UINT f_r1;
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UINT f_accs;
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} fmt_39_mvfachi_a;
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} fmt_37_mvfachi_a;
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struct { /* e.g. mvfc $dr,$scr */
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UINT f_r1;
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UINT f_r2;
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} fmt_40_mvfc;
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struct { /* e.g. mvtachi $src1 */
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UINT f_r1;
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} fmt_41_mvtachi;
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} fmt_38_mvfc;
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struct { /* e.g. mvtachi $src1,$accs */
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UINT f_r1;
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UINT f_accs;
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} fmt_42_mvtachi_a;
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} fmt_39_mvtachi_a;
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struct { /* e.g. mvtc $sr,$dcr */
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||||
UINT f_r1;
|
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UINT f_r2;
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||||
} fmt_43_mvtc;
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} fmt_40_mvtc;
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||||
struct { /* e.g. nop */
|
||||
int empty;
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||||
} fmt_44_nop;
|
||||
struct { /* e.g. rac */
|
||||
int empty;
|
||||
} fmt_45_rac;
|
||||
} fmt_41_nop;
|
||||
struct { /* e.g. rac $accs */
|
||||
UINT f_accs;
|
||||
} fmt_46_rac_a;
|
||||
struct { /* e.g. seth $dr,$hi16 */
|
||||
} fmt_42_rac_a;
|
||||
struct { /* e.g. rte */
|
||||
int empty;
|
||||
} fmt_43_rte;
|
||||
struct { /* e.g. seth $dr,#$hi16 */
|
||||
UINT f_r1;
|
||||
UHI f_hi16;
|
||||
} fmt_47_seth;
|
||||
} fmt_44_seth;
|
||||
struct { /* e.g. slli $dr,#$uimm5 */
|
||||
UINT f_r1;
|
||||
USI f_uimm5;
|
||||
} fmt_48_slli;
|
||||
} fmt_45_slli;
|
||||
struct { /* e.g. st $src1,@($slo16,$src2) */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
HI f_simm16;
|
||||
} fmt_49_st_d;
|
||||
} fmt_46_st_d;
|
||||
struct { /* e.g. trap #$uimm4 */
|
||||
USI f_uimm4;
|
||||
} fmt_50_trap;
|
||||
} fmt_47_trap;
|
||||
struct { /* e.g. satb $dr,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_51_satb;
|
||||
struct { /* e.g. pcmpbz $src2 */
|
||||
} fmt_48_satb;
|
||||
struct { /* e.g. sat $dr,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_52_pcmpbz;
|
||||
} fmt_49_sat;
|
||||
struct { /* e.g. sadd */
|
||||
int empty;
|
||||
} fmt_53_sadd;
|
||||
} fmt_50_sadd;
|
||||
struct { /* e.g. macwu1 $src1,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_54_macwu1;
|
||||
} fmt_51_macwu1;
|
||||
struct { /* e.g. msblo $src1,$src2 */
|
||||
UINT f_r1;
|
||||
UINT f_r2;
|
||||
} fmt_52_msblo;
|
||||
struct { /* e.g. sc */
|
||||
int empty;
|
||||
} fmt_55_sc;
|
||||
} fmt_53_sc;
|
||||
} fields;
|
||||
#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
|
||||
unsigned long h_gr_get;
|
||||
|
|
@ -840,21 +842,7 @@ struct scache {
|
|||
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||||
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||||
|
||||
#define EXTRACT_FMT_34_MACHI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_34_MACHI_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_35_MACHI_A_VARS \
|
||||
#define EXTRACT_FMT_34_MACHI_A_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -862,7 +850,7 @@ struct scache {
|
|||
UINT f_op23; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_35_MACHI_A_CODE \
|
||||
#define EXTRACT_FMT_34_MACHI_A_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
|
|
@ -870,7 +858,7 @@ struct scache {
|
|||
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_36_MULHI_A_VARS \
|
||||
#define EXTRACT_FMT_35_MULHI_A_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -878,7 +866,7 @@ struct scache {
|
|||
UINT f_op23; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_36_MULHI_A_CODE \
|
||||
#define EXTRACT_FMT_35_MULHI_A_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
|
|
@ -886,35 +874,21 @@ struct scache {
|
|||
f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_37_MV_VARS \
|
||||
#define EXTRACT_FMT_36_MV_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_37_MV_CODE \
|
||||
#define EXTRACT_FMT_36_MV_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_38_MVFACHI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_38_MVFACHI_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_39_MVFACHI_A_VARS \
|
||||
#define EXTRACT_FMT_37_MVFACHI_A_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -922,7 +896,7 @@ struct scache {
|
|||
UINT f_accs; \
|
||||
UINT f_op3; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_39_MVFACHI_A_CODE \
|
||||
#define EXTRACT_FMT_37_MVFACHI_A_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
|
|
@ -930,35 +904,21 @@ struct scache {
|
|||
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
|
||||
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
|
||||
|
||||
#define EXTRACT_FMT_40_MVFC_VARS \
|
||||
#define EXTRACT_FMT_38_MVFC_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_40_MVFC_CODE \
|
||||
#define EXTRACT_FMT_38_MVFC_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_41_MVTACHI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_41_MVTACHI_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_42_MVTACHI_A_VARS \
|
||||
#define EXTRACT_FMT_39_MVTACHI_A_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -966,7 +926,7 @@ struct scache {
|
|||
UINT f_accs; \
|
||||
UINT f_op3; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_42_MVTACHI_A_CODE \
|
||||
#define EXTRACT_FMT_39_MVTACHI_A_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
|
|
@ -974,49 +934,35 @@ struct scache {
|
|||
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
|
||||
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
|
||||
|
||||
#define EXTRACT_FMT_43_MVTC_VARS \
|
||||
#define EXTRACT_FMT_40_MVTC_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_43_MVTC_CODE \
|
||||
#define EXTRACT_FMT_40_MVTC_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_44_NOP_VARS \
|
||||
#define EXTRACT_FMT_41_NOP_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_44_NOP_CODE \
|
||||
#define EXTRACT_FMT_41_NOP_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_45_RAC_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_45_RAC_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_46_RAC_A_VARS \
|
||||
#define EXTRACT_FMT_42_RAC_A_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -1024,7 +970,7 @@ struct scache {
|
|||
UINT f_accs; \
|
||||
UINT f_op3; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_46_RAC_A_CODE \
|
||||
#define EXTRACT_FMT_42_RAC_A_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
|
|
@ -1032,7 +978,21 @@ struct scache {
|
|||
f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
|
||||
f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
|
||||
|
||||
#define EXTRACT_FMT_47_SETH_VARS \
|
||||
#define EXTRACT_FMT_43_RTE_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_43_RTE_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_44_SETH_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -1040,7 +1000,7 @@ struct scache {
|
|||
UINT f_r2; \
|
||||
UINT f_hi16; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_47_SETH_CODE \
|
||||
#define EXTRACT_FMT_44_SETH_CODE \
|
||||
length = 4; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||||
|
|
@ -1048,21 +1008,21 @@ struct scache {
|
|||
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||||
f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
||||
|
||||
#define EXTRACT_FMT_48_SLLI_VARS \
|
||||
#define EXTRACT_FMT_45_SLLI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_shift_op2; \
|
||||
UINT f_uimm5; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_48_SLLI_CODE \
|
||||
#define EXTRACT_FMT_45_SLLI_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
|
||||
f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
|
||||
|
||||
#define EXTRACT_FMT_49_ST_D_VARS \
|
||||
#define EXTRACT_FMT_46_ST_D_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -1070,7 +1030,7 @@ struct scache {
|
|||
UINT f_r2; \
|
||||
int f_simm16; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_49_ST_D_CODE \
|
||||
#define EXTRACT_FMT_46_ST_D_CODE \
|
||||
length = 4; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||||
|
|
@ -1078,21 +1038,21 @@ struct scache {
|
|||
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||||
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||||
|
||||
#define EXTRACT_FMT_50_TRAP_VARS \
|
||||
#define EXTRACT_FMT_47_TRAP_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_uimm4; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_50_TRAP_CODE \
|
||||
#define EXTRACT_FMT_47_TRAP_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_51_SATB_VARS \
|
||||
#define EXTRACT_FMT_48_SATB_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
|
|
@ -1100,7 +1060,7 @@ struct scache {
|
|||
UINT f_r2; \
|
||||
UINT f_uimm16; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_51_SATB_CODE \
|
||||
#define EXTRACT_FMT_48_SATB_CODE \
|
||||
length = 4; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||||
|
|
@ -1108,56 +1068,72 @@ struct scache {
|
|||
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||||
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
||||
|
||||
#define EXTRACT_FMT_52_PCMPBZ_VARS \
|
||||
#define EXTRACT_FMT_49_SAT_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
UINT f_uimm16; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_49_SAT_CODE \
|
||||
length = 4; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||||
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
||||
|
||||
#define EXTRACT_FMT_50_SADD_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_52_PCMPBZ_CODE \
|
||||
#define EXTRACT_FMT_50_SADD_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_53_SADD_VARS \
|
||||
#define EXTRACT_FMT_51_MACWU1_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_53_SADD_CODE \
|
||||
#define EXTRACT_FMT_51_MACWU1_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_54_MACWU1_VARS \
|
||||
#define EXTRACT_FMT_52_MSBLO_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_54_MACWU1_CODE \
|
||||
#define EXTRACT_FMT_52_MSBLO_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||||
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||||
|
||||
#define EXTRACT_FMT_55_SC_VARS \
|
||||
#define EXTRACT_FMT_53_SC_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_op1; \
|
||||
UINT f_r1; \
|
||||
UINT f_op2; \
|
||||
UINT f_r2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_FMT_55_SC_CODE \
|
||||
#define EXTRACT_FMT_53_SC_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||||
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||||
|
|
@ -1269,29 +1245,29 @@ struct parallel_exec {
|
|||
SI sr;
|
||||
} fmt_24_jmp;
|
||||
struct { /* e.g. ld $dr,@$sr */
|
||||
UQI h_memory;
|
||||
UQI h_memory_sr;
|
||||
SI sr;
|
||||
} fmt_25_ld;
|
||||
struct { /* e.g. ld $dr,@($slo16,$sr) */
|
||||
UQI h_memory;
|
||||
UQI h_memory_add_WI_sr_slo16;
|
||||
HI slo16;
|
||||
SI sr;
|
||||
} fmt_26_ld_d;
|
||||
struct { /* e.g. ldb $dr,@$sr */
|
||||
UQI h_memory;
|
||||
UQI h_memory_sr;
|
||||
SI sr;
|
||||
} fmt_27_ldb;
|
||||
struct { /* e.g. ldb $dr,@($slo16,$sr) */
|
||||
UQI h_memory;
|
||||
UQI h_memory_add_WI_sr_slo16;
|
||||
HI slo16;
|
||||
SI sr;
|
||||
} fmt_28_ldb_d;
|
||||
struct { /* e.g. ldh $dr,@$sr */
|
||||
UQI h_memory;
|
||||
UQI h_memory_sr;
|
||||
SI sr;
|
||||
} fmt_29_ldh;
|
||||
struct { /* e.g. ldh $dr,@($slo16,$sr) */
|
||||
UQI h_memory;
|
||||
UQI h_memory_add_WI_sr_slo16;
|
||||
HI slo16;
|
||||
SI sr;
|
||||
} fmt_30_ldh_d;
|
||||
|
|
@ -1304,85 +1280,82 @@ struct parallel_exec {
|
|||
struct { /* e.g. ldi $dr,$slo16 */
|
||||
HI slo16;
|
||||
} fmt_33_ldi16;
|
||||
struct { /* e.g. machi $src1,$src2 */
|
||||
DI accum;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_34_machi;
|
||||
struct { /* e.g. machi $src1,$src2,$acc */
|
||||
DI acc;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_35_machi_a;
|
||||
} fmt_34_machi_a;
|
||||
struct { /* e.g. mulhi $src1,$src2,$acc */
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_36_mulhi_a;
|
||||
} fmt_35_mulhi_a;
|
||||
struct { /* e.g. mv $dr,$sr */
|
||||
SI sr;
|
||||
} fmt_37_mv;
|
||||
struct { /* e.g. mvfachi $dr */
|
||||
DI accum;
|
||||
} fmt_38_mvfachi;
|
||||
} fmt_36_mv;
|
||||
struct { /* e.g. mvfachi $dr,$accs */
|
||||
DI accs;
|
||||
} fmt_39_mvfachi_a;
|
||||
} fmt_37_mvfachi_a;
|
||||
struct { /* e.g. mvfc $dr,$scr */
|
||||
SI scr;
|
||||
} fmt_40_mvfc;
|
||||
struct { /* e.g. mvtachi $src1 */
|
||||
DI accum;
|
||||
SI src1;
|
||||
} fmt_41_mvtachi;
|
||||
} fmt_38_mvfc;
|
||||
struct { /* e.g. mvtachi $src1,$accs */
|
||||
DI accs;
|
||||
SI src1;
|
||||
} fmt_42_mvtachi_a;
|
||||
} fmt_39_mvtachi_a;
|
||||
struct { /* e.g. mvtc $sr,$dcr */
|
||||
SI sr;
|
||||
} fmt_43_mvtc;
|
||||
} fmt_40_mvtc;
|
||||
struct { /* e.g. nop */
|
||||
int empty;
|
||||
} fmt_44_nop;
|
||||
struct { /* e.g. rac */
|
||||
DI accum;
|
||||
} fmt_45_rac;
|
||||
} fmt_41_nop;
|
||||
struct { /* e.g. rac $accs */
|
||||
DI accs;
|
||||
} fmt_46_rac_a;
|
||||
struct { /* e.g. seth $dr,$hi16 */
|
||||
} fmt_42_rac_a;
|
||||
struct { /* e.g. rte */
|
||||
UBI h_bcond_0;
|
||||
UBI h_bie_0;
|
||||
SI h_bpc_0;
|
||||
UBI h_bsm_0;
|
||||
} fmt_43_rte;
|
||||
struct { /* e.g. seth $dr,#$hi16 */
|
||||
UHI hi16;
|
||||
} fmt_47_seth;
|
||||
} fmt_44_seth;
|
||||
struct { /* e.g. slli $dr,#$uimm5 */
|
||||
SI dr;
|
||||
USI uimm5;
|
||||
} fmt_48_slli;
|
||||
} fmt_45_slli;
|
||||
struct { /* e.g. st $src1,@($slo16,$src2) */
|
||||
HI slo16;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_49_st_d;
|
||||
} fmt_46_st_d;
|
||||
struct { /* e.g. trap #$uimm4 */
|
||||
USI uimm4;
|
||||
} fmt_50_trap;
|
||||
} fmt_47_trap;
|
||||
struct { /* e.g. satb $dr,$src2 */
|
||||
int empty;
|
||||
} fmt_51_satb;
|
||||
struct { /* e.g. pcmpbz $src2 */
|
||||
int empty;
|
||||
} fmt_52_pcmpbz;
|
||||
SI src2;
|
||||
} fmt_48_satb;
|
||||
struct { /* e.g. sat $dr,$src2 */
|
||||
UBI condbit;
|
||||
SI src2;
|
||||
} fmt_49_sat;
|
||||
struct { /* e.g. sadd */
|
||||
DI h_accums;
|
||||
DI h_accums;
|
||||
} fmt_53_sadd;
|
||||
DI h_accums_0;
|
||||
DI h_accums_1;
|
||||
} fmt_50_sadd;
|
||||
struct { /* e.g. macwu1 $src1,$src2 */
|
||||
DI h_accums;
|
||||
DI h_accums_1;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_54_macwu1;
|
||||
} fmt_51_macwu1;
|
||||
struct { /* e.g. msblo $src1,$src2 */
|
||||
DI accum;
|
||||
SI src1;
|
||||
SI src2;
|
||||
} fmt_52_msblo;
|
||||
struct { /* e.g. sc */
|
||||
UBI condbit;
|
||||
} fmt_55_sc;
|
||||
} fmt_53_sc;
|
||||
} operands;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,529 @@
|
|||
/* Simulator instruction decoder for m32r.
|
||||
|
||||
This file is machine generated with CGEN.
|
||||
|
||||
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#define WANT_CPU
|
||||
#define WANT_CPU_M32R
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "sim-xcat.h"
|
||||
#include "cpu-sim.h"
|
||||
#include "cpu-opc.h"
|
||||
|
||||
/* FIXME: wip, may eventually only want one form so this would then go
|
||||
away. However, in the mean time, having both keeps a stable version
|
||||
around while the cache version is being developed.
|
||||
It may still be useful to allow two versions to exist though. */
|
||||
#if WITH_SCACHE
|
||||
#define EX(fn) XCONCAT3 (m32r,_ex_,fn)
|
||||
#else
|
||||
#define EX(fn) 0
|
||||
#endif
|
||||
|
||||
#if WITH_SEM_SWITCH_FULL
|
||||
#define FULL(fn) 0
|
||||
#else
|
||||
#define FULL(fn) XCONCAT3 (m32r,_sem_,fn)
|
||||
#endif
|
||||
|
||||
#if WITH_SEM_SWITCH_FAST
|
||||
#define FAST(fn) 0
|
||||
#else
|
||||
#if WITH_SCACHE
|
||||
#define FAST(fn) XCONCAT3 (m32r,_semc_,fn)
|
||||
#else
|
||||
#define FAST(fn) 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*#define DECODE M32R_DECODE*/
|
||||
|
||||
/* The decode_illegal case is currently non-static and the generator doesn't
|
||||
prepend m32r_, so simplify things by handling it here. */
|
||||
#define decode_illegal m32r_decode_illegal
|
||||
|
||||
static DECODE decode_add = { M32R_INSN_ADD, & m32r_cgen_insn_table_entries[M32R_INSN_ADD], EX (fmt_0_add), FULL (add), FAST (add) };
|
||||
static DECODE decode_add3 = { M32R_INSN_ADD3, & m32r_cgen_insn_table_entries[M32R_INSN_ADD3], EX (fmt_1_add3), FULL (add3), FAST (add3) };
|
||||
static DECODE decode_and = { M32R_INSN_AND, & m32r_cgen_insn_table_entries[M32R_INSN_AND], EX (fmt_0_add), FULL (and), FAST (and) };
|
||||
static DECODE decode_and3 = { M32R_INSN_AND3, & m32r_cgen_insn_table_entries[M32R_INSN_AND3], EX (fmt_2_and3), FULL (and3), FAST (and3) };
|
||||
static DECODE decode_or = { M32R_INSN_OR, & m32r_cgen_insn_table_entries[M32R_INSN_OR], EX (fmt_0_add), FULL (or), FAST (or) };
|
||||
static DECODE decode_or3 = { M32R_INSN_OR3, & m32r_cgen_insn_table_entries[M32R_INSN_OR3], EX (fmt_3_or3), FULL (or3), FAST (or3) };
|
||||
static DECODE decode_xor = { M32R_INSN_XOR, & m32r_cgen_insn_table_entries[M32R_INSN_XOR], EX (fmt_0_add), FULL (xor), FAST (xor) };
|
||||
static DECODE decode_xor3 = { M32R_INSN_XOR3, & m32r_cgen_insn_table_entries[M32R_INSN_XOR3], EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
|
||||
static DECODE decode_addi = { M32R_INSN_ADDI, & m32r_cgen_insn_table_entries[M32R_INSN_ADDI], EX (fmt_4_addi), FULL (addi), FAST (addi) };
|
||||
static DECODE decode_addv = { M32R_INSN_ADDV, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV], EX (fmt_0_add), FULL (addv), FAST (addv) };
|
||||
static DECODE decode_addv3 = { M32R_INSN_ADDV3, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV3], EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
|
||||
static DECODE decode_addx = { M32R_INSN_ADDX, & m32r_cgen_insn_table_entries[M32R_INSN_ADDX], EX (fmt_6_addx), FULL (addx), FAST (addx) };
|
||||
static DECODE decode_bc8 = { M32R_INSN_BC8, & m32r_cgen_insn_table_entries[M32R_INSN_BC8], EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
|
||||
static DECODE decode_bc24 = { M32R_INSN_BC24, & m32r_cgen_insn_table_entries[M32R_INSN_BC24], EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
|
||||
static DECODE decode_beq = { M32R_INSN_BEQ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQ], EX (fmt_9_beq), FULL (beq), FAST (beq) };
|
||||
static DECODE decode_beqz = { M32R_INSN_BEQZ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQZ], EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
|
||||
static DECODE decode_bgez = { M32R_INSN_BGEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGEZ], EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
|
||||
static DECODE decode_bgtz = { M32R_INSN_BGTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGTZ], EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
|
||||
static DECODE decode_blez = { M32R_INSN_BLEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLEZ], EX (fmt_10_beqz), FULL (blez), FAST (blez) };
|
||||
static DECODE decode_bltz = { M32R_INSN_BLTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLTZ], EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
|
||||
static DECODE decode_bnez = { M32R_INSN_BNEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BNEZ], EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
|
||||
static DECODE decode_bl8 = { M32R_INSN_BL8, & m32r_cgen_insn_table_entries[M32R_INSN_BL8], EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
|
||||
static DECODE decode_bl24 = { M32R_INSN_BL24, & m32r_cgen_insn_table_entries[M32R_INSN_BL24], EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
|
||||
static DECODE decode_bnc8 = { M32R_INSN_BNC8, & m32r_cgen_insn_table_entries[M32R_INSN_BNC8], EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
|
||||
static DECODE decode_bnc24 = { M32R_INSN_BNC24, & m32r_cgen_insn_table_entries[M32R_INSN_BNC24], EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
|
||||
static DECODE decode_bne = { M32R_INSN_BNE, & m32r_cgen_insn_table_entries[M32R_INSN_BNE], EX (fmt_9_beq), FULL (bne), FAST (bne) };
|
||||
static DECODE decode_bra8 = { M32R_INSN_BRA8, & m32r_cgen_insn_table_entries[M32R_INSN_BRA8], EX (fmt_13_bra8), FULL (bra8), FAST (bra8) };
|
||||
static DECODE decode_bra24 = { M32R_INSN_BRA24, & m32r_cgen_insn_table_entries[M32R_INSN_BRA24], EX (fmt_14_bra24), FULL (bra24), FAST (bra24) };
|
||||
static DECODE decode_cmp = { M32R_INSN_CMP, & m32r_cgen_insn_table_entries[M32R_INSN_CMP], EX (fmt_15_cmp), FULL (cmp), FAST (cmp) };
|
||||
static DECODE decode_cmpi = { M32R_INSN_CMPI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPI], EX (fmt_16_cmpi), FULL (cmpi), FAST (cmpi) };
|
||||
static DECODE decode_cmpu = { M32R_INSN_CMPU, & m32r_cgen_insn_table_entries[M32R_INSN_CMPU], EX (fmt_15_cmp), FULL (cmpu), FAST (cmpu) };
|
||||
static DECODE decode_cmpui = { M32R_INSN_CMPUI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPUI], EX (fmt_17_cmpui), FULL (cmpui), FAST (cmpui) };
|
||||
static DECODE decode_div = { M32R_INSN_DIV, & m32r_cgen_insn_table_entries[M32R_INSN_DIV], EX (fmt_18_div), FULL (div), FAST (div) };
|
||||
static DECODE decode_divu = { M32R_INSN_DIVU, & m32r_cgen_insn_table_entries[M32R_INSN_DIVU], EX (fmt_18_div), FULL (divu), FAST (divu) };
|
||||
static DECODE decode_rem = { M32R_INSN_REM, & m32r_cgen_insn_table_entries[M32R_INSN_REM], EX (fmt_18_div), FULL (rem), FAST (rem) };
|
||||
static DECODE decode_remu = { M32R_INSN_REMU, & m32r_cgen_insn_table_entries[M32R_INSN_REMU], EX (fmt_18_div), FULL (remu), FAST (remu) };
|
||||
static DECODE decode_jl = { M32R_INSN_JL, & m32r_cgen_insn_table_entries[M32R_INSN_JL], EX (fmt_19_jl), FULL (jl), FAST (jl) };
|
||||
static DECODE decode_jmp = { M32R_INSN_JMP, & m32r_cgen_insn_table_entries[M32R_INSN_JMP], EX (fmt_20_jmp), FULL (jmp), FAST (jmp) };
|
||||
static DECODE decode_ld = { M32R_INSN_LD, & m32r_cgen_insn_table_entries[M32R_INSN_LD], EX (fmt_21_ld), FULL (ld), FAST (ld) };
|
||||
static DECODE decode_ld_d = { M32R_INSN_LD_D, & m32r_cgen_insn_table_entries[M32R_INSN_LD_D], EX (fmt_22_ld_d), FULL (ld_d), FAST (ld_d) };
|
||||
static DECODE decode_ldb = { M32R_INSN_LDB, & m32r_cgen_insn_table_entries[M32R_INSN_LDB], EX (fmt_23_ldb), FULL (ldb), FAST (ldb) };
|
||||
static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDB_D], EX (fmt_24_ldb_d), FULL (ldb_d), FAST (ldb_d) };
|
||||
static DECODE decode_ldh = { M32R_INSN_LDH, & m32r_cgen_insn_table_entries[M32R_INSN_LDH], EX (fmt_25_ldh), FULL (ldh), FAST (ldh) };
|
||||
static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDH_D], EX (fmt_26_ldh_d), FULL (ldh_d), FAST (ldh_d) };
|
||||
static DECODE decode_ldub = { M32R_INSN_LDUB, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB], EX (fmt_23_ldb), FULL (ldub), FAST (ldub) };
|
||||
static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB_D], EX (fmt_24_ldb_d), FULL (ldub_d), FAST (ldub_d) };
|
||||
static DECODE decode_lduh = { M32R_INSN_LDUH, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH], EX (fmt_25_ldh), FULL (lduh), FAST (lduh) };
|
||||
static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH_D], EX (fmt_26_ldh_d), FULL (lduh_d), FAST (lduh_d) };
|
||||
static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_LD_PLUS], EX (fmt_21_ld), FULL (ld_plus), FAST (ld_plus) };
|
||||
static DECODE decode_ld24 = { M32R_INSN_LD24, & m32r_cgen_insn_table_entries[M32R_INSN_LD24], EX (fmt_27_ld24), FULL (ld24), FAST (ld24) };
|
||||
static DECODE decode_ldi8 = { M32R_INSN_LDI8, & m32r_cgen_insn_table_entries[M32R_INSN_LDI8], EX (fmt_28_ldi8), FULL (ldi8), FAST (ldi8) };
|
||||
static DECODE decode_ldi16 = { M32R_INSN_LDI16, & m32r_cgen_insn_table_entries[M32R_INSN_LDI16], EX (fmt_29_ldi16), FULL (ldi16), FAST (ldi16) };
|
||||
static DECODE decode_lock = { M32R_INSN_LOCK, & m32r_cgen_insn_table_entries[M32R_INSN_LOCK], EX (fmt_0_add), FULL (lock), FAST (lock) };
|
||||
static DECODE decode_machi = { M32R_INSN_MACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MACHI], EX (fmt_30_machi), FULL (machi), FAST (machi) };
|
||||
static DECODE decode_maclo = { M32R_INSN_MACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MACLO], EX (fmt_30_machi), FULL (maclo), FAST (maclo) };
|
||||
static DECODE decode_macwhi = { M32R_INSN_MACWHI, & m32r_cgen_insn_table_entries[M32R_INSN_MACWHI], EX (fmt_30_machi), FULL (macwhi), FAST (macwhi) };
|
||||
static DECODE decode_macwlo = { M32R_INSN_MACWLO, & m32r_cgen_insn_table_entries[M32R_INSN_MACWLO], EX (fmt_30_machi), FULL (macwlo), FAST (macwlo) };
|
||||
static DECODE decode_mul = { M32R_INSN_MUL, & m32r_cgen_insn_table_entries[M32R_INSN_MUL], EX (fmt_0_add), FULL (mul), FAST (mul) };
|
||||
static DECODE decode_mulhi = { M32R_INSN_MULHI, & m32r_cgen_insn_table_entries[M32R_INSN_MULHI], EX (fmt_15_cmp), FULL (mulhi), FAST (mulhi) };
|
||||
static DECODE decode_mullo = { M32R_INSN_MULLO, & m32r_cgen_insn_table_entries[M32R_INSN_MULLO], EX (fmt_15_cmp), FULL (mullo), FAST (mullo) };
|
||||
static DECODE decode_mulwhi = { M32R_INSN_MULWHI, & m32r_cgen_insn_table_entries[M32R_INSN_MULWHI], EX (fmt_15_cmp), FULL (mulwhi), FAST (mulwhi) };
|
||||
static DECODE decode_mulwlo = { M32R_INSN_MULWLO, & m32r_cgen_insn_table_entries[M32R_INSN_MULWLO], EX (fmt_15_cmp), FULL (mulwlo), FAST (mulwlo) };
|
||||
static DECODE decode_mv = { M32R_INSN_MV, & m32r_cgen_insn_table_entries[M32R_INSN_MV], EX (fmt_31_mv), FULL (mv), FAST (mv) };
|
||||
static DECODE decode_mvfachi = { M32R_INSN_MVFACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACHI], EX (fmt_32_mvfachi), FULL (mvfachi), FAST (mvfachi) };
|
||||
static DECODE decode_mvfaclo = { M32R_INSN_MVFACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACLO], EX (fmt_32_mvfachi), FULL (mvfaclo), FAST (mvfaclo) };
|
||||
static DECODE decode_mvfacmi = { M32R_INSN_MVFACMI, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACMI], EX (fmt_32_mvfachi), FULL (mvfacmi), FAST (mvfacmi) };
|
||||
static DECODE decode_mvfc = { M32R_INSN_MVFC, & m32r_cgen_insn_table_entries[M32R_INSN_MVFC], EX (fmt_33_mvfc), FULL (mvfc), FAST (mvfc) };
|
||||
static DECODE decode_mvtachi = { M32R_INSN_MVTACHI, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACHI], EX (fmt_34_mvtachi), FULL (mvtachi), FAST (mvtachi) };
|
||||
static DECODE decode_mvtaclo = { M32R_INSN_MVTACLO, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACLO], EX (fmt_34_mvtachi), FULL (mvtaclo), FAST (mvtaclo) };
|
||||
static DECODE decode_mvtc = { M32R_INSN_MVTC, & m32r_cgen_insn_table_entries[M32R_INSN_MVTC], EX (fmt_35_mvtc), FULL (mvtc), FAST (mvtc) };
|
||||
static DECODE decode_neg = { M32R_INSN_NEG, & m32r_cgen_insn_table_entries[M32R_INSN_NEG], EX (fmt_31_mv), FULL (neg), FAST (neg) };
|
||||
static DECODE decode_nop = { M32R_INSN_NOP, & m32r_cgen_insn_table_entries[M32R_INSN_NOP], EX (fmt_36_nop), FULL (nop), FAST (nop) };
|
||||
static DECODE decode_not = { M32R_INSN_NOT, & m32r_cgen_insn_table_entries[M32R_INSN_NOT], EX (fmt_31_mv), FULL (not), FAST (not) };
|
||||
static DECODE decode_rac = { M32R_INSN_RAC, & m32r_cgen_insn_table_entries[M32R_INSN_RAC], EX (fmt_37_rac), FULL (rac), FAST (rac) };
|
||||
static DECODE decode_rach = { M32R_INSN_RACH, & m32r_cgen_insn_table_entries[M32R_INSN_RACH], EX (fmt_37_rac), FULL (rach), FAST (rach) };
|
||||
static DECODE decode_rte = { M32R_INSN_RTE, & m32r_cgen_insn_table_entries[M32R_INSN_RTE], EX (fmt_38_rte), FULL (rte), FAST (rte) };
|
||||
static DECODE decode_seth = { M32R_INSN_SETH, & m32r_cgen_insn_table_entries[M32R_INSN_SETH], EX (fmt_39_seth), FULL (seth), FAST (seth) };
|
||||
static DECODE decode_sll = { M32R_INSN_SLL, & m32r_cgen_insn_table_entries[M32R_INSN_SLL], EX (fmt_0_add), FULL (sll), FAST (sll) };
|
||||
static DECODE decode_sll3 = { M32R_INSN_SLL3, & m32r_cgen_insn_table_entries[M32R_INSN_SLL3], EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
|
||||
static DECODE decode_slli = { M32R_INSN_SLLI, & m32r_cgen_insn_table_entries[M32R_INSN_SLLI], EX (fmt_40_slli), FULL (slli), FAST (slli) };
|
||||
static DECODE decode_sra = { M32R_INSN_SRA, & m32r_cgen_insn_table_entries[M32R_INSN_SRA], EX (fmt_0_add), FULL (sra), FAST (sra) };
|
||||
static DECODE decode_sra3 = { M32R_INSN_SRA3, & m32r_cgen_insn_table_entries[M32R_INSN_SRA3], EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
|
||||
static DECODE decode_srai = { M32R_INSN_SRAI, & m32r_cgen_insn_table_entries[M32R_INSN_SRAI], EX (fmt_40_slli), FULL (srai), FAST (srai) };
|
||||
static DECODE decode_srl = { M32R_INSN_SRL, & m32r_cgen_insn_table_entries[M32R_INSN_SRL], EX (fmt_0_add), FULL (srl), FAST (srl) };
|
||||
static DECODE decode_srl3 = { M32R_INSN_SRL3, & m32r_cgen_insn_table_entries[M32R_INSN_SRL3], EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
|
||||
static DECODE decode_srli = { M32R_INSN_SRLI, & m32r_cgen_insn_table_entries[M32R_INSN_SRLI], EX (fmt_40_slli), FULL (srli), FAST (srli) };
|
||||
static DECODE decode_st = { M32R_INSN_ST, & m32r_cgen_insn_table_entries[M32R_INSN_ST], EX (fmt_15_cmp), FULL (st), FAST (st) };
|
||||
static DECODE decode_st_d = { M32R_INSN_ST_D, & m32r_cgen_insn_table_entries[M32R_INSN_ST_D], EX (fmt_41_st_d), FULL (st_d), FAST (st_d) };
|
||||
static DECODE decode_stb = { M32R_INSN_STB, & m32r_cgen_insn_table_entries[M32R_INSN_STB], EX (fmt_15_cmp), FULL (stb), FAST (stb) };
|
||||
static DECODE decode_stb_d = { M32R_INSN_STB_D, & m32r_cgen_insn_table_entries[M32R_INSN_STB_D], EX (fmt_41_st_d), FULL (stb_d), FAST (stb_d) };
|
||||
static DECODE decode_sth = { M32R_INSN_STH, & m32r_cgen_insn_table_entries[M32R_INSN_STH], EX (fmt_15_cmp), FULL (sth), FAST (sth) };
|
||||
static DECODE decode_sth_d = { M32R_INSN_STH_D, & m32r_cgen_insn_table_entries[M32R_INSN_STH_D], EX (fmt_41_st_d), FULL (sth_d), FAST (sth_d) };
|
||||
static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_PLUS], EX (fmt_15_cmp), FULL (st_plus), FAST (st_plus) };
|
||||
static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_MINUS], EX (fmt_15_cmp), FULL (st_minus), FAST (st_minus) };
|
||||
static DECODE decode_sub = { M32R_INSN_SUB, & m32r_cgen_insn_table_entries[M32R_INSN_SUB], EX (fmt_0_add), FULL (sub), FAST (sub) };
|
||||
static DECODE decode_subv = { M32R_INSN_SUBV, & m32r_cgen_insn_table_entries[M32R_INSN_SUBV], EX (fmt_0_add), FULL (subv), FAST (subv) };
|
||||
static DECODE decode_subx = { M32R_INSN_SUBX, & m32r_cgen_insn_table_entries[M32R_INSN_SUBX], EX (fmt_6_addx), FULL (subx), FAST (subx) };
|
||||
static DECODE decode_trap = { M32R_INSN_TRAP, & m32r_cgen_insn_table_entries[M32R_INSN_TRAP], EX (fmt_42_trap), FULL (trap), FAST (trap) };
|
||||
static DECODE decode_unlock = { M32R_INSN_UNLOCK, & m32r_cgen_insn_table_entries[M32R_INSN_UNLOCK], EX (fmt_15_cmp), FULL (unlock), FAST (unlock) };
|
||||
DECODE m32r_decode_illegal = {
|
||||
M32R_INSN_ILLEGAL, & m32r_cgen_insn_table_entries[0],
|
||||
EX (illegal), FULL (illegal),
|
||||
FAST (illegal)
|
||||
};
|
||||
|
||||
/* The order must match that of `labels' in sem-switch.c. */
|
||||
|
||||
DECODE *m32r_decode_vars[] = {
|
||||
& m32r_decode_illegal,
|
||||
& decode_add,
|
||||
& decode_add3,
|
||||
& decode_and,
|
||||
& decode_and3,
|
||||
& decode_or,
|
||||
& decode_or3,
|
||||
& decode_xor,
|
||||
& decode_xor3,
|
||||
& decode_addi,
|
||||
& decode_addv,
|
||||
& decode_addv3,
|
||||
& decode_addx,
|
||||
& decode_bc8,
|
||||
& decode_bc24,
|
||||
& decode_beq,
|
||||
& decode_beqz,
|
||||
& decode_bgez,
|
||||
& decode_bgtz,
|
||||
& decode_blez,
|
||||
& decode_bltz,
|
||||
& decode_bnez,
|
||||
& decode_bl8,
|
||||
& decode_bl24,
|
||||
& decode_bnc8,
|
||||
& decode_bnc24,
|
||||
& decode_bne,
|
||||
& decode_bra8,
|
||||
& decode_bra24,
|
||||
& decode_cmp,
|
||||
& decode_cmpi,
|
||||
& decode_cmpu,
|
||||
& decode_cmpui,
|
||||
& decode_div,
|
||||
& decode_divu,
|
||||
& decode_rem,
|
||||
& decode_remu,
|
||||
& decode_jl,
|
||||
& decode_jmp,
|
||||
& decode_ld,
|
||||
& decode_ld_d,
|
||||
& decode_ldb,
|
||||
& decode_ldb_d,
|
||||
& decode_ldh,
|
||||
& decode_ldh_d,
|
||||
& decode_ldub,
|
||||
& decode_ldub_d,
|
||||
& decode_lduh,
|
||||
& decode_lduh_d,
|
||||
& decode_ld_plus,
|
||||
& decode_ld24,
|
||||
& decode_ldi8,
|
||||
& decode_ldi16,
|
||||
& decode_lock,
|
||||
& decode_machi,
|
||||
& decode_maclo,
|
||||
& decode_macwhi,
|
||||
& decode_macwlo,
|
||||
& decode_mul,
|
||||
& decode_mulhi,
|
||||
& decode_mullo,
|
||||
& decode_mulwhi,
|
||||
& decode_mulwlo,
|
||||
& decode_mv,
|
||||
& decode_mvfachi,
|
||||
& decode_mvfaclo,
|
||||
& decode_mvfacmi,
|
||||
& decode_mvfc,
|
||||
& decode_mvtachi,
|
||||
& decode_mvtaclo,
|
||||
& decode_mvtc,
|
||||
& decode_neg,
|
||||
& decode_nop,
|
||||
& decode_not,
|
||||
& decode_rac,
|
||||
& decode_rach,
|
||||
& decode_rte,
|
||||
& decode_seth,
|
||||
& decode_sll,
|
||||
& decode_sll3,
|
||||
& decode_slli,
|
||||
& decode_sra,
|
||||
& decode_sra3,
|
||||
& decode_srai,
|
||||
& decode_srl,
|
||||
& decode_srl3,
|
||||
& decode_srli,
|
||||
& decode_st,
|
||||
& decode_st_d,
|
||||
& decode_stb,
|
||||
& decode_stb_d,
|
||||
& decode_sth,
|
||||
& decode_sth_d,
|
||||
& decode_st_plus,
|
||||
& decode_st_minus,
|
||||
& decode_sub,
|
||||
& decode_subv,
|
||||
& decode_subx,
|
||||
& decode_trap,
|
||||
& decode_unlock,
|
||||
0
|
||||
};
|
||||
|
||||
/* The decoder needs a slightly different computed goto switch control. */
|
||||
#ifdef __GNUC__
|
||||
#define DECODE_SWITCH(N, X) goto *labels_##N[X];
|
||||
#else
|
||||
#define DECODE_SWITCH(N, X) switch (X)
|
||||
#endif
|
||||
|
||||
/* Given an instruction, return a pointer to its DECODE entry. */
|
||||
|
||||
DECODE *
|
||||
m32r_decode (current_cpu, pc, insn)
|
||||
SIM_CPU *current_cpu;
|
||||
PCADDR pc;
|
||||
insn_t insn;
|
||||
{
|
||||
{
|
||||
#ifdef __GNUC__
|
||||
static void *labels_0[256] = {
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& case_0_28, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && case_0_87,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && case_0_95,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& case_0_112, && case_0_113, && case_0_114, && case_0_115,
|
||||
&& case_0_116, && case_0_117, && case_0_118, && case_0_119,
|
||||
&& case_0_120, && case_0_121, && case_0_122, && case_0_123,
|
||||
&& case_0_124, && case_0_125, && case_0_126, && case_0_127,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& case_0_240, && case_0_241, && case_0_242, && case_0_243,
|
||||
&& case_0_244, && case_0_245, && case_0_246, && case_0_247,
|
||||
&& case_0_248, && case_0_249, && case_0_250, && case_0_251,
|
||||
&& case_0_252, && case_0_253, && case_0_254, && case_0_255,
|
||||
};
|
||||
#endif
|
||||
static DECODE *insns[256] = {
|
||||
&decode_subv, &decode_subx, &decode_sub, &decode_neg,
|
||||
&decode_cmp, &decode_cmpu, &decode_illegal, &decode_illegal,
|
||||
&decode_addv, &decode_addx, &decode_add, &decode_not,
|
||||
&decode_and, &decode_xor, &decode_or, &decode_illegal,
|
||||
&decode_srl, &decode_illegal, &decode_sra, &decode_illegal,
|
||||
&decode_sll, &decode_illegal, &decode_mul, &decode_illegal,
|
||||
&decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal,
|
||||
0, &decode_rte, &decode_illegal, &decode_trap,
|
||||
&decode_stb, &decode_illegal, &decode_sth, &decode_illegal,
|
||||
&decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus,
|
||||
&decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh,
|
||||
&decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal,
|
||||
&decode_mulhi, &decode_mullo, &decode_mulwhi, &decode_mulwlo,
|
||||
&decode_machi, &decode_maclo, &decode_macwhi, &decode_macwlo,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_srli, &decode_srli, &decode_srai, &decode_srai,
|
||||
&decode_slli, &decode_slli, &decode_illegal, 0,
|
||||
&decode_rach, &decode_rac, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, 0,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal,
|
||||
&decode_addv3, &decode_illegal, &decode_add3, &decode_illegal,
|
||||
&decode_and3, &decode_xor3, &decode_or3, &decode_illegal,
|
||||
&decode_div, &decode_divu, &decode_rem, &decode_remu,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal,
|
||||
&decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16,
|
||||
&decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal,
|
||||
&decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d,
|
||||
&decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_beq, &decode_bne, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez,
|
||||
&decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_seth, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
};
|
||||
unsigned int val;
|
||||
val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
|
||||
DECODE_SWITCH (0, val)
|
||||
{
|
||||
CASE (0, 28) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_jl, &decode_jmp,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 87) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_mvtachi, &decode_mvtaclo, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
};
|
||||
unsigned int val = (((insn >> 0) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 95) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_mvfachi, &decode_mvfaclo, &decode_mvfacmi, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
};
|
||||
unsigned int val = (((insn >> 0) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 112) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_nop, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 113) : /* fall through */
|
||||
CASE (0, 114) : /* fall through */
|
||||
CASE (0, 115) : /* fall through */
|
||||
CASE (0, 116) : /* fall through */
|
||||
CASE (0, 117) : /* fall through */
|
||||
CASE (0, 118) : /* fall through */
|
||||
CASE (0, 119) : /* fall through */
|
||||
CASE (0, 120) : /* fall through */
|
||||
CASE (0, 121) : /* fall through */
|
||||
CASE (0, 122) : /* fall through */
|
||||
CASE (0, 123) : /* fall through */
|
||||
CASE (0, 124) : /* fall through */
|
||||
CASE (0, 125) : /* fall through */
|
||||
CASE (0, 126) : /* fall through */
|
||||
CASE (0, 127) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 240) : /* fall through */
|
||||
CASE (0, 241) : /* fall through */
|
||||
CASE (0, 242) : /* fall through */
|
||||
CASE (0, 243) : /* fall through */
|
||||
CASE (0, 244) : /* fall through */
|
||||
CASE (0, 245) : /* fall through */
|
||||
CASE (0, 246) : /* fall through */
|
||||
CASE (0, 247) : /* fall through */
|
||||
CASE (0, 248) : /* fall through */
|
||||
CASE (0, 249) : /* fall through */
|
||||
CASE (0, 250) : /* fall through */
|
||||
CASE (0, 251) : /* fall through */
|
||||
CASE (0, 252) : /* fall through */
|
||||
CASE (0, 253) : /* fall through */
|
||||
CASE (0, 254) : /* fall through */
|
||||
CASE (0, 255) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
DEFAULT (0) : return insns[val];
|
||||
}
|
||||
ENDSWITCH (0)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,601 @@
|
|||
/* Simulator instruction decoder for m32r.
|
||||
|
||||
This file is machine generated with CGEN.
|
||||
|
||||
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
#define WANT_CPU
|
||||
#define WANT_CPU_M32RX
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "sim-xcat.h"
|
||||
#include "cpu-sim.h"
|
||||
#include "cpu-opc.h"
|
||||
|
||||
/* FIXME: wip, may eventually only want one form so this would then go
|
||||
away. However, in the mean time, having both keeps a stable version
|
||||
around while the cache version is being developed.
|
||||
It may still be useful to allow two versions to exist though. */
|
||||
#if WITH_SCACHE
|
||||
#define EX(fn) XCONCAT3 (m32rx,_ex_,fn)
|
||||
#else
|
||||
#define EX(fn) 0
|
||||
#endif
|
||||
|
||||
#if WITH_SEM_SWITCH_FULL
|
||||
#define FULL(fn) 0
|
||||
#else
|
||||
#define FULL(fn) XCONCAT3 (m32rx,_sem_,fn)
|
||||
#endif
|
||||
|
||||
#if WITH_SEM_SWITCH_FAST
|
||||
#define FAST(fn) 0
|
||||
#else
|
||||
#if WITH_SCACHE
|
||||
#define FAST(fn) XCONCAT3 (m32rx,_semc_,fn)
|
||||
#else
|
||||
#define FAST(fn) 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*#define DECODE M32RX_DECODE*/
|
||||
|
||||
/* The decode_illegal case is currently non-static and the generator doesn't
|
||||
prepend m32rx_, so simplify things by handling it here. */
|
||||
#define decode_illegal m32rx_decode_illegal
|
||||
|
||||
static DECODE decode_add = { M32R_INSN_ADD, & m32r_cgen_insn_table_entries[M32R_INSN_ADD], EX (fmt_0_add), FULL (add), FAST (add) };
|
||||
static DECODE decode_add3 = { M32R_INSN_ADD3, & m32r_cgen_insn_table_entries[M32R_INSN_ADD3], EX (fmt_1_add3), FULL (add3), FAST (add3) };
|
||||
static DECODE decode_and = { M32R_INSN_AND, & m32r_cgen_insn_table_entries[M32R_INSN_AND], EX (fmt_0_add), FULL (and), FAST (and) };
|
||||
static DECODE decode_and3 = { M32R_INSN_AND3, & m32r_cgen_insn_table_entries[M32R_INSN_AND3], EX (fmt_2_and3), FULL (and3), FAST (and3) };
|
||||
static DECODE decode_or = { M32R_INSN_OR, & m32r_cgen_insn_table_entries[M32R_INSN_OR], EX (fmt_0_add), FULL (or), FAST (or) };
|
||||
static DECODE decode_or3 = { M32R_INSN_OR3, & m32r_cgen_insn_table_entries[M32R_INSN_OR3], EX (fmt_3_or3), FULL (or3), FAST (or3) };
|
||||
static DECODE decode_xor = { M32R_INSN_XOR, & m32r_cgen_insn_table_entries[M32R_INSN_XOR], EX (fmt_0_add), FULL (xor), FAST (xor) };
|
||||
static DECODE decode_xor3 = { M32R_INSN_XOR3, & m32r_cgen_insn_table_entries[M32R_INSN_XOR3], EX (fmt_2_and3), FULL (xor3), FAST (xor3) };
|
||||
static DECODE decode_addi = { M32R_INSN_ADDI, & m32r_cgen_insn_table_entries[M32R_INSN_ADDI], EX (fmt_4_addi), FULL (addi), FAST (addi) };
|
||||
static DECODE decode_addv = { M32R_INSN_ADDV, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV], EX (fmt_0_add), FULL (addv), FAST (addv) };
|
||||
static DECODE decode_addv3 = { M32R_INSN_ADDV3, & m32r_cgen_insn_table_entries[M32R_INSN_ADDV3], EX (fmt_5_addv3), FULL (addv3), FAST (addv3) };
|
||||
static DECODE decode_addx = { M32R_INSN_ADDX, & m32r_cgen_insn_table_entries[M32R_INSN_ADDX], EX (fmt_6_addx), FULL (addx), FAST (addx) };
|
||||
static DECODE decode_bc8 = { M32R_INSN_BC8, & m32r_cgen_insn_table_entries[M32R_INSN_BC8], EX (fmt_7_bc8), FULL (bc8), FAST (bc8) };
|
||||
static DECODE decode_bc24 = { M32R_INSN_BC24, & m32r_cgen_insn_table_entries[M32R_INSN_BC24], EX (fmt_8_bc24), FULL (bc24), FAST (bc24) };
|
||||
static DECODE decode_beq = { M32R_INSN_BEQ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQ], EX (fmt_9_beq), FULL (beq), FAST (beq) };
|
||||
static DECODE decode_beqz = { M32R_INSN_BEQZ, & m32r_cgen_insn_table_entries[M32R_INSN_BEQZ], EX (fmt_10_beqz), FULL (beqz), FAST (beqz) };
|
||||
static DECODE decode_bgez = { M32R_INSN_BGEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGEZ], EX (fmt_10_beqz), FULL (bgez), FAST (bgez) };
|
||||
static DECODE decode_bgtz = { M32R_INSN_BGTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BGTZ], EX (fmt_10_beqz), FULL (bgtz), FAST (bgtz) };
|
||||
static DECODE decode_blez = { M32R_INSN_BLEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLEZ], EX (fmt_10_beqz), FULL (blez), FAST (blez) };
|
||||
static DECODE decode_bltz = { M32R_INSN_BLTZ, & m32r_cgen_insn_table_entries[M32R_INSN_BLTZ], EX (fmt_10_beqz), FULL (bltz), FAST (bltz) };
|
||||
static DECODE decode_bnez = { M32R_INSN_BNEZ, & m32r_cgen_insn_table_entries[M32R_INSN_BNEZ], EX (fmt_10_beqz), FULL (bnez), FAST (bnez) };
|
||||
static DECODE decode_bl8 = { M32R_INSN_BL8, & m32r_cgen_insn_table_entries[M32R_INSN_BL8], EX (fmt_11_bl8), FULL (bl8), FAST (bl8) };
|
||||
static DECODE decode_bl24 = { M32R_INSN_BL24, & m32r_cgen_insn_table_entries[M32R_INSN_BL24], EX (fmt_12_bl24), FULL (bl24), FAST (bl24) };
|
||||
static DECODE decode_bcl8 = { M32R_INSN_BCL8, & m32r_cgen_insn_table_entries[M32R_INSN_BCL8], EX (fmt_13_bcl8), FULL (bcl8), FAST (bcl8) };
|
||||
static DECODE decode_bcl24 = { M32R_INSN_BCL24, & m32r_cgen_insn_table_entries[M32R_INSN_BCL24], EX (fmt_14_bcl24), FULL (bcl24), FAST (bcl24) };
|
||||
static DECODE decode_bnc8 = { M32R_INSN_BNC8, & m32r_cgen_insn_table_entries[M32R_INSN_BNC8], EX (fmt_7_bc8), FULL (bnc8), FAST (bnc8) };
|
||||
static DECODE decode_bnc24 = { M32R_INSN_BNC24, & m32r_cgen_insn_table_entries[M32R_INSN_BNC24], EX (fmt_8_bc24), FULL (bnc24), FAST (bnc24) };
|
||||
static DECODE decode_bne = { M32R_INSN_BNE, & m32r_cgen_insn_table_entries[M32R_INSN_BNE], EX (fmt_9_beq), FULL (bne), FAST (bne) };
|
||||
static DECODE decode_bra8 = { M32R_INSN_BRA8, & m32r_cgen_insn_table_entries[M32R_INSN_BRA8], EX (fmt_15_bra8), FULL (bra8), FAST (bra8) };
|
||||
static DECODE decode_bra24 = { M32R_INSN_BRA24, & m32r_cgen_insn_table_entries[M32R_INSN_BRA24], EX (fmt_16_bra24), FULL (bra24), FAST (bra24) };
|
||||
static DECODE decode_bncl8 = { M32R_INSN_BNCL8, & m32r_cgen_insn_table_entries[M32R_INSN_BNCL8], EX (fmt_13_bcl8), FULL (bncl8), FAST (bncl8) };
|
||||
static DECODE decode_bncl24 = { M32R_INSN_BNCL24, & m32r_cgen_insn_table_entries[M32R_INSN_BNCL24], EX (fmt_14_bcl24), FULL (bncl24), FAST (bncl24) };
|
||||
static DECODE decode_cmp = { M32R_INSN_CMP, & m32r_cgen_insn_table_entries[M32R_INSN_CMP], EX (fmt_17_cmp), FULL (cmp), FAST (cmp) };
|
||||
static DECODE decode_cmpi = { M32R_INSN_CMPI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPI], EX (fmt_18_cmpi), FULL (cmpi), FAST (cmpi) };
|
||||
static DECODE decode_cmpu = { M32R_INSN_CMPU, & m32r_cgen_insn_table_entries[M32R_INSN_CMPU], EX (fmt_17_cmp), FULL (cmpu), FAST (cmpu) };
|
||||
static DECODE decode_cmpui = { M32R_INSN_CMPUI, & m32r_cgen_insn_table_entries[M32R_INSN_CMPUI], EX (fmt_19_cmpui), FULL (cmpui), FAST (cmpui) };
|
||||
static DECODE decode_cmpeq = { M32R_INSN_CMPEQ, & m32r_cgen_insn_table_entries[M32R_INSN_CMPEQ], EX (fmt_17_cmp), FULL (cmpeq), FAST (cmpeq) };
|
||||
static DECODE decode_cmpz = { M32R_INSN_CMPZ, & m32r_cgen_insn_table_entries[M32R_INSN_CMPZ], EX (fmt_20_cmpz), FULL (cmpz), FAST (cmpz) };
|
||||
static DECODE decode_div = { M32R_INSN_DIV, & m32r_cgen_insn_table_entries[M32R_INSN_DIV], EX (fmt_21_div), FULL (div), FAST (div) };
|
||||
static DECODE decode_divu = { M32R_INSN_DIVU, & m32r_cgen_insn_table_entries[M32R_INSN_DIVU], EX (fmt_21_div), FULL (divu), FAST (divu) };
|
||||
static DECODE decode_rem = { M32R_INSN_REM, & m32r_cgen_insn_table_entries[M32R_INSN_REM], EX (fmt_21_div), FULL (rem), FAST (rem) };
|
||||
static DECODE decode_remu = { M32R_INSN_REMU, & m32r_cgen_insn_table_entries[M32R_INSN_REMU], EX (fmt_21_div), FULL (remu), FAST (remu) };
|
||||
static DECODE decode_jc = { M32R_INSN_JC, & m32r_cgen_insn_table_entries[M32R_INSN_JC], EX (fmt_22_jc), FULL (jc), FAST (jc) };
|
||||
static DECODE decode_jnc = { M32R_INSN_JNC, & m32r_cgen_insn_table_entries[M32R_INSN_JNC], EX (fmt_22_jc), FULL (jnc), FAST (jnc) };
|
||||
static DECODE decode_jl = { M32R_INSN_JL, & m32r_cgen_insn_table_entries[M32R_INSN_JL], EX (fmt_23_jl), FULL (jl), FAST (jl) };
|
||||
static DECODE decode_jmp = { M32R_INSN_JMP, & m32r_cgen_insn_table_entries[M32R_INSN_JMP], EX (fmt_24_jmp), FULL (jmp), FAST (jmp) };
|
||||
static DECODE decode_ld = { M32R_INSN_LD, & m32r_cgen_insn_table_entries[M32R_INSN_LD], EX (fmt_25_ld), FULL (ld), FAST (ld) };
|
||||
static DECODE decode_ld_d = { M32R_INSN_LD_D, & m32r_cgen_insn_table_entries[M32R_INSN_LD_D], EX (fmt_26_ld_d), FULL (ld_d), FAST (ld_d) };
|
||||
static DECODE decode_ldb = { M32R_INSN_LDB, & m32r_cgen_insn_table_entries[M32R_INSN_LDB], EX (fmt_27_ldb), FULL (ldb), FAST (ldb) };
|
||||
static DECODE decode_ldb_d = { M32R_INSN_LDB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDB_D], EX (fmt_28_ldb_d), FULL (ldb_d), FAST (ldb_d) };
|
||||
static DECODE decode_ldh = { M32R_INSN_LDH, & m32r_cgen_insn_table_entries[M32R_INSN_LDH], EX (fmt_29_ldh), FULL (ldh), FAST (ldh) };
|
||||
static DECODE decode_ldh_d = { M32R_INSN_LDH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDH_D], EX (fmt_30_ldh_d), FULL (ldh_d), FAST (ldh_d) };
|
||||
static DECODE decode_ldub = { M32R_INSN_LDUB, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB], EX (fmt_27_ldb), FULL (ldub), FAST (ldub) };
|
||||
static DECODE decode_ldub_d = { M32R_INSN_LDUB_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUB_D], EX (fmt_28_ldb_d), FULL (ldub_d), FAST (ldub_d) };
|
||||
static DECODE decode_lduh = { M32R_INSN_LDUH, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH], EX (fmt_29_ldh), FULL (lduh), FAST (lduh) };
|
||||
static DECODE decode_lduh_d = { M32R_INSN_LDUH_D, & m32r_cgen_insn_table_entries[M32R_INSN_LDUH_D], EX (fmt_30_ldh_d), FULL (lduh_d), FAST (lduh_d) };
|
||||
static DECODE decode_ld_plus = { M32R_INSN_LD_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_LD_PLUS], EX (fmt_25_ld), FULL (ld_plus), FAST (ld_plus) };
|
||||
static DECODE decode_ld24 = { M32R_INSN_LD24, & m32r_cgen_insn_table_entries[M32R_INSN_LD24], EX (fmt_31_ld24), FULL (ld24), FAST (ld24) };
|
||||
static DECODE decode_ldi8 = { M32R_INSN_LDI8, & m32r_cgen_insn_table_entries[M32R_INSN_LDI8], EX (fmt_32_ldi8), FULL (ldi8), FAST (ldi8) };
|
||||
static DECODE decode_ldi16 = { M32R_INSN_LDI16, & m32r_cgen_insn_table_entries[M32R_INSN_LDI16], EX (fmt_33_ldi16), FULL (ldi16), FAST (ldi16) };
|
||||
static DECODE decode_lock = { M32R_INSN_LOCK, & m32r_cgen_insn_table_entries[M32R_INSN_LOCK], EX (fmt_0_add), FULL (lock), FAST (lock) };
|
||||
static DECODE decode_machi_a = { M32R_INSN_MACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MACHI_A], EX (fmt_34_machi_a), FULL (machi_a), FAST (machi_a) };
|
||||
static DECODE decode_maclo_a = { M32R_INSN_MACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MACLO_A], EX (fmt_34_machi_a), FULL (maclo_a), FAST (maclo_a) };
|
||||
static DECODE decode_mul = { M32R_INSN_MUL, & m32r_cgen_insn_table_entries[M32R_INSN_MUL], EX (fmt_0_add), FULL (mul), FAST (mul) };
|
||||
static DECODE decode_mulhi_a = { M32R_INSN_MULHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MULHI_A], EX (fmt_35_mulhi_a), FULL (mulhi_a), FAST (mulhi_a) };
|
||||
static DECODE decode_mullo_a = { M32R_INSN_MULLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MULLO_A], EX (fmt_35_mulhi_a), FULL (mullo_a), FAST (mullo_a) };
|
||||
static DECODE decode_mv = { M32R_INSN_MV, & m32r_cgen_insn_table_entries[M32R_INSN_MV], EX (fmt_36_mv), FULL (mv), FAST (mv) };
|
||||
static DECODE decode_mvfachi_a = { M32R_INSN_MVFACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACHI_A], EX (fmt_37_mvfachi_a), FULL (mvfachi_a), FAST (mvfachi_a) };
|
||||
static DECODE decode_mvfaclo_a = { M32R_INSN_MVFACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACLO_A], EX (fmt_37_mvfachi_a), FULL (mvfaclo_a), FAST (mvfaclo_a) };
|
||||
static DECODE decode_mvfacmi_a = { M32R_INSN_MVFACMI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVFACMI_A], EX (fmt_37_mvfachi_a), FULL (mvfacmi_a), FAST (mvfacmi_a) };
|
||||
static DECODE decode_mvfc = { M32R_INSN_MVFC, & m32r_cgen_insn_table_entries[M32R_INSN_MVFC], EX (fmt_38_mvfc), FULL (mvfc), FAST (mvfc) };
|
||||
static DECODE decode_mvtachi_a = { M32R_INSN_MVTACHI_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACHI_A], EX (fmt_39_mvtachi_a), FULL (mvtachi_a), FAST (mvtachi_a) };
|
||||
static DECODE decode_mvtaclo_a = { M32R_INSN_MVTACLO_A, & m32r_cgen_insn_table_entries[M32R_INSN_MVTACLO_A], EX (fmt_39_mvtachi_a), FULL (mvtaclo_a), FAST (mvtaclo_a) };
|
||||
static DECODE decode_mvtc = { M32R_INSN_MVTC, & m32r_cgen_insn_table_entries[M32R_INSN_MVTC], EX (fmt_40_mvtc), FULL (mvtc), FAST (mvtc) };
|
||||
static DECODE decode_neg = { M32R_INSN_NEG, & m32r_cgen_insn_table_entries[M32R_INSN_NEG], EX (fmt_36_mv), FULL (neg), FAST (neg) };
|
||||
static DECODE decode_nop = { M32R_INSN_NOP, & m32r_cgen_insn_table_entries[M32R_INSN_NOP], EX (fmt_41_nop), FULL (nop), FAST (nop) };
|
||||
static DECODE decode_not = { M32R_INSN_NOT, & m32r_cgen_insn_table_entries[M32R_INSN_NOT], EX (fmt_36_mv), FULL (not), FAST (not) };
|
||||
static DECODE decode_rac_a = { M32R_INSN_RAC_A, & m32r_cgen_insn_table_entries[M32R_INSN_RAC_A], EX (fmt_42_rac_a), FULL (rac_a), FAST (rac_a) };
|
||||
static DECODE decode_rach_a = { M32R_INSN_RACH_A, & m32r_cgen_insn_table_entries[M32R_INSN_RACH_A], EX (fmt_42_rac_a), FULL (rach_a), FAST (rach_a) };
|
||||
static DECODE decode_rte = { M32R_INSN_RTE, & m32r_cgen_insn_table_entries[M32R_INSN_RTE], EX (fmt_43_rte), FULL (rte), FAST (rte) };
|
||||
static DECODE decode_seth = { M32R_INSN_SETH, & m32r_cgen_insn_table_entries[M32R_INSN_SETH], EX (fmt_44_seth), FULL (seth), FAST (seth) };
|
||||
static DECODE decode_sll = { M32R_INSN_SLL, & m32r_cgen_insn_table_entries[M32R_INSN_SLL], EX (fmt_0_add), FULL (sll), FAST (sll) };
|
||||
static DECODE decode_sll3 = { M32R_INSN_SLL3, & m32r_cgen_insn_table_entries[M32R_INSN_SLL3], EX (fmt_5_addv3), FULL (sll3), FAST (sll3) };
|
||||
static DECODE decode_slli = { M32R_INSN_SLLI, & m32r_cgen_insn_table_entries[M32R_INSN_SLLI], EX (fmt_45_slli), FULL (slli), FAST (slli) };
|
||||
static DECODE decode_sra = { M32R_INSN_SRA, & m32r_cgen_insn_table_entries[M32R_INSN_SRA], EX (fmt_0_add), FULL (sra), FAST (sra) };
|
||||
static DECODE decode_sra3 = { M32R_INSN_SRA3, & m32r_cgen_insn_table_entries[M32R_INSN_SRA3], EX (fmt_5_addv3), FULL (sra3), FAST (sra3) };
|
||||
static DECODE decode_srai = { M32R_INSN_SRAI, & m32r_cgen_insn_table_entries[M32R_INSN_SRAI], EX (fmt_45_slli), FULL (srai), FAST (srai) };
|
||||
static DECODE decode_srl = { M32R_INSN_SRL, & m32r_cgen_insn_table_entries[M32R_INSN_SRL], EX (fmt_0_add), FULL (srl), FAST (srl) };
|
||||
static DECODE decode_srl3 = { M32R_INSN_SRL3, & m32r_cgen_insn_table_entries[M32R_INSN_SRL3], EX (fmt_5_addv3), FULL (srl3), FAST (srl3) };
|
||||
static DECODE decode_srli = { M32R_INSN_SRLI, & m32r_cgen_insn_table_entries[M32R_INSN_SRLI], EX (fmt_45_slli), FULL (srli), FAST (srli) };
|
||||
static DECODE decode_st = { M32R_INSN_ST, & m32r_cgen_insn_table_entries[M32R_INSN_ST], EX (fmt_17_cmp), FULL (st), FAST (st) };
|
||||
static DECODE decode_st_d = { M32R_INSN_ST_D, & m32r_cgen_insn_table_entries[M32R_INSN_ST_D], EX (fmt_46_st_d), FULL (st_d), FAST (st_d) };
|
||||
static DECODE decode_stb = { M32R_INSN_STB, & m32r_cgen_insn_table_entries[M32R_INSN_STB], EX (fmt_17_cmp), FULL (stb), FAST (stb) };
|
||||
static DECODE decode_stb_d = { M32R_INSN_STB_D, & m32r_cgen_insn_table_entries[M32R_INSN_STB_D], EX (fmt_46_st_d), FULL (stb_d), FAST (stb_d) };
|
||||
static DECODE decode_sth = { M32R_INSN_STH, & m32r_cgen_insn_table_entries[M32R_INSN_STH], EX (fmt_17_cmp), FULL (sth), FAST (sth) };
|
||||
static DECODE decode_sth_d = { M32R_INSN_STH_D, & m32r_cgen_insn_table_entries[M32R_INSN_STH_D], EX (fmt_46_st_d), FULL (sth_d), FAST (sth_d) };
|
||||
static DECODE decode_st_plus = { M32R_INSN_ST_PLUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_PLUS], EX (fmt_17_cmp), FULL (st_plus), FAST (st_plus) };
|
||||
static DECODE decode_st_minus = { M32R_INSN_ST_MINUS, & m32r_cgen_insn_table_entries[M32R_INSN_ST_MINUS], EX (fmt_17_cmp), FULL (st_minus), FAST (st_minus) };
|
||||
static DECODE decode_sub = { M32R_INSN_SUB, & m32r_cgen_insn_table_entries[M32R_INSN_SUB], EX (fmt_0_add), FULL (sub), FAST (sub) };
|
||||
static DECODE decode_subv = { M32R_INSN_SUBV, & m32r_cgen_insn_table_entries[M32R_INSN_SUBV], EX (fmt_0_add), FULL (subv), FAST (subv) };
|
||||
static DECODE decode_subx = { M32R_INSN_SUBX, & m32r_cgen_insn_table_entries[M32R_INSN_SUBX], EX (fmt_6_addx), FULL (subx), FAST (subx) };
|
||||
static DECODE decode_trap = { M32R_INSN_TRAP, & m32r_cgen_insn_table_entries[M32R_INSN_TRAP], EX (fmt_47_trap), FULL (trap), FAST (trap) };
|
||||
static DECODE decode_unlock = { M32R_INSN_UNLOCK, & m32r_cgen_insn_table_entries[M32R_INSN_UNLOCK], EX (fmt_17_cmp), FULL (unlock), FAST (unlock) };
|
||||
static DECODE decode_satb = { M32R_INSN_SATB, & m32r_cgen_insn_table_entries[M32R_INSN_SATB], EX (fmt_48_satb), FULL (satb), FAST (satb) };
|
||||
static DECODE decode_sath = { M32R_INSN_SATH, & m32r_cgen_insn_table_entries[M32R_INSN_SATH], EX (fmt_48_satb), FULL (sath), FAST (sath) };
|
||||
static DECODE decode_sat = { M32R_INSN_SAT, & m32r_cgen_insn_table_entries[M32R_INSN_SAT], EX (fmt_49_sat), FULL (sat), FAST (sat) };
|
||||
static DECODE decode_pcmpbz = { M32R_INSN_PCMPBZ, & m32r_cgen_insn_table_entries[M32R_INSN_PCMPBZ], EX (fmt_20_cmpz), FULL (pcmpbz), FAST (pcmpbz) };
|
||||
static DECODE decode_sadd = { M32R_INSN_SADD, & m32r_cgen_insn_table_entries[M32R_INSN_SADD], EX (fmt_50_sadd), FULL (sadd), FAST (sadd) };
|
||||
static DECODE decode_macwu1 = { M32R_INSN_MACWU1, & m32r_cgen_insn_table_entries[M32R_INSN_MACWU1], EX (fmt_51_macwu1), FULL (macwu1), FAST (macwu1) };
|
||||
static DECODE decode_msblo = { M32R_INSN_MSBLO, & m32r_cgen_insn_table_entries[M32R_INSN_MSBLO], EX (fmt_52_msblo), FULL (msblo), FAST (msblo) };
|
||||
static DECODE decode_mulwu1 = { M32R_INSN_MULWU1, & m32r_cgen_insn_table_entries[M32R_INSN_MULWU1], EX (fmt_17_cmp), FULL (mulwu1), FAST (mulwu1) };
|
||||
static DECODE decode_machl1 = { M32R_INSN_MACHL1, & m32r_cgen_insn_table_entries[M32R_INSN_MACHL1], EX (fmt_51_macwu1), FULL (machl1), FAST (machl1) };
|
||||
static DECODE decode_sc = { M32R_INSN_SC, & m32r_cgen_insn_table_entries[M32R_INSN_SC], EX (fmt_53_sc), FULL (sc), FAST (sc) };
|
||||
static DECODE decode_snc = { M32R_INSN_SNC, & m32r_cgen_insn_table_entries[M32R_INSN_SNC], EX (fmt_53_sc), FULL (snc), FAST (snc) };
|
||||
DECODE m32rx_decode_illegal = {
|
||||
M32R_INSN_ILLEGAL, & m32r_cgen_insn_table_entries[0],
|
||||
EX (illegal), FULL (illegal),
|
||||
FAST (illegal)
|
||||
};
|
||||
|
||||
/* The order must match that of `labels' in sem-switch.c. */
|
||||
|
||||
DECODE *m32rx_decode_vars[] = {
|
||||
& m32rx_decode_illegal,
|
||||
& decode_add,
|
||||
& decode_add3,
|
||||
& decode_and,
|
||||
& decode_and3,
|
||||
& decode_or,
|
||||
& decode_or3,
|
||||
& decode_xor,
|
||||
& decode_xor3,
|
||||
& decode_addi,
|
||||
& decode_addv,
|
||||
& decode_addv3,
|
||||
& decode_addx,
|
||||
& decode_bc8,
|
||||
& decode_bc24,
|
||||
& decode_beq,
|
||||
& decode_beqz,
|
||||
& decode_bgez,
|
||||
& decode_bgtz,
|
||||
& decode_blez,
|
||||
& decode_bltz,
|
||||
& decode_bnez,
|
||||
& decode_bl8,
|
||||
& decode_bl24,
|
||||
& decode_bcl8,
|
||||
& decode_bcl24,
|
||||
& decode_bnc8,
|
||||
& decode_bnc24,
|
||||
& decode_bne,
|
||||
& decode_bra8,
|
||||
& decode_bra24,
|
||||
& decode_bncl8,
|
||||
& decode_bncl24,
|
||||
& decode_cmp,
|
||||
& decode_cmpi,
|
||||
& decode_cmpu,
|
||||
& decode_cmpui,
|
||||
& decode_cmpeq,
|
||||
& decode_cmpz,
|
||||
& decode_div,
|
||||
& decode_divu,
|
||||
& decode_rem,
|
||||
& decode_remu,
|
||||
& decode_jc,
|
||||
& decode_jnc,
|
||||
& decode_jl,
|
||||
& decode_jmp,
|
||||
& decode_ld,
|
||||
& decode_ld_d,
|
||||
& decode_ldb,
|
||||
& decode_ldb_d,
|
||||
& decode_ldh,
|
||||
& decode_ldh_d,
|
||||
& decode_ldub,
|
||||
& decode_ldub_d,
|
||||
& decode_lduh,
|
||||
& decode_lduh_d,
|
||||
& decode_ld_plus,
|
||||
& decode_ld24,
|
||||
& decode_ldi8,
|
||||
& decode_ldi16,
|
||||
& decode_lock,
|
||||
& decode_machi_a,
|
||||
& decode_maclo_a,
|
||||
& decode_mul,
|
||||
& decode_mulhi_a,
|
||||
& decode_mullo_a,
|
||||
& decode_mv,
|
||||
& decode_mvfachi_a,
|
||||
& decode_mvfaclo_a,
|
||||
& decode_mvfacmi_a,
|
||||
& decode_mvfc,
|
||||
& decode_mvtachi_a,
|
||||
& decode_mvtaclo_a,
|
||||
& decode_mvtc,
|
||||
& decode_neg,
|
||||
& decode_nop,
|
||||
& decode_not,
|
||||
& decode_rac_a,
|
||||
& decode_rach_a,
|
||||
& decode_rte,
|
||||
& decode_seth,
|
||||
& decode_sll,
|
||||
& decode_sll3,
|
||||
& decode_slli,
|
||||
& decode_sra,
|
||||
& decode_sra3,
|
||||
& decode_srai,
|
||||
& decode_srl,
|
||||
& decode_srl3,
|
||||
& decode_srli,
|
||||
& decode_st,
|
||||
& decode_st_d,
|
||||
& decode_stb,
|
||||
& decode_stb_d,
|
||||
& decode_sth,
|
||||
& decode_sth_d,
|
||||
& decode_st_plus,
|
||||
& decode_st_minus,
|
||||
& decode_sub,
|
||||
& decode_subv,
|
||||
& decode_subx,
|
||||
& decode_trap,
|
||||
& decode_unlock,
|
||||
& decode_satb,
|
||||
& decode_sath,
|
||||
& decode_sat,
|
||||
& decode_pcmpbz,
|
||||
& decode_sadd,
|
||||
& decode_macwu1,
|
||||
& decode_msblo,
|
||||
& decode_mulwu1,
|
||||
& decode_machl1,
|
||||
& decode_sc,
|
||||
& decode_snc,
|
||||
0
|
||||
};
|
||||
|
||||
/* The decoder needs a slightly different computed goto switch control. */
|
||||
#ifdef __GNUC__
|
||||
#define DECODE_SWITCH(N, X) goto *labels_##N[X];
|
||||
#else
|
||||
#define DECODE_SWITCH(N, X) switch (X)
|
||||
#endif
|
||||
|
||||
/* Given an instruction, return a pointer to its DECODE entry. */
|
||||
|
||||
DECODE *
|
||||
m32rx_decode (current_cpu, pc, insn)
|
||||
SIM_CPU *current_cpu;
|
||||
PCADDR pc;
|
||||
insn_t insn;
|
||||
{
|
||||
{
|
||||
#ifdef __GNUC__
|
||||
static void *labels_0[256] = {
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && case_0_7,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& case_0_28, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && case_0_87,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && case_0_95,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& case_0_112, && case_0_113, && case_0_114, && case_0_115,
|
||||
&& case_0_116, && case_0_117, && case_0_118, && case_0_119,
|
||||
&& case_0_120, && case_0_121, && case_0_122, && case_0_123,
|
||||
&& case_0_124, && case_0_125, && case_0_126, && case_0_127,
|
||||
&& case_0_128, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& default_0, && default_0, && default_0, && default_0,
|
||||
&& case_0_240, && case_0_241, && case_0_242, && case_0_243,
|
||||
&& case_0_244, && case_0_245, && case_0_246, && case_0_247,
|
||||
&& case_0_248, && case_0_249, && case_0_250, && case_0_251,
|
||||
&& case_0_252, && case_0_253, && case_0_254, && case_0_255,
|
||||
};
|
||||
#endif
|
||||
static DECODE *insns[256] = {
|
||||
&decode_subv, &decode_subx, &decode_sub, &decode_neg,
|
||||
&decode_cmp, &decode_cmpu, &decode_cmpeq, 0,
|
||||
&decode_addv, &decode_addx, &decode_add, &decode_not,
|
||||
&decode_and, &decode_xor, &decode_or, &decode_illegal,
|
||||
&decode_srl, &decode_illegal, &decode_sra, &decode_illegal,
|
||||
&decode_sll, &decode_illegal, &decode_mul, &decode_illegal,
|
||||
&decode_mv, &decode_mvfc, &decode_mvtc, &decode_illegal,
|
||||
0, &decode_rte, &decode_illegal, &decode_trap,
|
||||
&decode_stb, &decode_illegal, &decode_sth, &decode_illegal,
|
||||
&decode_st, &decode_unlock, &decode_st_plus, &decode_st_minus,
|
||||
&decode_ldb, &decode_ldub, &decode_ldh, &decode_lduh,
|
||||
&decode_ld, &decode_lock, &decode_ld_plus, &decode_illegal,
|
||||
&decode_mulhi_a, &decode_mullo_a, &decode_illegal, &decode_illegal,
|
||||
&decode_machi_a, &decode_maclo_a, &decode_illegal, &decode_illegal,
|
||||
&decode_mulhi_a, &decode_mullo_a, &decode_illegal, &decode_illegal,
|
||||
&decode_machi_a, &decode_maclo_a, &decode_illegal, &decode_illegal,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_addi, &decode_addi, &decode_addi, &decode_addi,
|
||||
&decode_srli, &decode_srli, &decode_srai, &decode_srai,
|
||||
&decode_slli, &decode_slli, &decode_illegal, 0,
|
||||
&decode_rach_a, &decode_rac_a, &decode_mulwu1, &decode_macwu1,
|
||||
&decode_machl1, &decode_msblo, &decode_sadd, 0,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
&decode_ldi8, &decode_ldi8, &decode_ldi8, &decode_ldi8,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_cmpi, &decode_cmpui, &decode_illegal, &decode_illegal,
|
||||
&decode_addv3, &decode_illegal, &decode_add3, &decode_illegal,
|
||||
&decode_and3, &decode_xor3, &decode_or3, &decode_illegal,
|
||||
&decode_div, &decode_divu, &decode_rem, &decode_remu,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_srl3, &decode_illegal, &decode_sra3, &decode_illegal,
|
||||
&decode_sll3, &decode_illegal, &decode_illegal, &decode_ldi16,
|
||||
&decode_stb_d, &decode_illegal, &decode_sth_d, &decode_illegal,
|
||||
&decode_st_d, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_ldb_d, &decode_ldub_d, &decode_ldh_d, &decode_lduh_d,
|
||||
&decode_ld_d, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_beq, &decode_bne, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_beqz, &decode_bnez, &decode_bltz, &decode_bgez,
|
||||
&decode_blez, &decode_bgtz, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_seth, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
&decode_ld24, &decode_ld24, &decode_ld24, &decode_ld24,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
};
|
||||
unsigned int val;
|
||||
val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
|
||||
DECODE_SWITCH (0, val)
|
||||
{
|
||||
CASE (0, 7) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_cmpz, &decode_illegal, &decode_illegal, &decode_pcmpbz,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 28) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_jc, &decode_jnc, &decode_jl, &decode_jmp,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 87) :
|
||||
{
|
||||
static DECODE *insns[4] = {
|
||||
&decode_mvtachi_a, &decode_mvtaclo_a, &decode_illegal, &decode_illegal,
|
||||
};
|
||||
unsigned int val = (((insn >> 0) & (3 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 95) :
|
||||
{
|
||||
static DECODE *insns[4] = {
|
||||
&decode_mvfachi_a, &decode_mvfaclo_a, &decode_mvfacmi_a, &decode_illegal,
|
||||
};
|
||||
unsigned int val = (((insn >> 0) & (3 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 112) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_nop, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_sc, &decode_snc, &decode_illegal, &decode_illegal,
|
||||
&decode_bcl8, &decode_bncl8, &decode_illegal, &decode_illegal,
|
||||
&decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 113) : /* fall through */
|
||||
CASE (0, 114) : /* fall through */
|
||||
CASE (0, 115) : /* fall through */
|
||||
CASE (0, 116) : /* fall through */
|
||||
CASE (0, 117) : /* fall through */
|
||||
CASE (0, 118) : /* fall through */
|
||||
CASE (0, 119) : /* fall through */
|
||||
CASE (0, 120) : /* fall through */
|
||||
CASE (0, 121) : /* fall through */
|
||||
CASE (0, 122) : /* fall through */
|
||||
CASE (0, 123) : /* fall through */
|
||||
CASE (0, 124) : /* fall through */
|
||||
CASE (0, 125) : /* fall through */
|
||||
CASE (0, 126) : /* fall through */
|
||||
CASE (0, 127) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_bcl8, &decode_bncl8, &decode_illegal, &decode_illegal,
|
||||
&decode_bc8, &decode_bnc8, &decode_bl8, &decode_bra8,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
CASE (0, 128) :
|
||||
{
|
||||
#ifdef __GNUC__
|
||||
static void *labels_0_128[16] = {
|
||||
&& case_0_128_0, && default_0_128, && default_0_128, && default_0_128,
|
||||
&& default_0_128, && default_0_128, && default_0_128, && default_0_128,
|
||||
&& default_0_128, && default_0_128, && default_0_128, && default_0_128,
|
||||
&& default_0_128, && default_0_128, && default_0_128, && default_0_128,
|
||||
};
|
||||
#endif
|
||||
static DECODE *insns[16] = {
|
||||
0, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
};
|
||||
unsigned int val;
|
||||
/* Must fetch more bits. */
|
||||
insn = GETIMEMUHI (current_cpu, CPU (h_pc) + 2);
|
||||
val = (((insn >> 12) & (15 << 0)));
|
||||
DECODE_SWITCH (0_128, val)
|
||||
{
|
||||
CASE (0_128, 0) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_sat, &decode_satb, &decode_sath, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
DEFAULT (0_128) : return insns[val];
|
||||
}
|
||||
ENDSWITCH (0_128)
|
||||
}
|
||||
CASE (0, 240) : /* fall through */
|
||||
CASE (0, 241) : /* fall through */
|
||||
CASE (0, 242) : /* fall through */
|
||||
CASE (0, 243) : /* fall through */
|
||||
CASE (0, 244) : /* fall through */
|
||||
CASE (0, 245) : /* fall through */
|
||||
CASE (0, 246) : /* fall through */
|
||||
CASE (0, 247) : /* fall through */
|
||||
CASE (0, 248) : /* fall through */
|
||||
CASE (0, 249) : /* fall through */
|
||||
CASE (0, 250) : /* fall through */
|
||||
CASE (0, 251) : /* fall through */
|
||||
CASE (0, 252) : /* fall through */
|
||||
CASE (0, 253) : /* fall through */
|
||||
CASE (0, 254) : /* fall through */
|
||||
CASE (0, 255) :
|
||||
{
|
||||
static DECODE *insns[16] = {
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_illegal, &decode_illegal, &decode_illegal, &decode_illegal,
|
||||
&decode_bcl24, &decode_bncl24, &decode_illegal, &decode_illegal,
|
||||
&decode_bc24, &decode_bnc24, &decode_bl24, &decode_bra24,
|
||||
};
|
||||
unsigned int val = (((insn >> 8) & (15 << 0)));
|
||||
return insns[val];
|
||||
}
|
||||
DEFAULT (0) : return insns[val];
|
||||
}
|
||||
ENDSWITCH (0)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,7 @@
|
|||
/* Simulator instruction extractor for m32r.
|
||||
|
||||
This file is machine generated with CGEN.
|
||||
|
||||
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Simulators.
|
||||
|
|
@ -320,6 +322,14 @@ EX_FN_NAME (m32r,fmt_11_bl8) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGB
|
|||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
/* Record the fields for profiling. */
|
||||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
abuf->h_gr_set = 0 | (1 << 14);
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
|
|
@ -337,6 +347,14 @@ EX_FN_NAME (m32r,fmt_12_bl24) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
|
|||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
/* Record the fields for profiling. */
|
||||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
abuf->h_gr_set = 0 | (1 << 14);
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
|
|
@ -499,6 +517,7 @@ EX_FN_NAME (m32r,fmt_19_jl) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBU
|
|||
if (PROFILE_MODEL_P (current_cpu))
|
||||
{
|
||||
abuf->h_gr_get = 0 | (1 << f_r2);
|
||||
abuf->h_gr_set = 0 | (1 << 14);
|
||||
}
|
||||
#endif
|
||||
#undef FLD
|
||||
|
|
@ -960,17 +979,33 @@ EX_FN_NAME (m32r,fmt_37_rac) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGB
|
|||
}
|
||||
|
||||
void
|
||||
EX_FN_NAME (m32r,fmt_38_seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
EX_FN_NAME (m32r,fmt_38_rte) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_38_seth.f
|
||||
EXTRACT_FMT_38_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
|
||||
#define FLD(f) abuf->fields.fmt_38_rte.f
|
||||
EXTRACT_FMT_38_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_38_SETH_CODE
|
||||
EXTRACT_FMT_38_RTE_CODE
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_38_rte", (char *) 0));
|
||||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
#undef FLD
|
||||
}
|
||||
|
||||
void
|
||||
EX_FN_NAME (m32r,fmt_39_seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_39_seth.f
|
||||
EXTRACT_FMT_39_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
|
||||
|
||||
EXTRACT_FMT_39_SETH_CODE
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_r1) = & CPU (h_gr)[f_r1];
|
||||
FLD (f_hi16) = f_hi16;
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_38_seth", "dr 0x%x", 'x', f_r1, "hi16 0x%x", 'x', f_hi16, (char *) 0));
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_39_seth", "dr 0x%x", 'x', f_r1, "hi16 0x%x", 'x', f_hi16, (char *) 0));
|
||||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
|
|
@ -986,17 +1021,17 @@ EX_FN_NAME (m32r,fmt_38_seth) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
|
|||
}
|
||||
|
||||
void
|
||||
EX_FN_NAME (m32r,fmt_39_slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
EX_FN_NAME (m32r,fmt_40_slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_39_slli.f
|
||||
EXTRACT_FMT_39_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
|
||||
#define FLD(f) abuf->fields.fmt_40_slli.f
|
||||
EXTRACT_FMT_40_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
|
||||
|
||||
EXTRACT_FMT_39_SLLI_CODE
|
||||
EXTRACT_FMT_40_SLLI_CODE
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_r1) = & CPU (h_gr)[f_r1];
|
||||
FLD (f_uimm5) = f_uimm5;
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_39_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_40_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
|
||||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
|
|
@ -1013,18 +1048,18 @@ EX_FN_NAME (m32r,fmt_39_slli) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
|
|||
}
|
||||
|
||||
void
|
||||
EX_FN_NAME (m32r,fmt_40_st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
EX_FN_NAME (m32r,fmt_41_st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_40_st_d.f
|
||||
EXTRACT_FMT_40_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
#define FLD(f) abuf->fields.fmt_41_st_d.f
|
||||
EXTRACT_FMT_41_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_40_ST_D_CODE
|
||||
EXTRACT_FMT_41_ST_D_CODE
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_r1) = & CPU (h_gr)[f_r1];
|
||||
FLD (f_r2) = & CPU (h_gr)[f_r2];
|
||||
FLD (f_simm16) = f_simm16;
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_40_st_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_41_st_d", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, (char *) 0));
|
||||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
|
|
@ -1040,16 +1075,16 @@ EX_FN_NAME (m32r,fmt_40_st_d) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARG
|
|||
}
|
||||
|
||||
void
|
||||
EX_FN_NAME (m32r,fmt_41_trap) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
EX_FN_NAME (m32r,fmt_42_trap) (SIM_CPU *current_cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_41_trap.f
|
||||
EXTRACT_FMT_41_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
|
||||
#define FLD(f) abuf->fields.fmt_42_trap.f
|
||||
EXTRACT_FMT_42_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
|
||||
|
||||
EXTRACT_FMT_41_TRAP_CODE
|
||||
EXTRACT_FMT_42_TRAP_CODE
|
||||
|
||||
/* Record the fields for the semantic handler. */
|
||||
FLD (f_uimm4) = f_uimm4;
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_41_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
|
||||
TRACE_EXTRACT (current_cpu, (current_cpu, pc, "fmt_42_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
|
||||
|
||||
abuf->length = length;
|
||||
abuf->addr = pc;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,112 @@
|
|||
/* m32rx simulator support code
|
||||
Copyright (C) 1997, 1998 Free Software Foundation, Inc.
|
||||
Contributed by Cygnus Support.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#define WANT_CPU
|
||||
#define WANT_CPU_M32RX
|
||||
|
||||
#include "sim-main.h"
|
||||
#include <signal.h>
|
||||
#include "libiberty.h"
|
||||
#include "bfd.h"
|
||||
/* FIXME: need to provide general mechanism for accessing target files
|
||||
these. For now this is a hack to avoid getting the host version. */
|
||||
#include "../../libgloss/m32r/sys/syscall.h"
|
||||
#include "targ-vals.h"
|
||||
|
||||
/* The contents of BUF are in target byte order. */
|
||||
|
||||
void
|
||||
m32rx_fetch_register (sd, rn, buf)
|
||||
SIM_DESC sd;
|
||||
int rn;
|
||||
unsigned char *buf;
|
||||
{
|
||||
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
|
||||
|
||||
if (rn < 16)
|
||||
SETTWI (buf, GET_H_GR (rn));
|
||||
else if (rn < 21)
|
||||
SETTWI (buf, GET_H_CR (rn - 16));
|
||||
else switch (rn) {
|
||||
case PC_REGNUM:
|
||||
SETTWI (buf, GET_H_PC ());
|
||||
break;
|
||||
case ACCL_REGNUM:
|
||||
SETTWI (buf, GETLODI (GET_H_ACCUM ()));
|
||||
break;
|
||||
case ACCH_REGNUM:
|
||||
SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
|
||||
break;
|
||||
#if 0
|
||||
case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond; break;
|
||||
case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm; break;
|
||||
case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm; break;
|
||||
case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie; break;
|
||||
case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie; break;
|
||||
case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry; break; /* rename: bc */
|
||||
case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI)); break; /* duplicate */
|
||||
#endif
|
||||
default: abort ();
|
||||
}
|
||||
}
|
||||
|
||||
/* The contents of BUF are in target byte order. */
|
||||
|
||||
void
|
||||
m32rx_store_register (sd, rn, buf)
|
||||
SIM_DESC sd;
|
||||
int rn;
|
||||
unsigned char *buf;
|
||||
{
|
||||
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
|
||||
|
||||
if (rn < 16)
|
||||
SET_H_GR (rn, GETTWI (buf));
|
||||
else if (rn < 21)
|
||||
SET_H_CR (rn - 16, GETTWI (buf));
|
||||
else switch (rn) {
|
||||
case PC_REGNUM:
|
||||
SET_H_PC (GETTWI (buf));
|
||||
break;
|
||||
case ACCL_REGNUM:
|
||||
SETLODI (CPU (h_accum), GETTWI (buf));
|
||||
break;
|
||||
case ACCH_REGNUM:
|
||||
SETHIDI (CPU (h_accum), GETTWI (buf));
|
||||
break;
|
||||
#if 0
|
||||
case 23: STATE_CPU_CPU (sd, 0)->h_cond = *reg; break;
|
||||
case 24: STATE_CPU_CPU (sd, 0)->h_sm = *reg; break;
|
||||
case 25: STATE_CPU_CPU (sd, 0)->h_bsm = *reg; break;
|
||||
case 26: STATE_CPU_CPU (sd, 0)->h_ie = *reg; break;
|
||||
case 27: STATE_CPU_CPU (sd, 0)->h_bie = *reg; break;
|
||||
case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg; break; /* rename: bc */
|
||||
case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI)); break; /* duplicate */
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* Cover fn to access h-accums. */
|
||||
|
||||
UDI
|
||||
m32rx_h_accums_get (SIM_CPU *current_cpu, UINT accum)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
# Simulator main loop for m32rx. -*- C -*-
|
||||
# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of the GNU Simulators.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License along
|
||||
# with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
# Syntax:
|
||||
# /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
|
||||
|
||||
# ??? After a few more ports are done, revisit.
|
||||
# Will eventually need to machine generate a lot of this.
|
||||
|
||||
case "x$1" in
|
||||
|
||||
xsupport)
|
||||
|
||||
cat <<EOF
|
||||
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xinit)
|
||||
|
||||
cat <<EOF
|
||||
USI insn,insn1,insn2;
|
||||
DECODE *decode,*d1,*d2;
|
||||
int icount,icount2;
|
||||
ARGBUF abufs[MAX_PARALLEL_INSNS];
|
||||
SEM_ARG sem_arg;
|
||||
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xfull-extract-* | xfast-extract-*)
|
||||
|
||||
cat <<EOF
|
||||
{
|
||||
PCADDR pc = CPU (h_pc);
|
||||
|
||||
if ((pc & 3) != 0)
|
||||
{
|
||||
insn1 = GETIMEMUHI (current_cpu, pc);
|
||||
insn1 &= 0x7fff;
|
||||
d1 = m32rx_decode (current_cpu, pc, insn1);
|
||||
icount = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
insn1 = GETIMEMUSI (current_cpu, pc);
|
||||
if ((SI) insn1 < 0)
|
||||
{
|
||||
d1 = m32rx_decode (current_cpu, pc, insn1 >> 16);
|
||||
icount = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (insn & 0x8000)
|
||||
{
|
||||
insn2 = insn1 & 0x7fff;
|
||||
insn1 = insn1 >> 16;
|
||||
d1 = m32rx_decode (current_cpu, pc, insn1);
|
||||
d2 = m32rx_decode (current_cpu, pc, insn2);
|
||||
icount = 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
insn1 = insn1 >> 16;
|
||||
d1 = m32rx_decode (current_cpu, pc, insn1);
|
||||
icount = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
icount2 = icount;
|
||||
insn = insn1;
|
||||
decode = d1;
|
||||
do
|
||||
{
|
||||
#define DEFINE_SWITCH
|
||||
#include "readx.c"
|
||||
|
||||
insn = insn2;
|
||||
decode = d2;
|
||||
}
|
||||
while (--icount2 > 0);
|
||||
}
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xfull-exec-* | xfast-exec-*)
|
||||
|
||||
cat <<EOF
|
||||
{
|
||||
decode = d1;
|
||||
do
|
||||
{
|
||||
PCADDR new_pc;
|
||||
TRACE_INSN_INIT (current_cpu);
|
||||
TRACE_INSN (current_cpu, sc->argbuf.opcode, (const struct argbuf *) &sc->argbuf, sc->argbuf.addr);
|
||||
new_pc = (*decode->semantic) (current_cpu, &sc->argbuf);
|
||||
TRACE_INSN_FINI (current_cpu);
|
||||
PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
|
||||
CPU (h_pc) = new_pc;
|
||||
decode = d2;
|
||||
}
|
||||
while (--icount > 0);
|
||||
}
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
*)
|
||||
echo "Invalid argument to mainloop.in: $1" >&2
|
||||
exit 1
|
||||
;;
|
||||
|
||||
esac
|
||||
342
sim/m32r/readx.c
342
sim/m32r/readx.c
|
|
@ -1,5 +1,7 @@
|
|||
/* Simulator instruction operand reader for m32r.
|
||||
|
||||
This file is machine generated with CGEN.
|
||||
|
||||
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Simulators.
|
||||
|
|
@ -29,7 +31,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
#ifdef DEFINE_LABELS
|
||||
#undef DEFINE_LABELS
|
||||
|
||||
|
||||
/* The labels have the case they have because the enum of insn types
|
||||
is all uppercase and in the non-stdc case the fmt symbol is built
|
||||
into the enum name.
|
||||
|
|
@ -72,28 +73,26 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
&& case_read_READ_FMT_31_LD24,
|
||||
&& case_read_READ_FMT_32_LDI8,
|
||||
&& case_read_READ_FMT_33_LDI16,
|
||||
&& case_read_READ_FMT_34_MACHI,
|
||||
&& case_read_READ_FMT_35_MACHI_A,
|
||||
&& case_read_READ_FMT_36_MULHI_A,
|
||||
&& case_read_READ_FMT_37_MV,
|
||||
&& case_read_READ_FMT_38_MVFACHI,
|
||||
&& case_read_READ_FMT_39_MVFACHI_A,
|
||||
&& case_read_READ_FMT_40_MVFC,
|
||||
&& case_read_READ_FMT_41_MVTACHI,
|
||||
&& case_read_READ_FMT_42_MVTACHI_A,
|
||||
&& case_read_READ_FMT_43_MVTC,
|
||||
&& case_read_READ_FMT_44_NOP,
|
||||
&& case_read_READ_FMT_45_RAC,
|
||||
&& case_read_READ_FMT_46_RAC_A,
|
||||
&& case_read_READ_FMT_47_SETH,
|
||||
&& case_read_READ_FMT_48_SLLI,
|
||||
&& case_read_READ_FMT_49_ST_D,
|
||||
&& case_read_READ_FMT_50_TRAP,
|
||||
&& case_read_READ_FMT_51_SATB,
|
||||
&& case_read_READ_FMT_52_PCMPBZ,
|
||||
&& case_read_READ_FMT_53_SADD,
|
||||
&& case_read_READ_FMT_54_MACWU1,
|
||||
&& case_read_READ_FMT_55_SC,
|
||||
&& case_read_READ_FMT_34_MACHI_A,
|
||||
&& case_read_READ_FMT_35_MULHI_A,
|
||||
&& case_read_READ_FMT_36_MV,
|
||||
&& case_read_READ_FMT_37_MVFACHI_A,
|
||||
&& case_read_READ_FMT_38_MVFC,
|
||||
&& case_read_READ_FMT_39_MVTACHI_A,
|
||||
&& case_read_READ_FMT_40_MVTC,
|
||||
&& case_read_READ_FMT_41_NOP,
|
||||
&& case_read_READ_FMT_42_RAC_A,
|
||||
&& case_read_READ_FMT_43_RTE,
|
||||
&& case_read_READ_FMT_44_SETH,
|
||||
&& case_read_READ_FMT_45_SLLI,
|
||||
&& case_read_READ_FMT_46_ST_D,
|
||||
&& case_read_READ_FMT_47_TRAP,
|
||||
&& case_read_READ_FMT_48_SATB,
|
||||
&& case_read_READ_FMT_49_SAT,
|
||||
&& case_read_READ_FMT_50_SADD,
|
||||
&& case_read_READ_FMT_51_MACWU1,
|
||||
&& case_read_READ_FMT_52_MSBLO,
|
||||
&& case_read_READ_FMT_53_SC,
|
||||
0
|
||||
};
|
||||
extern DECODE *m32rx_decode_vars[];
|
||||
|
|
@ -121,7 +120,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_0_add.f
|
||||
EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_0_ADD_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -135,7 +133,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_1_add3.f
|
||||
EXTRACT_FMT_1_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_1_ADD3_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -149,7 +146,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_2_and3.f
|
||||
EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
|
||||
|
||||
EXTRACT_FMT_2_AND3_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -163,7 +159,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_3_or3.f
|
||||
EXTRACT_FMT_3_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
|
||||
|
||||
EXTRACT_FMT_3_OR3_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -177,7 +172,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_4_addi.f
|
||||
EXTRACT_FMT_4_ADDI_VARS /* f-op1 f-r1 f-simm8 */
|
||||
|
||||
EXTRACT_FMT_4_ADDI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -191,7 +185,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_5_addv3.f
|
||||
EXTRACT_FMT_5_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_5_ADDV3_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -205,7 +198,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_6_addx.f
|
||||
EXTRACT_FMT_6_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_6_ADDX_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -220,7 +212,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_7_bc8.f
|
||||
EXTRACT_FMT_7_BC8_VARS /* f-op1 f-r1 f-disp8 */
|
||||
|
||||
EXTRACT_FMT_7_BC8_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -234,7 +225,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_8_bc24.f
|
||||
EXTRACT_FMT_8_BC24_VARS /* f-op1 f-r1 f-disp24 */
|
||||
|
||||
EXTRACT_FMT_8_BC24_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -248,7 +238,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_9_beq.f
|
||||
EXTRACT_FMT_9_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
|
||||
|
||||
EXTRACT_FMT_9_BEQ_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -263,7 +252,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_10_beqz.f
|
||||
EXTRACT_FMT_10_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
|
||||
|
||||
EXTRACT_FMT_10_BEQZ_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -277,7 +265,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_11_bl8.f
|
||||
EXTRACT_FMT_11_BL8_VARS /* f-op1 f-r1 f-disp8 */
|
||||
|
||||
EXTRACT_FMT_11_BL8_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -291,7 +278,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_12_bl24.f
|
||||
EXTRACT_FMT_12_BL24_VARS /* f-op1 f-r1 f-disp24 */
|
||||
|
||||
EXTRACT_FMT_12_BL24_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -305,7 +291,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_13_bcl8.f
|
||||
EXTRACT_FMT_13_BCL8_VARS /* f-op1 f-r1 f-disp8 */
|
||||
|
||||
EXTRACT_FMT_13_BCL8_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -320,7 +305,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_14_bcl24.f
|
||||
EXTRACT_FMT_14_BCL24_VARS /* f-op1 f-r1 f-disp24 */
|
||||
|
||||
EXTRACT_FMT_14_BCL24_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -335,7 +319,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_15_bra8.f
|
||||
EXTRACT_FMT_15_BRA8_VARS /* f-op1 f-r1 f-disp8 */
|
||||
|
||||
EXTRACT_FMT_15_BRA8_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -348,7 +331,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_16_bra24.f
|
||||
EXTRACT_FMT_16_BRA24_VARS /* f-op1 f-r1 f-disp24 */
|
||||
|
||||
EXTRACT_FMT_16_BRA24_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -361,7 +343,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_17_cmp.f
|
||||
EXTRACT_FMT_17_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_17_CMP_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -375,7 +356,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_18_cmpi.f
|
||||
EXTRACT_FMT_18_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_18_CMPI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -389,7 +369,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_19_cmpui.f
|
||||
EXTRACT_FMT_19_CMPUI_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
|
||||
|
||||
EXTRACT_FMT_19_CMPUI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -403,7 +382,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_20_cmpz.f
|
||||
EXTRACT_FMT_20_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_20_CMPZ_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -416,7 +394,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_21_div.f
|
||||
EXTRACT_FMT_21_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_21_DIV_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -430,7 +407,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_22_jc.f
|
||||
EXTRACT_FMT_22_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_22_JC_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -444,7 +420,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_23_jl.f
|
||||
EXTRACT_FMT_23_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_23_JL_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -458,7 +433,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_24_jmp.f
|
||||
EXTRACT_FMT_24_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_24_JMP_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -471,11 +445,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_25_ld.f
|
||||
EXTRACT_FMT_25_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_25_LD_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_memory) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
|
||||
OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
|
|
@ -485,11 +458,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_26_ld_d.f
|
||||
EXTRACT_FMT_26_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_26_LD_D_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_memory) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
|
||||
OPRND (h_memory_add_WI_sr_slo16) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
|
||||
OPRND (slo16) = f_simm16;
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
|
|
@ -500,11 +472,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_27_ldb.f
|
||||
EXTRACT_FMT_27_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_27_LDB_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_memory) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
|
||||
OPRND (h_memory_sr) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
|
|
@ -514,11 +485,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_28_ldb_d.f
|
||||
EXTRACT_FMT_28_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_28_LDB_D_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_memory) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
|
||||
OPRND (h_memory_add_WI_sr_slo16) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
|
||||
OPRND (slo16) = f_simm16;
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
|
|
@ -529,11 +499,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_29_ldh.f
|
||||
EXTRACT_FMT_29_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_29_LDH_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_memory) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
|
||||
OPRND (h_memory_sr) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
|
|
@ -543,11 +512,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_30_ldh_d.f
|
||||
EXTRACT_FMT_30_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_30_LDH_D_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_memory) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
|
||||
OPRND (h_memory_add_WI_sr_slo16) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
|
||||
OPRND (slo16) = f_simm16;
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
|
|
@ -558,7 +526,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_31_ld24.f
|
||||
EXTRACT_FMT_31_LD24_VARS /* f-op1 f-r1 f-uimm24 */
|
||||
|
||||
EXTRACT_FMT_31_LD24_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -571,7 +538,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_32_ldi8.f
|
||||
EXTRACT_FMT_32_LDI8_VARS /* f-op1 f-r1 f-simm8 */
|
||||
|
||||
EXTRACT_FMT_32_LDI8_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -584,7 +550,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_33_ldi16.f
|
||||
EXTRACT_FMT_33_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_33_LDI16_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
|
|
@ -593,27 +558,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_34_MACHI) : /* e.g. machi $src1,$src2 */
|
||||
CASE (read, READ_FMT_34_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi.f
|
||||
EXTRACT_FMT_34_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_34_MACHI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accum) = CPU (h_accum);
|
||||
OPRND (src1) = CPU (h_gr[f_r1]);
|
||||
OPRND (src2) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_35_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_machi_a.f
|
||||
EXTRACT_FMT_35_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
|
||||
|
||||
EXTRACT_FMT_35_MACHI_A_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_34_machi_a.f
|
||||
EXTRACT_FMT_34_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
|
||||
EXTRACT_FMT_34_MACHI_A_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc);
|
||||
|
|
@ -623,12 +572,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_36_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
|
||||
CASE (read, READ_FMT_35_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mulhi_a.f
|
||||
EXTRACT_FMT_36_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
|
||||
|
||||
EXTRACT_FMT_36_MULHI_A_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_35_mulhi_a.f
|
||||
EXTRACT_FMT_35_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
|
||||
EXTRACT_FMT_35_MULHI_A_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (src1) = CPU (h_gr[f_r1]);
|
||||
|
|
@ -637,12 +585,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_37_MV) : /* e.g. mv $dr,$sr */
|
||||
CASE (read, READ_FMT_36_MV) : /* e.g. mv $dr,$sr */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mv.f
|
||||
EXTRACT_FMT_37_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_37_MV_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_36_mv.f
|
||||
EXTRACT_FMT_36_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_36_MV_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
|
|
@ -650,25 +597,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_38_MVFACHI) : /* e.g. mvfachi $dr */
|
||||
CASE (read, READ_FMT_37_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfachi.f
|
||||
EXTRACT_FMT_38_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_38_MVFACHI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accum) = CPU (h_accum);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_39_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvfachi_a.f
|
||||
EXTRACT_FMT_39_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
|
||||
|
||||
EXTRACT_FMT_39_MVFACHI_A_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_37_mvfachi_a.f
|
||||
EXTRACT_FMT_37_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
|
||||
EXTRACT_FMT_37_MVFACHI_A_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
|
||||
|
|
@ -676,12 +609,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_40_MVFC) : /* e.g. mvfc $dr,$scr */
|
||||
CASE (read, READ_FMT_38_MVFC) : /* e.g. mvfc $dr,$scr */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvfc.f
|
||||
EXTRACT_FMT_40_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_40_MVFC_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_38_mvfc.f
|
||||
EXTRACT_FMT_38_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_38_MVFC_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2);
|
||||
|
|
@ -689,26 +621,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_41_MVTACHI) : /* e.g. mvtachi $src1 */
|
||||
CASE (read, READ_FMT_39_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_mvtachi.f
|
||||
EXTRACT_FMT_41_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_41_MVTACHI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accum) = CPU (h_accum);
|
||||
OPRND (src1) = CPU (h_gr[f_r1]);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_42_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_mvtachi_a.f
|
||||
EXTRACT_FMT_42_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
|
||||
|
||||
EXTRACT_FMT_42_MVTACHI_A_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_39_mvtachi_a.f
|
||||
EXTRACT_FMT_39_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
|
||||
EXTRACT_FMT_39_MVTACHI_A_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
|
||||
|
|
@ -717,12 +634,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_43_MVTC) : /* e.g. mvtc $sr,$dcr */
|
||||
CASE (read, READ_FMT_40_MVTC) : /* e.g. mvtc $sr,$dcr */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_mvtc.f
|
||||
EXTRACT_FMT_43_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_43_MVTC_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_40_mvtc.f
|
||||
EXTRACT_FMT_40_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_40_MVTC_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (sr) = CPU (h_gr[f_r2]);
|
||||
|
|
@ -730,37 +646,22 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_44_NOP) : /* e.g. nop */
|
||||
CASE (read, READ_FMT_41_NOP) : /* e.g. nop */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_nop.f
|
||||
EXTRACT_FMT_44_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_44_NOP_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_41_nop.f
|
||||
EXTRACT_FMT_41_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_41_NOP_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_45_RAC) : /* e.g. rac */
|
||||
CASE (read, READ_FMT_42_RAC_A) : /* e.g. rac $accs */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_rac.f
|
||||
EXTRACT_FMT_45_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_45_RAC_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accum) = CPU (h_accum);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_46_RAC_A) : /* e.g. rac $accs */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_rac_a.f
|
||||
EXTRACT_FMT_46_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
|
||||
|
||||
EXTRACT_FMT_46_RAC_A_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_42_rac_a.f
|
||||
EXTRACT_FMT_42_RAC_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
|
||||
EXTRACT_FMT_42_RAC_A_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
|
||||
|
|
@ -768,12 +669,26 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_47_SETH) : /* e.g. seth $dr,$hi16 */
|
||||
CASE (read, READ_FMT_43_RTE) : /* e.g. rte */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_seth.f
|
||||
EXTRACT_FMT_47_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_43_rte.f
|
||||
EXTRACT_FMT_43_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_43_RTE_CODE
|
||||
|
||||
EXTRACT_FMT_47_SETH_CODE
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_bcond_0) = CPU (h_bcond);
|
||||
OPRND (h_bie_0) = CPU (h_bie);
|
||||
OPRND (h_bpc_0) = CPU (h_bpc);
|
||||
OPRND (h_bsm_0) = CPU (h_bsm);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_44_SETH) : /* e.g. seth $dr,#$hi16 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_44_seth.f
|
||||
EXTRACT_FMT_44_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
|
||||
EXTRACT_FMT_44_SETH_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (hi16) = f_hi16;
|
||||
|
|
@ -781,12 +696,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_48_SLLI) : /* e.g. slli $dr,#$uimm5 */
|
||||
CASE (read, READ_FMT_45_SLLI) : /* e.g. slli $dr,#$uimm5 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_slli.f
|
||||
EXTRACT_FMT_48_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
|
||||
|
||||
EXTRACT_FMT_48_SLLI_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_45_slli.f
|
||||
EXTRACT_FMT_45_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
|
||||
EXTRACT_FMT_45_SLLI_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (dr) = CPU (h_gr[f_r1]);
|
||||
|
|
@ -795,12 +709,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_49_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
|
||||
CASE (read, READ_FMT_46_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_st_d.f
|
||||
EXTRACT_FMT_49_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
|
||||
EXTRACT_FMT_49_ST_D_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_46_st_d.f
|
||||
EXTRACT_FMT_46_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
|
||||
EXTRACT_FMT_46_ST_D_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (slo16) = f_simm16;
|
||||
|
|
@ -810,12 +723,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_50_TRAP) : /* e.g. trap #$uimm4 */
|
||||
CASE (read, READ_FMT_47_TRAP) : /* e.g. trap #$uimm4 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_trap.f
|
||||
EXTRACT_FMT_50_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
|
||||
|
||||
EXTRACT_FMT_50_TRAP_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_47_trap.f
|
||||
EXTRACT_FMT_47_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
|
||||
EXTRACT_FMT_47_TRAP_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (uimm4) = f_uimm4;
|
||||
|
|
@ -823,65 +735,77 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_51_SATB) : /* e.g. satb $dr,$src2 */
|
||||
CASE (read, READ_FMT_48_SATB) : /* e.g. satb $dr,$src2 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_satb.f
|
||||
EXTRACT_FMT_51_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
|
||||
|
||||
EXTRACT_FMT_51_SATB_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_48_satb.f
|
||||
EXTRACT_FMT_48_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
|
||||
EXTRACT_FMT_48_SATB_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (src2) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_52_PCMPBZ) : /* e.g. pcmpbz $src2 */
|
||||
CASE (read, READ_FMT_49_SAT) : /* e.g. sat $dr,$src2 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_pcmpbz.f
|
||||
EXTRACT_FMT_52_PCMPBZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_52_PCMPBZ_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_49_sat.f
|
||||
EXTRACT_FMT_49_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
|
||||
EXTRACT_FMT_49_SAT_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (condbit) = CPU (h_cond);
|
||||
OPRND (src2) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_53_SADD) : /* e.g. sadd */
|
||||
CASE (read, READ_FMT_50_SADD) : /* e.g. sadd */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sadd.f
|
||||
EXTRACT_FMT_53_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_53_SADD_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_50_sadd.f
|
||||
EXTRACT_FMT_50_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_50_SADD_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 0);
|
||||
OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 1);
|
||||
OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0);
|
||||
OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_54_MACWU1) : /* e.g. macwu1 $src1,$src2 */
|
||||
CASE (read, READ_FMT_51_MACWU1) : /* e.g. macwu1 $src1,$src2 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_54_macwu1.f
|
||||
EXTRACT_FMT_54_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
|
||||
EXTRACT_FMT_54_MACWU1_CODE
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_51_macwu1.f
|
||||
EXTRACT_FMT_51_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_51_MACWU1_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (h_accums) = m32rx_h_accums_get (current_cpu, 1);
|
||||
OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
|
||||
OPRND (src1) = CPU (h_gr[f_r1]);
|
||||
OPRND (src2) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_55_SC) : /* e.g. sc */
|
||||
CASE (read, READ_FMT_52_MSBLO) : /* e.g. msblo $src1,$src2 */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_55_sc.f
|
||||
EXTRACT_FMT_55_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_52_msblo.f
|
||||
EXTRACT_FMT_52_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_52_MSBLO_CODE
|
||||
|
||||
EXTRACT_FMT_55_SC_CODE
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (accum) = CPU (h_accum);
|
||||
OPRND (src1) = CPU (h_gr[f_r1]);
|
||||
OPRND (src2) = CPU (h_gr[f_r2]);
|
||||
#undef OPRND
|
||||
}
|
||||
BREAK (read);
|
||||
|
||||
CASE (read, READ_FMT_53_SC) : /* e.g. sc */
|
||||
{
|
||||
#define OPRND(f) CPU_PAR_EXEC (current_cpu)->operands.fmt_53_sc.f
|
||||
EXTRACT_FMT_53_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
|
||||
EXTRACT_FMT_53_SC_CODE
|
||||
|
||||
/* Fetch the input operands for the semantic handler. */
|
||||
OPRND (condbit) = CPU (h_cond);
|
||||
|
|
|
|||
580
sim/m32r/sem.c
580
sim/m32r/sem.c
File diff suppressed because it is too large
Load Diff
1891
sim/m32r/semx.c
1891
sim/m32r/semx.c
File diff suppressed because it is too large
Load Diff
|
|
@ -9,6 +9,7 @@ typedef struct _sim_cpu SIM_CPU;
|
|||
sim-basics.h and cgen-types.h needs config.h. */
|
||||
#include "config.h"
|
||||
|
||||
#include "ansidecl.h"
|
||||
#include "cgen-types.h"
|
||||
#include "arch.h"
|
||||
#include "sim-basics.h"
|
||||
|
|
@ -24,7 +25,6 @@ typedef SI sim_cia;
|
|||
#include "cgen-sim.h"
|
||||
/*#include "cgen-mem.h"*/
|
||||
#include "cgen-trace.h"
|
||||
#include "cpu-opc.h" /* Needed for INSN_NAME. */
|
||||
#include "cpu-sim.h"
|
||||
|
||||
#ifdef WANT_CPU_M32R
|
||||
|
|
|
|||
Loading…
Reference in New Issue