PowerPC64 __tls_get_addr sequence optimization
There isn't a good reason for ld.bfd to behave differently from gold in the code generated by TLS GD/LD to LE optimization. bfd/ * elf64-ppc.c (ppc64_elf_relocate_section): When optimizing __tls_get_addr call sequences to LE, don't move the addi down to the nop. Replace the bl with addi and leave the nop alone. ld/ * testsuite/ld-powerpc/tls.d: Update. * testsuite/ld-powerpc/tlsexe.d: Update. * testsuite/ld-powerpc/tlsexetoc.d: Update. * testsuite/ld-powerpc/tlsld.d: Update. * testsuite/ld-powerpc/tlsmark.d: Update. * testsuite/ld-powerpc/tlsopt4.d: Update. * testsuite/ld-powerpc/tlstoc.d: Update.
This commit is contained in:
Alan Modra
parent
c7dffc390c
commit
b9f04fe0df
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@ -1,3 +1,9 @@
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2017-08-30 Alan Modra <amodra@gmail.com>
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* elf64-ppc.c (ppc64_elf_relocate_section): When optimizing
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__tls_get_addr call sequences to LE, don't move the addi down
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to the nop. Replace the bl with addi and leave the nop alone.
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2017-08-29 H.J. Lu <hongjiu.lu@intel.com>
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* elf32-i386.c (elf_i386_pie_finish_undefweak_symbol):
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@ -13916,7 +13916,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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case R_PPC64_GOT_TLSLD16_LO:
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if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
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{
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unsigned int insn1, insn2, insn3;
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unsigned int insn1, insn2;
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bfd_vma offset;
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tls_ldgd_opt:
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@ -13995,18 +13995,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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bfd_put_32 (input_bfd, insn1,
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contents + rel->r_offset - d_offset);
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if (offset != (bfd_vma) -1)
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{
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insn3 = bfd_get_32 (input_bfd,
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contents + offset + 4);
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if (insn3 == NOP
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|| insn3 == CROR_151515 || insn3 == CROR_313131)
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{
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rel[1].r_offset += 4;
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bfd_put_32 (input_bfd, insn2, contents + offset + 4);
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insn2 = NOP;
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}
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bfd_put_32 (input_bfd, insn2, contents + offset);
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}
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bfd_put_32 (input_bfd, insn2, contents + offset);
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if ((tls_mask & tls_gd) == 0
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&& (tls_gd == 0 || toc_symndx != 0))
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{
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@ -14020,7 +14009,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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case R_PPC64_TLSGD:
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if (tls_mask != 0 && (tls_mask & TLS_GD) == 0)
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{
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unsigned int insn2, insn3;
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unsigned int insn2;
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bfd_vma offset = rel->r_offset;
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if ((tls_mask & TLS_TPRELGD) != 0)
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@ -14045,15 +14034,6 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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/* Zap the reloc on the _tls_get_addr call too. */
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BFD_ASSERT (offset == rel[1].r_offset);
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rel[1].r_info = ELF64_R_INFO (STN_UNDEF, R_PPC64_NONE);
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insn3 = bfd_get_32 (input_bfd,
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contents + offset + 4);
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if (insn3 == NOP
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|| insn3 == CROR_151515 || insn3 == CROR_313131)
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{
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rel->r_offset += 4;
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bfd_put_32 (input_bfd, insn2, contents + offset + 4);
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insn2 = NOP;
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}
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bfd_put_32 (input_bfd, insn2, contents + offset);
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if ((tls_mask & TLS_TPRELGD) == 0 && toc_symndx != 0)
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goto again;
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@ -14063,7 +14043,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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case R_PPC64_TLSLD:
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if (tls_mask != 0 && (tls_mask & TLS_LD) == 0)
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{
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unsigned int insn2, insn3;
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unsigned int insn2;
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bfd_vma offset = rel->r_offset;
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if (toc_symndx)
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@ -14088,15 +14068,6 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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BFD_ASSERT (offset == rel[1].r_offset);
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rel[1].r_info = ELF64_R_INFO (STN_UNDEF, R_PPC64_NONE);
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insn2 = 0x38630000; /* addi 3,3,0 */
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insn3 = bfd_get_32 (input_bfd,
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contents + offset + 4);
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if (insn3 == NOP
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|| insn3 == CROR_151515 || insn3 == CROR_313131)
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{
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rel->r_offset += 4;
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bfd_put_32 (input_bfd, insn2, contents + offset + 4);
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insn2 = NOP;
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}
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bfd_put_32 (input_bfd, insn2, contents + offset);
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goto again;
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}
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10
ld/ChangeLog
10
ld/ChangeLog
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@ -1,3 +1,13 @@
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2017-08-30 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/tls.d: Update.
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* testsuite/ld-powerpc/tlsexe.d: Update.
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* testsuite/ld-powerpc/tlsexetoc.d: Update.
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* testsuite/ld-powerpc/tlsld.d: Update.
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* testsuite/ld-powerpc/tlsmark.d: Update.
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* testsuite/ld-powerpc/tlsopt4.d: Update.
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* testsuite/ld-powerpc/tlstoc.d: Update.
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2017-08-30 Hans-Peter Nilsson <hp@axis.com>
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* testsuite/ld-cris/dso-pltdis1.d: Run ld with --hash-style=sysv.
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@ -11,17 +11,17 @@ Disassembly of section \.text:
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0+100000e8 <\._start>:
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 78|78 90 63 38) addi r3,r3,-28552
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (38 63 90 40|40 90 63 38) addi r3,r3,-28608
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (39 23 80 48|48 80 23 39) addi r9,r3,-32696
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.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.*: (81 49 80 50|50 80 49 81) lwz r10,-32688\(r9\)
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@ -33,11 +33,11 @@ Disassembly of section \.text:
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.*: (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
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.*: (99 49 90 70|70 90 49 99) stb r10,-28560\(r9\)
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (f9 43 80 08|08 80 43 f9) std r10,-32760\(r3\)
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.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.*: (91 49 80 10|10 80 49 91) stw r10,-32752\(r9\)
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@ -30,17 +30,17 @@ Disassembly of section \.text:
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.* <._start>:
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.* (e8 62 80 10|10 80 62 e8) ld r3,-32752\(r2\)
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.* (60 00 00 00|00 00 00 60) nop
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.* (7c 63 6a 14|14 6a 63 7c) add r3,r3,r13
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.* (60 00 00 00|00 00 00 60) nop
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.* (38 62 80 18|18 80 62 38) addi r3,r2,-32744
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.* (4b ff ff a9|a9 ff ff 4b) bl .*
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (38 63 90 38|38 90 63 38) addi r3,r3,-28616
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.* (60 00 00 00|00 00 00 60) nop
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.* (39 23 80 40|40 80 23 39) addi r9,r3,-32704
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.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.* (81 49 80 48|48 80 49 81) lwz r10,-32696\(r9\)
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@ -52,11 +52,11 @@ Disassembly of section \.text:
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.* (3d 2d 00 00|00 00 2d 3d) addis r9,r13,0
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.* (99 49 90 68|68 90 49 99) stb r10,-28568\(r9\)
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (38 63 90 00|00 90 63 38) addi r3,r3,-28672
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.* (60 00 00 00|00 00 00 60) nop
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.* (f9 43 80 08|08 80 43 f9) std r10,-32760\(r3\)
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.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.* (91 49 80 10|10 80 49 91) stw r10,-32752\(r9\)
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@ -36,11 +36,11 @@ Disassembly of section \.text:
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.* (4b ff ff a9|a9 ff ff 4b) bl .*
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (38 63 90 38|38 90 63 38) addi r3,r3,-28616
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.* (60 00 00 00|00 00 00 60) nop
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.* (39 23 80 40|40 80 23 39) addi r9,r3,-32704
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.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.* (81 49 80 48|48 80 49 81) lwz r10,-32696\(r9\)
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@ -12,15 +12,15 @@ Disassembly of section \.text:
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.* nop
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.* addis r29,r13,0
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.* mr r3,r29
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.* nop
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.* addi r3,r3,4096
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.* nop
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.* addis r3,r3,0
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.* ld r3,-32768\(r3\)
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.* nop
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.* addis r29,r13,0
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.* mr r3,r29
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.* nop
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.* addi r3,r3,4096
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.* nop
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.* ld r3,-32768\(r3\)
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.* nop
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.* nop
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@ -28,15 +28,15 @@ Disassembly of section \.text:
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.* nop
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.* addis r29,r13,0
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.* mr r3,r29
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.* nop
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.* addi r3,r3,-28672
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.* nop
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.* ld r3,0\(r3\)
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.* nop
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.* nop
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.* addis r29,r13,0
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.* mr r3,r29
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.* nop
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.* addi r3,r3,-28672
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.* nop
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.* ld r3,0\(r3\)
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.* nop
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.* nop
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@ -11,26 +11,26 @@ Disassembly of section \.text:
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0+100000e8 <_start>:
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.*: (48 00 00 18|18 00 00 48) b 10000100 <_start\+0x18>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 00|00 90 63 38) addi r3,r3,-28672
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (e8 83 00 00|00 00 83 e8) ld r4,0\(r3\)
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (48 00 00 0c|0c 00 00 48) b 10000108 <_start\+0x20>
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (4b ff ff e8|e8 ff ff 4b) b 100000ec <_start\+0x4>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (e8 83 80 00|00 80 83 e8) ld r4,-32768\(r3\)
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (48 00 00 0c|0c 00 00 48) b 10000124 <_start\+0x3c>
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (48 00 00 14|14 00 00 48) b 10000134 <_start\+0x4c>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 04|04 90 63 38) addi r3,r3,-28668
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (e8 a3 00 00|00 00 a3 e8) ld r5,0\(r3\)
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.*: (4b ff ff ec|ec ff ff 4b) b 1000011c <_start\+0x34>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (e8 a3 80 04|04 80 a3 e8) ld r5,-32764\(r3\)
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0+10000140 <\.__tls_get_addr>:
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@ -18,11 +18,11 @@ Disassembly of section \.opt1:
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
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.*: (41 82 00 10|10 00 82 41) beq .*
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (48 00 00 0c|0c 00 00 48) b .*
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
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.*: (60 00 00 00|00 00 00 60) nop
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Disassembly of section \.opt2:
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@ -31,8 +31,8 @@ Disassembly of section \.opt2:
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.*: (2c 24 00 00|00 00 24 2c) cmpdi r4,0
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.*: (41 82 00 08|08 00 82 41) beq .*
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
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.*: (60 00 00 00|00 00 00 60) nop
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Disassembly of section \.opt3:
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@ -41,8 +41,8 @@ Disassembly of section \.opt3:
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.*: (48 00 00 0c|0c 00 00 48) b .*
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.*: (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.*: (48 00 00 10|10 00 00 48) b .*
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
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.*: (48 00 00 0c|0c 00 00 48) b .*
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (48 00 00 0c|0c 00 00 48) b .*
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.*: (38 63 90 08|08 90 63 38) addi r3,r3,-28664
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.*: (60 00 00 00|00 00 00 60) nop
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|
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@ -14,17 +14,17 @@ Disassembly of section \.text:
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.* <\._start>:
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (38 63 90 40|40 90 63 38) addi r3,r3,-28608
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (38 63 90 48|48 90 63 38) addi r3,r3,-28600
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (60 00 00 00|00 00 00 60) nop
|
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.* (3c 6d 00 00|00 00 6d 3c) addis r3,r13,0
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.* (38 63 10 00|00 10 63 38) addi r3,r3,4096
|
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.* (60 00 00 00|00 00 00 60) nop
|
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.* (39 23 80 50|50 80 23 39) addi r9,r3,-32688
|
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.* (3d 23 00 00|00 00 23 3d) addis r9,r3,0
|
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.* (81 49 80 58|58 80 49 81) lwz r10,-32680\(r9\)
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Reference in New Issue