Reduce excessive .eh_frame alignment for powerpc
PowerPC64 .cfi directives use DW_EH_PE_sdata4 encoding for .eh_frame, so there is no real reason why .eh_frame should be 8 byte aligned. gas/ * config/tc-ppc.h (EH_FRAME_ALIGNMENT): Define. ld/ * testsuite/ld-powerpc/tlsopt5.wf: Update for reduced alignment.
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@ -1,3 +1,7 @@
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2017-09-21 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.h (EH_FRAME_ALIGNMENT): Define.
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2017-09-14 Alan Modra <amodra@gmail.com>
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PR 22127
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@ -325,3 +325,4 @@ extern int ppc_dwarf2_line_min_insn_length;
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#define DWARF2_LINE_MIN_INSN_LENGTH ppc_dwarf2_line_min_insn_length
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#define DWARF2_DEFAULT_RETURN_COLUMN 0x41
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#define DWARF2_CIE_DATA_ALIGNMENT ppc_cie_data_alignment
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#define EH_FRAME_ALIGNMENT 2
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@ -1,3 +1,7 @@
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2017-09-21 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/tlsopt5.wf: Update for reduced alignment.
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2017-09-19 Maciej W. Rozycki <macro@imgtec.com>
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* configure.tgt <mips64el-*-openbsd*, mips64-*-openbsd*>: New
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@ -16,17 +16,13 @@ Contents of the \.eh_frame section:
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DW_CFA_advance_loc: 16 to .*
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DW_CFA_restore_extended: r65
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0+2c 0+18 0+30 FDE cie=0+ pc=.*
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0+2c 0+14 0+30 FDE cie=0+ pc=.*
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DW_CFA_advance_loc: 4 to .*
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DW_CFA_register: r65 in r0
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DW_CFA_advance_loc: 28 to .*
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DW_CFA_restore_extended: r65
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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0+48 0+10 0+4c FDE cie=0+ pc=.*
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0+44 0+10 0+48 FDE cie=0+ pc=.*
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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