Add support for converting VLDR <reg>,=<constant> to a VMOV instruction when appropriate.
PR gas/18500 gas * config/tc-arm.c (is_double_a_single): New function. (double_to_single): New function. (move_or_literal_pool): Add support for converting VLDR to VMOV. tests * gas/arm/vfpv2-ldr_immediate.s: New test case. * gas/arm/vfpv2-ldr_immediate.d: Expected disassembly. * gas/arm/vfpv3-ldr_immediate.s: New test case. * gas/arm/vfpv3-ldr_immediate.d: Expected disassembly. * gas/arm/vfpv3xd-ldr_immediate.s: New test case. * gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
This commit is contained in:
Alessandro Marzocchi
Nick Clifton
parent
fc24848555
commit
ba592044bc
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@ -1,3 +1,10 @@
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2015-06-17 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
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PR gas/18500
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* config/tc-arm.c (is_double_a_single): New function.
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(double_to_single): New function.
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(move_or_literal_pool): Add support for converting VLDR to VMOV.
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2015-06-17 Nicolas Pitre <nico@linaro.org>
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* as.c (show_usage): Document --sectname-subst.
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@ -4924,7 +4924,9 @@ parse_fpa_immediate (char ** str)
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{
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/* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
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Ditto for 15. */
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if (gen_to_words (words, 5, (long) 15) == 0)
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#define X_PRECISION 5
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#define E_PRECISION 15L
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if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
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{
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for (i = 0; i < NUM_FLOAT_VALS; i++)
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{
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@ -7750,6 +7752,52 @@ neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
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return FAIL;
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}
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/* Returns TRUE if double precision value V may be cast
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to single precision without loss of accuracy. */
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static bfd_boolean
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is_double_a_single (long int v)
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{
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int exp = (int) (v >> 52) & 0x7FF;
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long int mantissa = (v & 0xFFFFFFFFFFFFFl);
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return (exp == 0 || exp == 0x7FF
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|| (exp >= 1023 - 126 && exp <= 1023 + 127))
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&& (mantissa & 0x1FFFFFFFl) == 0;
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}
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/* Returns a double precision value casted to single precision
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(ignoring the least significant bits in exponent and mantissa). */
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static int
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double_to_single (long int v)
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{
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int sign = (int) ((v >> 63) & 1l);
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int exp = (int) (v >> 52) & 0x7FF;
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long int mantissa = (v & 0xFFFFFFFFFFFFFl);
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if (exp == 0x7FF)
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exp = 0xFF;
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else
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{
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exp = exp - 1023 + 127;
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if (exp >= 0xFF)
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{
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/* Infinity. */
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exp = 0x7F;
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mantissa = 0;
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}
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else if (exp < 0)
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{
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/* No denormalized numbers. */
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exp = 0;
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mantissa = 0;
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}
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}
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mantissa >>= 29;
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return (sign << 31) | (exp << 23) | mantissa;
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}
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enum lit_type
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{
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CONST_THUMB,
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@ -7757,6 +7805,8 @@ enum lit_type
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CONST_VEC
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};
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static void do_vfp_nsyn_opcode (const char *);
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/* inst.reloc.exp describes an "=expr" load pseudo-operation.
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Determine whether it can be performed with a move instruction; if
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it can, convert inst.instruction to that move instruction and
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@ -7772,7 +7822,6 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
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unsigned long tbit;
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bfd_boolean thumb_p = (t == CONST_THUMB);
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bfd_boolean arm_p = (t == CONST_ARM);
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bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;
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if (thumb_p)
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tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
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@ -7784,6 +7833,7 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
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inst.error = _("invalid pseudo operation");
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return TRUE;
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}
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if (inst.reloc.exp.X_op != O_constant
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&& inst.reloc.exp.X_op != O_symbol
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&& inst.reloc.exp.X_op != O_big)
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@ -7791,77 +7841,130 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
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inst.error = _("constant expression expected");
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return TRUE;
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}
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if ((inst.reloc.exp.X_op == O_constant
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|| inst.reloc.exp.X_op == O_big)
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&& !inst.operands[i].issingle)
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if (inst.reloc.exp.X_op == O_constant
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|| inst.reloc.exp.X_op == O_big)
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{
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if (thumb_p && inst.reloc.exp.X_op == O_constant)
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offsetT v;
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if (inst.reloc.exp.X_op == O_big)
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{
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if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
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LITTLENUM_TYPE w[X_PRECISION];
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LITTLENUM_TYPE * l;
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if (inst.reloc.exp.X_add_number == -1)
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{
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/* This can be done with a mov(1) instruction. */
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inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
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inst.instruction |= inst.reloc.exp.X_add_number;
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return TRUE;
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gen_to_words (w, X_PRECISION, E_PRECISION);
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l = w;
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/* FIXME: Should we check words w[2..5] ? */
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}
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else
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l = generic_bignum;
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v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
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| (l[0] & LITTLENUM_MASK);
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}
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else
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v = inst.reloc.exp.X_add_number;
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if (!inst.operands[i].issingle)
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{
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if (thumb_p && inst.reloc.exp.X_op == O_constant)
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{
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if (!unified_syntax && (v & ~0xFF) == 0)
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{
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/* This can be done with a mov(1) instruction. */
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inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
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inst.instruction |= v;
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return TRUE;
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}
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}
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else if (arm_p && inst.reloc.exp.X_op == O_constant)
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{
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int value = encode_arm_immediate (v);
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if (value != FAIL)
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{
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/* This can be done with a mov instruction. */
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inst.instruction &= LITERAL_MASK;
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inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
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inst.instruction |= value & 0xfff;
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return TRUE;
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}
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value = encode_arm_immediate (~ v);
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if (value != FAIL)
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{
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/* This can be done with a mvn instruction. */
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inst.instruction &= LITERAL_MASK;
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inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
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inst.instruction |= value & 0xfff;
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return TRUE;
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}
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}
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else if (t == CONST_VEC)
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{
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int op = 0;
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unsigned immbits = 0;
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unsigned immlo = inst.operands[1].imm;
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unsigned immhi = inst.operands[1].regisimm
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? inst.operands[1].reg
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: inst.reloc.exp.X_unsigned
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? 0
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: ((bfd_int64_t)((int) immlo)) >> 32;
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int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
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&op, 64, NT_invtype);
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if (cmode == FAIL)
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{
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neon_invert_size (&immlo, &immhi, 64);
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op = !op;
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cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
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&op, 64, NT_invtype);
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}
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if (cmode != FAIL)
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{
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inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
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| (1 << 23)
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| (cmode << 8)
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| (op << 5)
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| (1 << 4);
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/* Fill other bits in vmov encoding for both thumb and arm. */
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if (thumb_mode)
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inst.instruction |= (0x7 << 29) | (0xF << 24);
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else
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inst.instruction |= (0xF << 28) | (0x1 << 25);
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neon_write_immbits (immbits);
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return TRUE;
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}
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}
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}
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else if (arm_p && inst.reloc.exp.X_op == O_constant)
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{
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int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
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if (value != FAIL)
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{
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/* This can be done with a mov instruction. */
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inst.instruction &= LITERAL_MASK;
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inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
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inst.instruction |= value & 0xfff;
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return TRUE;
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}
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value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
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if (value != FAIL)
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{
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/* This can be done with a mvn instruction. */
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inst.instruction &= LITERAL_MASK;
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inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
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inst.instruction |= value & 0xfff;
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return TRUE;
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}
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}
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else if (vec64_p)
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if (t == CONST_VEC)
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{
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int op = 0;
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unsigned immbits = 0;
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unsigned immlo = inst.operands[1].imm;
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unsigned immhi = inst.operands[1].regisimm
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? inst.operands[1].reg
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: inst.reloc.exp.X_unsigned
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? 0
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: ((bfd_int64_t)((int) immlo)) >> 32;
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int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
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&op, 64, NT_invtype);
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if (cmode == FAIL)
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/* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
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if (inst.operands[i].issingle
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&& is_quarter_float (inst.operands[1].imm)
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&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
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{
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neon_invert_size (&immlo, &immhi, 64);
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op = !op;
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cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
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&op, 64, NT_invtype);
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}
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if (cmode != FAIL)
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{
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inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
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| (1 << 23)
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| (cmode << 8)
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| (op << 5)
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| (1 << 4);
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/* Fill other bits in vmov encoding for both thumb and arm. */
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if (thumb_mode)
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inst.instruction |= (0x7 << 29) | (0xF << 24);
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else
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inst.instruction |= (0xF << 28) | (0x1 << 25);
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neon_write_immbits (immbits);
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inst.operands[1].imm =
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neon_qfloat_bits (v);
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do_vfp_nsyn_opcode ("fconsts");
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return TRUE;
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}
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else if (!inst.operands[1].issingle
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&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
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{
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if (is_double_a_single (v)
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&& is_quarter_float (double_to_single (v)))
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{
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inst.operands[1].imm =
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neon_qfloat_bits (double_to_single (v));
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do_vfp_nsyn_opcode ("fconstd");
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return TRUE;
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}
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}
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}
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}
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@ -8799,8 +8902,6 @@ do_mov16 (void)
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}
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}
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static void do_vfp_nsyn_opcode (const char *);
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static int
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do_vfp_nsyn_mrs (void)
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{
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@ -1,3 +1,13 @@
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2015-06-17 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
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PR gas/18500
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* gas/arm/vfpv2-ldr_immediate.s: New test case.
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* gas/arm/vfpv2-ldr_immediate.d: Expected disassembly.
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* gas/arm/vfpv3-ldr_immediate.s: New test case.
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* gas/arm/vfpv3-ldr_immediate.d: Expected disassembly.
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* gas/arm/vfpv3xd-ldr_immediate.s: New test case.
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* gas/arm/vfpv3xd-ldr_immediate.d: Expected disassembly.
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2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
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* sysreg.d: Add id_mmfr4_el1, update expected output.
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@ -0,0 +1,50 @@
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# name: VFPv2 vldr to vmov
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# as: -mfpu=vfpv2
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# objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section \.text:
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*3fbe0000 .*
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0[0-9a-fx]+ .*3df00000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*bfc00000 .*
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0[0-9a-fx]+ .*be000000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*3fc00000 .*
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0[0-9a-fx]+ .*3e000000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*3fe08000 .*
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0[0-9a-fx]+ .*3f040000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*3fef0000 .*
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0[0-9a-fx]+ .*3f780000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*403f0000 .*
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0[0-9a-fx]+ .*41f80000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*00000000 .*
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0[0-9a-fx]+ .*40400000 .*
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0[0-9a-fx]+ .*42000000 .*
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#pass
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@ -0,0 +1,48 @@
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.arm
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.syntax unified
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# VFPv2 has no VMOV instruction... all vldr will be kept
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# 15 * 2^-7 =0.1171875 VMOV does not exists
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.align 3
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vldr d0,=0x3FBE000000000000
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vldr s0,=0x3df00000
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.pool
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# -16 * 2^-7 =0.125 VMOV does not exists
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.align 3
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vldr d0,=0xbfc0000000000000
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vldr s0,=0xbe000000
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.pool
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# 16 * 2^-7 =0.125 VMOV does not exists
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.align 3
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vldr d0,=0x3fc0000000000000
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vldr s0,=0x3e000000
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.pool
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# 16.5 * 2^-7 =0.125 VMOV does not exists
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.align 3
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vldr d0,=0x3fe0800000000000
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vldr s0,=0x3f040000
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.pool
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# 31 * 2^-5 = 0.96875 VMOV does not exists
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.align 3
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vldr d0,=0x3fef000000000000
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vldr s0,=0x3f780000
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.pool
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# 31 * 2^ 0 = 31 VMOV does not exists
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.align 3
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vldr d0,=0x403F000000000000
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vldr s0,=0x41f80000
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.pool
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# 16 * 2^ 1 = 32 VMOV does not exists
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.align 3
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vldr d0,=0x4040000000000000
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vldr s0,=0x42000000
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.pool
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nop
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|
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@ -0,0 +1,35 @@
|
|||
# name: VFPv3 vldr to vmov
|
||||
# as: -mfpu=vfp3
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*3fbe0000 .*
|
||||
0[0-9a-fx]+ .*3df00000 .*
|
||||
.*
|
||||
|
||||
0[0-9a-fx]+ .*eebc0b00 (vmov\.f64|fconstd) d0, #192.*
|
||||
0[0-9a-fx]+ .*eebc0a00 (vmov\.f32|fconsts) s0, #192.*
|
||||
0[0-9a-fx]+ .*eeb40b00 (vmov\.f64|fconstd) d0, #64.*
|
||||
0[0-9a-fx]+ .*eeb40a00 (vmov\.f32|fconsts) s0, #64.*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*3fe08000 .*
|
||||
0[0-9a-fx]+ .*3f040000 .*
|
||||
.*
|
||||
0[0-9a-fx]+ .*eeb60b0f (vmov\.f64|fconstd) d0, #111.*
|
||||
0[0-9a-fx]+ .*eeb60a0f (vmov\.f32|fconsts) s0, #111.*
|
||||
0[0-9a-fx]+ .*eeb30b0f (vmov\.f64|fconstd) d0, #63.*
|
||||
0[0-9a-fx]+ .*eeb30a0f (vmov\.f32|fconsts) s0, #63.*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*40400000 .*
|
||||
0[0-9a-fx]+ .*42000000 .*
|
||||
#pass
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
.arm
|
||||
.syntax unified
|
||||
# 15 * 2^-7 =0.1171875 Not convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3FBE000000000000
|
||||
vldr s0,=0x3df00000
|
||||
.pool
|
||||
|
||||
# -16 * 2^-7 =-0.125 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0xbfc0000000000000
|
||||
vldr s0,=0xbe000000
|
||||
.pool
|
||||
|
||||
# 16 * 2^-7 =0.125 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3fc0000000000000
|
||||
vldr s0,=0x3e000000
|
||||
.pool
|
||||
|
||||
# 16.5 * 2^-7 =0.125 Not convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3fe0800000000000
|
||||
vldr s0,=0x3f040000
|
||||
.pool
|
||||
|
||||
# 31 * 2^-5 = 0.96875 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3fef000000000000
|
||||
vldr s0,=0x3f780000
|
||||
.pool
|
||||
|
||||
# 31 * 2^ 0 = 31 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x403F000000000000
|
||||
vldr s0,=0x41f80000
|
||||
.pool
|
||||
|
||||
# 16 * 2^ 1 = 32 Not convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x4040000000000000
|
||||
vldr s0,=0x42000000
|
||||
.pool
|
||||
|
||||
nop
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# name: VFPv3xd vldr to vmov
|
||||
# as: -mfpu=vfpv3xd
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*3fbe0000 .*
|
||||
0[0-9a-fx]+ .*3df00000 .*
|
||||
.*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*eebc0a00 (vmov\.f32|fconsts) s0, #192.*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*bfc00000 .*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*eeb40a00 (vmov\.f32|fconsts) s0, #64.*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*3fc00000 .*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*3fe08000 .*
|
||||
0[0-9a-fx]+ .*3f040000 .*
|
||||
.*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*eeb60a0f (vmov\.f32|fconsts) s0, #111.*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*3fef0000 .*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*eeb30a0f (vmov\.f32|fconsts) s0, #63.*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*403f0000 .*
|
||||
0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
|
||||
0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
|
||||
0[0-9a-fx]+ .*00000000 .*
|
||||
0[0-9a-fx]+ .*40400000 .*
|
||||
0[0-9a-fx]+ .*42000000 .*
|
||||
#pass
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
.arm
|
||||
.syntax unified
|
||||
# VFPv3xD has no VMOV instruction for double precision registers...
|
||||
# 15 * 2^-7 =0.1171875 Not convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3FBE000000000000
|
||||
vldr s0,=0x3df00000
|
||||
.pool
|
||||
|
||||
# -16 * 2^-7 =0.125 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0xbfc0000000000000
|
||||
vldr s0,=0xbe000000
|
||||
.pool
|
||||
|
||||
# 16 * 2^-7 =0.125 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3fc0000000000000
|
||||
vldr s0,=0x3e000000
|
||||
.pool
|
||||
|
||||
# 16.5 * 2^-7 =0.125 Not convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3fe0800000000000
|
||||
vldr s0,=0x3f040000
|
||||
.pool
|
||||
|
||||
# 31 * 2^-5 = 0.96875 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x3fef000000000000
|
||||
vldr s0,=0x3f780000
|
||||
.pool
|
||||
|
||||
# 31 * 2^ 0 = 31 Convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x403F000000000000
|
||||
vldr s0,=0x41f80000
|
||||
.pool
|
||||
|
||||
# 16 * 2^ 1 = 32 Not convertible to VMOV
|
||||
.align 3
|
||||
vldr d0,=0x4040000000000000
|
||||
vldr s0,=0x42000000
|
||||
.pool
|
||||
|
||||
nop
|
||||
|
||||
11
gas/write.c
11
gas/write.c
|
|
@ -1585,7 +1585,9 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
|
|||
f->fr_literal, (file_ptr) offset,
|
||||
(bfd_size_type) f->fr_fix);
|
||||
if (!x)
|
||||
as_fatal (_("can't write %s: %s"), stdoutput->filename,
|
||||
as_fatal (_("can't write %ld bytes to section %s of %s because: '%s'"),
|
||||
(long) f->fr_fix, sec->name,
|
||||
stdoutput->filename,
|
||||
bfd_errmsg (bfd_get_error ()));
|
||||
offset += f->fr_fix;
|
||||
}
|
||||
|
|
@ -1606,7 +1608,9 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
|
|||
(file_ptr) offset,
|
||||
(bfd_size_type) fill_size);
|
||||
if (!x)
|
||||
as_fatal (_("can't write %s: %s"), stdoutput->filename,
|
||||
as_fatal (_("can't fill %ld bytes in section %s of %s because '%s'"),
|
||||
(long) fill_size, sec->name,
|
||||
stdoutput->filename,
|
||||
bfd_errmsg (bfd_get_error ()));
|
||||
offset += fill_size;
|
||||
}
|
||||
|
|
@ -1636,7 +1640,8 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
|
|||
(stdoutput, sec, buf, (file_ptr) offset,
|
||||
(bfd_size_type) n_per_buf * fill_size);
|
||||
if (!x)
|
||||
as_fatal (_("cannot write to output file '%s': %s"),
|
||||
as_fatal (_("cannot fill %ld bytes in section %s of %s because: '%s'"),
|
||||
(long)(n_per_buf * fill_size), sec->name,
|
||||
stdoutput->filename,
|
||||
bfd_errmsg (bfd_get_error ()));
|
||||
offset += n_per_buf * fill_size;
|
||||
|
|
|
|||
Loading…
Reference in New Issue