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Add pseudo-basic-block execution support. 

* Makefile.in (SIM_OBJS): Add sim-reg.o, cgen-run.o, sim-stop.o.
	(SIM_EXTRA_DEPS): Add include/opcode/cgen.h.
	(INCLUDE_DEPS): Delete cpu-sim.h, include/opcode/cgen.h.
	(mloop.c): Build pseudo-basic-block version.  Depend on stamp-cpu.
	(stamp-decode): Delete, build decode files with other cpu files.
	* arch.c,arch.h,cpuall.h: Regenerate.
	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
	* sem-switch.c,sem.c: Regenerate.
	* m32r-sim.h (M32R_MISC_PROFILE): New members load_regs,
	load_regs_pending.
	* m32r.c (m32rbf_fetch_register): Renamed from m32rb_fetch_register.
	(m32rbf_store_register,m32rbf_h_cr_get,m32rbf_h_cr_set,
	m32rbf_h_psw_get,m32rbf_h_psw_set,m32rbf_h_accum_get,
	m32rbf_h_accum_set): Likewise.
	(m32r_model_{init,update}_insn_cycles): Delete.
	(m32rbf_model_insn_{before,after}): New fns.
	(m32r_model_record_cti,m32r_model_record_cycles): Delete.
	(m32rb_model_mark_get_h_gr,m32rb_model_mark_set_h_gr): Delete.
	(m32rb_model_mark_busy_reg,m32rb_model_mark_unbusy_reg): Delete.
	(check_load_stall): New fn.
	(m32rbf_model_m32r_d_u_{exec,cmp,mac,cti,load,store}): New fns.
	(m32rbf_model_test_u_exec): New fn.
	* mloop.in: Rewrite, use pbb support.
	* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Delete.
	(sim_fetch_register,sim_store_register): Delete.
	* sim-main.h (CIA_GET,CIA_SET): Fix.
	(SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Delete.
	* tconfig.in (WITH_SCACHE_PBB): Define.
	(WITH_SCACHE_PBB_M32RBF): Define.
	* traps.c (sim_engine_invalid_insn): Renamed from ..._illegal_....
	(m32r_trap): Pass pc to sim_engine_halt.
	* configure.in (SIM_AC_OPTION_SCACHE): Change 1024 to 16384.
	* configure: Regenerate.
start-sanitize-m32rx
	* Makefile.in (M32RX_OBJS): Delete semx.o, add extract.o.
	(mloopx.c): Build pseudo-basic-block version.  Depend on stamp-xcpu.
	(semx.o): Delete.
	(extractx.o): Add.
	(stamp-xdecode): Delete, build decode files with other cpu files.
	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c: Regenerate.
	* readx.c: Delete.
	* semx.c: Delete.
	* extractx.c: New file.
	* semx-switch.c: New file.
	* m32r-sim.h (BRANCH_NEW_PC): Delete.
	(SEM_SKIP_INSN): New macro.
	* m32rx.c (m32rxf_fetch_register): Renamed from m32rx_fetch_register.
	(m32rxf_store_register,m32rxf_h_cr_get,m32rxf_h_cr_set,
	m32rxf_h_psw_get,m32rxf_h_psw_set,m32rxf_h_accum_get,
	m32rxf_h_accum_set,m32rxf_h_accums_get,m32rxf_h_accums_set): Likewise.
	(m32rxf_model_insn_{before,after}): New fns.
	(m32rx_model_mark_get_h_gr,m32rx_model_mark_set_h_gr): Delete.
	(m32rx_model_mark_busy_reg,m32rx_model_mark_unbusy_reg): Delete.
	(check_load_stall): New fn.
	(m32rxf_model_m32rx_u_{exec,cmp,mac,cti,load,store}): New fns.
	* mloopx.in: Rewrite, use pbb support.
	* tconfig.in (WITH_SCACHE_PBB_M32RXF): Define.
	(WITH_SEM_SWITCH_FULL): Change from 0 to 1.
end-sanitize-m32rx
This commit is contained in:
Doug Evans 1998-10-09 23:43:28 +00:00
parent 0b517b9cf2
commit bb51b65d68
8 changed files with 1868 additions and 5612 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sim/m32r/.Sanitize
View File

@ -16,7 +16,7 @@
Do-first:
m32rx_files="cpux.c cpux.h decodex.c decodex.h m32rx.c mloopx.in modelx.c readx.c semx.c"
m32rx_files="cpux.c cpux.h decodex.c decodex.h extractx.c m32rx.c mloopx.in modelx.c semx-switch.c"
if ( echo $* | grep keep\-m32rx > /dev/null ) ; then
keep_these_too="${m32rx_files} ${keep_these_too}"
else

88
sim/m32r/ChangeLog
View File

@ -1,3 +1,91 @@
Fri Oct 9 16:11:58 1998 Doug Evans <devans@seba.cygnus.com>
Add pseudo-basic-block execution support.
* Makefile.in (SIM_OBJS): Add sim-reg.o, cgen-run.o, sim-stop.o.
(SIM_EXTRA_DEPS): Add include/opcode/cgen.h.
(INCLUDE_DEPS): Delete cpu-sim.h, include/opcode/cgen.h.
(mloop.c): Build pseudo-basic-block version. Depend on stamp-cpu.
(stamp-decode): Delete, build decode files with other cpu files.
* arch.c,arch.h,cpuall.h: Regenerate.
* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
* sem-switch.c,sem.c: Regenerate.
* m32r-sim.h (M32R_MISC_PROFILE): New members load_regs,
load_regs_pending.
* m32r.c (m32rbf_fetch_register): Renamed from m32rb_fetch_register.
(m32rbf_store_register,m32rbf_h_cr_get,m32rbf_h_cr_set,
m32rbf_h_psw_get,m32rbf_h_psw_set,m32rbf_h_accum_get,
m32rbf_h_accum_set): Likewise.
(m32r_model_{init,update}_insn_cycles): Delete.
(m32rbf_model_insn_{before,after}): New fns.
(m32r_model_record_cti,m32r_model_record_cycles): Delete.
(m32rb_model_mark_get_h_gr,m32rb_model_mark_set_h_gr): Delete.
(m32rb_model_mark_busy_reg,m32rb_model_mark_unbusy_reg): Delete.
(check_load_stall): New fn.
(m32rbf_model_m32r_d_u_{exec,cmp,mac,cti,load,store}): New fns.
(m32rbf_model_test_u_exec): New fn.
* mloop.in: Rewrite, use pbb support.
* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Delete.
(sim_fetch_register,sim_store_register): Delete.
* sim-main.h (CIA_GET,CIA_SET): Fix.
(SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Delete.
* tconfig.in (WITH_SCACHE_PBB): Define.
(WITH_SCACHE_PBB_M32RBF): Define.
* traps.c (sim_engine_invalid_insn): Renamed from ..._illegal_....
(m32r_trap): Pass pc to sim_engine_halt.
* configure.in (SIM_AC_OPTION_SCACHE): Change 1024 to 16384.
* configure: Regenerate.
start-sanitize-m32rx
* Makefile.in (M32RX_OBJS): Delete semx.o, add extract.o.
(mloopx.c): Build pseudo-basic-block version. Depend on stamp-xcpu.
(semx.o): Delete.
(extractx.o): Add.
(stamp-xdecode): Delete, build decode files with other cpu files.
* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c: Regenerate.
* readx.c: Delete.
* semx.c: Delete.
* extractx.c: New file.
* semx-switch.c: New file.
* m32r-sim.h (BRANCH_NEW_PC): Delete.
(SEM_SKIP_INSN): New macro.
* m32rx.c (m32rxf_fetch_register): Renamed from m32rx_fetch_register.
(m32rxf_store_register,m32rxf_h_cr_get,m32rxf_h_cr_set,
m32rxf_h_psw_get,m32rxf_h_psw_set,m32rxf_h_accum_get,
m32rxf_h_accum_set,m32rxf_h_accums_get,m32rxf_h_accums_set): Likewise.
(m32rxf_model_insn_{before,after}): New fns.
(m32rx_model_mark_get_h_gr,m32rx_model_mark_set_h_gr): Delete.
(m32rx_model_mark_busy_reg,m32rx_model_mark_unbusy_reg): Delete.
(check_load_stall): New fn.
(m32rxf_model_m32rx_u_{exec,cmp,mac,cti,load,store}): New fns.
* mloopx.in: Rewrite, use pbb support.
* tconfig.in (WITH_SCACHE_PBB_M32RXF): Define.
(WITH_SEM_SWITCH_FULL): Change from 0 to 1.
end-sanitize-m32rx
Wed Sep 16 18:22:27 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r-sim.h ({PSW,CBR,SPI,SPU,BPC,BBPSW,BBPC}_REGNUM): New macros.
({ACC1L,ACC1H}_REGNUM): New macros.
(m32r_decode_gdb_ctrl_regnum): Add prototype.
* m32r.c (m32r_decode_gdb_ctrl_regnum): New function.
(m32r_fetch_register,m32r_store_register): Rewrite.
start-sanitize-m32rx
* m32rx.c (m32rx_fetch_register,m32rx_store_register): Rewrite.
end-sanitize-m32rx
Tue Sep 15 15:01:14 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r-sim.h (GET_H_SM): New macro.
(UART params): Update to msa2000.
* devices.c (device_io_read_buffer): Update to msa2000.
* m32r.c (m32rb_h_cr_get,m32rb_h_cr_set): Handle bbpc,bbpsw.
(m32rb_h_psw_get,m32rb_h_psw_set): New functions.
* arch.c,arch.h,cpu.c,cpu.h,sem-switch.c,sem.c: Regenerate.
start-sanitize-m32rx
* m32rx.c (m32rx_h_cr_get,m32rx_h_cr_set): Handle bbpc,bbpsw.
(m32rx_h_psw_get,m32rx_h_psw_set): New functions.
* cpux.c,cpux.h,readx.c,semx.c: Regenerate.
end-sanitize-m32rx
Wed Sep 9 15:29:36 1998 Doug Evans <devans@canuck.cygnus.com>
* m32r-sim.h (m32r_trap): Update prototype.

69
sim/m32r/Makefile.in
View File

@ -22,7 +22,7 @@
M32R_OBJS = m32r.o cpu.o decode.o extract.o sem.o model.o mloop.o
# start-sanitize-m32rx
M32RX_OBJS = m32rx.o cpux.o decodex.o semx.o modelx.o mloopx.o
M32RX_OBJS = m32rx.o cpux.o decodex.o extractx.o modelx.o mloopx.o
# end-sanitize-m32rx
CONFIG_DEVICES = dv-sockser.o
@ -31,12 +31,12 @@ CONFIG_DEVICES =
SIM_OBJS = \
$(SIM_NEW_COMMON_OBJS) \
sim-cpu.o \
sim-engine.o \
sim-hload.o \
sim-hrw.o \
sim-model.o \
sim-reason.o \
sim-reg.o \
cgen-utils.o cgen-trace.o cgen-scache.o \
cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
sim-if.o arch.o \
$(M32R_OBJS) \
$(start-sanitize-m32rx) \
@ -50,7 +50,8 @@ SIM_EXTRA_DEPS = \
$(srcdir)/../common/cgen-types.h \
$(srcdir)/../common/cgen-sim.h \
$(srcdir)/../common/cgen-trace.h \
arch.h cpuall.h m32r-sim.h cpu-opc.h
arch.h cpuall.h m32r-sim.h cpu-opc.h \
$(srcdir)/../../include/opcode/cgen.h
SIM_EXTRA_CFLAGS =
@ -73,8 +74,7 @@ MAIN_INCLUDE_DEPS = \
$(srcdir)/../common/sim-trace.h \
$(srcdir)/../common/sim-profile.h \
tconfig.h
INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS) cpu-sim.h \
$(srcdir)/../../include/opcode/cgen.h
INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS)
OPS_INCLUDE_DEPS = \
$(srcdir)/../common/cgen-mem.h \
$(srcdir)/../common/cgen-ops.h
@ -93,21 +93,17 @@ m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile
rm -f mloop.c
$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
-mono -scache -fast m32r $(srcdir)/mloop.in \
| sed -e 's/@cpu@/m32r/' -e 's/@CPU@/M32R/' >mloop.c
mloop.o: mloop.c sem-switch.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
-mono -fast -pbb -switch sem-switch.c \
m32rbf $(srcdir)/mloop.in \
| sed -e 's/@cpu@/m32rbf/' -e 's/@CPU@/M32RBF/' >mloop.c
mloop.o: mloop.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) stamp-cpu
cpu.o: cpu.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
decode.o: decode.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
extract.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
$(CC) -c $(srcdir)/extract.c $(ALL_CFLAGS) -DSCACHE_P
sem.o: sem.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h
$(CC) -c $(srcdir)/sem.c $(ALL_CFLAGS) -DSCACHE_P
model.o: model.c $(INCLUDE_DEPS) cpu.h decode.h
#sem-cache.o: sem.c decode.h $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h
# $(CC) -c $(srcdir)/sem.c -o sem-cache.o -DSCACHE_P $(ALL_CFLAGS)
# start-sanitize-m32rx
# M32RX objs
@ -117,21 +113,22 @@ m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
rm -f mloopx.c
$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \
-mono -no-scache -no-fast -parallel \
m32r $(srcdir)/mloopx.in \
| sed -e 's/@cpu@/m32rx/' -e 's/@CPU@/M32RX/' >mloopx.c
mloopx.o: mloopx.c readx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
-mono -no-fast -pbb -parallel -switch semx-switch.c \
m32rxf $(srcdir)/mloopx.in \
| sed -e 's/@cpu@/m32rxf/' -e 's/@CPU@/M32RXF/' >mloopx.c
mloopx.o: mloopx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) stamp-xcpu
cpux.o: cpux.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
decodex.o: decodex.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
semx.o: semx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
extractx.o: extractx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
#semx.o: semx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h
modelx.o: modelx.c $(INCLUDE_DEPS) cpux.h decodex.h
# end-sanitize-m32rx
m32r-clean:
rm -f mloop.c stamp-arch stamp-cpu stamp-decode
rm -f mloop.c stamp-arch stamp-cpu
# start-sanitize-m32rx
rm -f mloopx.c stamp-xcpu stamp-xdecode
rm -f mloopx.c stamp-xcpu
# end-sanitize-m32rx
rm -f tmp-*
@ -147,33 +144,19 @@ stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
@true
stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32rbf mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
touch stamp-cpu
cpu.h extract.c sem.c sem-switch.c model.c: $(CGEN_MAINT) stamp-cpu
@true
stamp-decode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32r mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn"
touch stamp-decode
decode.h decode.c: $(CGEN_MAINT) stamp-decode
cpu.h extract.c sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
@true
# end-sanitize-cygnus
# start-sanitize-m32rx
stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
cpu=m32rx mach=m32rx SUFFIX=x FLAGS="with-profile fn" EXTRAFILES="$(CGEN_CPU_READ) $(CGEN_CPU_SEM)"
stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEMSW)"
touch stamp-xcpu
cpux.h readx.c semx.c modelx.c: $(CGEN_MAINT) stamp-xcpu
@true
stamp-xdecode: $(CGEN_MAIN_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32rx mach=m32rx SUFFIX=x
touch stamp-xdecode
decodex.h decodex.c: $(CGEN_MAINT) stamp-xdecode
cpux.h extractx.c semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
@true
# end-sanitize-m32rx

2
sim/m32r/configure.in
View File

@ -11,7 +11,7 @@ sim_link_links="${sim_link_links} cpu-sim.h cpu-opc.h"
SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_SCACHE(1024)
SIM_AC_OPTION_SCACHE(16384)
SIM_AC_OPTION_DEFAULT_MODEL(m32r/d)
SIM_AC_OPTION_ENVIRONMENT

505
sim/m32r/extract.c
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File diff suppressed because it is too large Load Diff

1550
sim/m32r/extractx.c Normal file
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File diff suppressed because it is too large Load Diff

965
sim/m32r/readx.c
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@ -1,965 +0,0 @@
/* Simulator instruction operand reader for m32r.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifdef DEFINE_LABELS
#undef DEFINE_LABELS
/* The labels have the case they have because the enum of insn types
is all uppercase and in the non-stdc case the fmt symbol is built
into the enum name. */
static struct {
int index;
void *label;
} labels[] = {
{ M32RX_XINSN_ILLEGAL, && case_read_READ_ILLEGAL },
{ M32RX_XINSN_ADD, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_ADD3, && case_read_READ_FMT_ADD3 },
{ M32RX_XINSN_AND, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_AND3, && case_read_READ_FMT_AND3 },
{ M32RX_XINSN_OR, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_OR3, && case_read_READ_FMT_OR3 },
{ M32RX_XINSN_XOR, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_XOR3, && case_read_READ_FMT_AND3 },
{ M32RX_XINSN_ADDI, && case_read_READ_FMT_ADDI },
{ M32RX_XINSN_ADDV, && case_read_READ_FMT_ADDV },
{ M32RX_XINSN_ADDV3, && case_read_READ_FMT_ADDV3 },
{ M32RX_XINSN_ADDX, && case_read_READ_FMT_ADDX },
{ M32RX_XINSN_BC8, && case_read_READ_FMT_BC8 },
{ M32RX_XINSN_BC24, && case_read_READ_FMT_BC24 },
{ M32RX_XINSN_BEQ, && case_read_READ_FMT_BEQ },
{ M32RX_XINSN_BEQZ, && case_read_READ_FMT_BEQZ },
{ M32RX_XINSN_BGEZ, && case_read_READ_FMT_BEQZ },
{ M32RX_XINSN_BGTZ, && case_read_READ_FMT_BEQZ },
{ M32RX_XINSN_BLEZ, && case_read_READ_FMT_BEQZ },
{ M32RX_XINSN_BLTZ, && case_read_READ_FMT_BEQZ },
{ M32RX_XINSN_BNEZ, && case_read_READ_FMT_BEQZ },
{ M32RX_XINSN_BL8, && case_read_READ_FMT_BL8 },
{ M32RX_XINSN_BL24, && case_read_READ_FMT_BL24 },
{ M32RX_XINSN_BCL8, && case_read_READ_FMT_BCL8 },
{ M32RX_XINSN_BCL24, && case_read_READ_FMT_BCL24 },
{ M32RX_XINSN_BNC8, && case_read_READ_FMT_BC8 },
{ M32RX_XINSN_BNC24, && case_read_READ_FMT_BC24 },
{ M32RX_XINSN_BNE, && case_read_READ_FMT_BEQ },
{ M32RX_XINSN_BRA8, && case_read_READ_FMT_BRA8 },
{ M32RX_XINSN_BRA24, && case_read_READ_FMT_BRA24 },
{ M32RX_XINSN_BNCL8, && case_read_READ_FMT_BCL8 },
{ M32RX_XINSN_BNCL24, && case_read_READ_FMT_BCL24 },
{ M32RX_XINSN_CMP, && case_read_READ_FMT_CMP },
{ M32RX_XINSN_CMPI, && case_read_READ_FMT_CMPI },
{ M32RX_XINSN_CMPU, && case_read_READ_FMT_CMP },
{ M32RX_XINSN_CMPUI, && case_read_READ_FMT_CMPI },
{ M32RX_XINSN_CMPEQ, && case_read_READ_FMT_CMP },
{ M32RX_XINSN_CMPZ, && case_read_READ_FMT_CMPZ },
{ M32RX_XINSN_DIV, && case_read_READ_FMT_DIV },
{ M32RX_XINSN_DIVU, && case_read_READ_FMT_DIV },
{ M32RX_XINSN_REM, && case_read_READ_FMT_DIV },
{ M32RX_XINSN_REMU, && case_read_READ_FMT_DIV },
{ M32RX_XINSN_DIVH, && case_read_READ_FMT_DIV },
{ M32RX_XINSN_JC, && case_read_READ_FMT_JC },
{ M32RX_XINSN_JNC, && case_read_READ_FMT_JC },
{ M32RX_XINSN_JL, && case_read_READ_FMT_JL },
{ M32RX_XINSN_JMP, && case_read_READ_FMT_JMP },
{ M32RX_XINSN_LD, && case_read_READ_FMT_LD },
{ M32RX_XINSN_LD_D, && case_read_READ_FMT_LD_D },
{ M32RX_XINSN_LDB, && case_read_READ_FMT_LDB },
{ M32RX_XINSN_LDB_D, && case_read_READ_FMT_LDB_D },
{ M32RX_XINSN_LDH, && case_read_READ_FMT_LDH },
{ M32RX_XINSN_LDH_D, && case_read_READ_FMT_LDH_D },
{ M32RX_XINSN_LDUB, && case_read_READ_FMT_LDB },
{ M32RX_XINSN_LDUB_D, && case_read_READ_FMT_LDB_D },
{ M32RX_XINSN_LDUH, && case_read_READ_FMT_LDH },
{ M32RX_XINSN_LDUH_D, && case_read_READ_FMT_LDH_D },
{ M32RX_XINSN_LD_PLUS, && case_read_READ_FMT_LD_PLUS },
{ M32RX_XINSN_LD24, && case_read_READ_FMT_LD24 },
{ M32RX_XINSN_LDI8, && case_read_READ_FMT_LDI8 },
{ M32RX_XINSN_LDI16, && case_read_READ_FMT_LDI16 },
{ M32RX_XINSN_LOCK, && case_read_READ_FMT_LOCK },
{ M32RX_XINSN_MACHI_A, && case_read_READ_FMT_MACHI_A },
{ M32RX_XINSN_MACLO_A, && case_read_READ_FMT_MACHI_A },
{ M32RX_XINSN_MACWHI_A, && case_read_READ_FMT_MACHI_A },
{ M32RX_XINSN_MACWLO_A, && case_read_READ_FMT_MACHI_A },
{ M32RX_XINSN_MUL, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_MULHI_A, && case_read_READ_FMT_MULHI_A },
{ M32RX_XINSN_MULLO_A, && case_read_READ_FMT_MULHI_A },
{ M32RX_XINSN_MULWHI_A, && case_read_READ_FMT_MULHI_A },
{ M32RX_XINSN_MULWLO_A, && case_read_READ_FMT_MULHI_A },
{ M32RX_XINSN_MV, && case_read_READ_FMT_MV },
{ M32RX_XINSN_MVFACHI_A, && case_read_READ_FMT_MVFACHI_A },
{ M32RX_XINSN_MVFACLO_A, && case_read_READ_FMT_MVFACHI_A },
{ M32RX_XINSN_MVFACMI_A, && case_read_READ_FMT_MVFACHI_A },
{ M32RX_XINSN_MVFC, && case_read_READ_FMT_MVFC },
{ M32RX_XINSN_MVTACHI_A, && case_read_READ_FMT_MVTACHI_A },
{ M32RX_XINSN_MVTACLO_A, && case_read_READ_FMT_MVTACHI_A },
{ M32RX_XINSN_MVTC, && case_read_READ_FMT_MVTC },
{ M32RX_XINSN_NEG, && case_read_READ_FMT_MV },
{ M32RX_XINSN_NOP, && case_read_READ_FMT_NOP },
{ M32RX_XINSN_NOT, && case_read_READ_FMT_MV },
{ M32RX_XINSN_RAC_DSI, && case_read_READ_FMT_RAC_DSI },
{ M32RX_XINSN_RACH_DSI, && case_read_READ_FMT_RAC_DSI },
{ M32RX_XINSN_RTE, && case_read_READ_FMT_RTE },
{ M32RX_XINSN_SETH, && case_read_READ_FMT_SETH },
{ M32RX_XINSN_SLL, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_SLL3, && case_read_READ_FMT_SLL3 },
{ M32RX_XINSN_SLLI, && case_read_READ_FMT_SLLI },
{ M32RX_XINSN_SRA, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_SRA3, && case_read_READ_FMT_SLL3 },
{ M32RX_XINSN_SRAI, && case_read_READ_FMT_SLLI },
{ M32RX_XINSN_SRL, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_SRL3, && case_read_READ_FMT_SLL3 },
{ M32RX_XINSN_SRLI, && case_read_READ_FMT_SLLI },
{ M32RX_XINSN_ST, && case_read_READ_FMT_ST },
{ M32RX_XINSN_ST_D, && case_read_READ_FMT_ST_D },
{ M32RX_XINSN_STB, && case_read_READ_FMT_STB },
{ M32RX_XINSN_STB_D, && case_read_READ_FMT_STB_D },
{ M32RX_XINSN_STH, && case_read_READ_FMT_STH },
{ M32RX_XINSN_STH_D, && case_read_READ_FMT_STH_D },
{ M32RX_XINSN_ST_PLUS, && case_read_READ_FMT_ST_PLUS },
{ M32RX_XINSN_ST_MINUS, && case_read_READ_FMT_ST_PLUS },
{ M32RX_XINSN_SUB, && case_read_READ_FMT_ADD },
{ M32RX_XINSN_SUBV, && case_read_READ_FMT_ADDV },
{ M32RX_XINSN_SUBX, && case_read_READ_FMT_ADDX },
{ M32RX_XINSN_TRAP, && case_read_READ_FMT_TRAP },
{ M32RX_XINSN_UNLOCK, && case_read_READ_FMT_UNLOCK },
{ M32RX_XINSN_SATB, && case_read_READ_FMT_SATB },
{ M32RX_XINSN_SATH, && case_read_READ_FMT_SATB },
{ M32RX_XINSN_SAT, && case_read_READ_FMT_SAT },
{ M32RX_XINSN_PCMPBZ, && case_read_READ_FMT_CMPZ },
{ M32RX_XINSN_SADD, && case_read_READ_FMT_SADD },
{ M32RX_XINSN_MACWU1, && case_read_READ_FMT_MACWU1 },
{ M32RX_XINSN_MSBLO, && case_read_READ_FMT_MSBLO },
{ M32RX_XINSN_MULWU1, && case_read_READ_FMT_MULWU1 },
{ M32RX_XINSN_MACLH1, && case_read_READ_FMT_MACWU1 },
{ M32RX_XINSN_SC, && case_read_READ_FMT_SC },
{ M32RX_XINSN_SNC, && case_read_READ_FMT_SC },
{ 0, 0 }
};
int i;
for (i = 0; labels[i].label != 0; ++i)
CPU_IDESC (current_cpu) [labels[i].index].read = labels[i].label;
#endif /* DEFINE_LABELS */
#ifdef DEFINE_SWITCH
#undef DEFINE_SWITCH
{
SWITCH (read, decode->read)
{
CASE (read, READ_ILLEGAL) :
{
sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
}
BREAK (read);
CASE (read, READ_FMT_ADD) : /* e.g. add $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_add.f
EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADD_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (dr) = CPU (h_gr[f_r1]);
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ADD3) : /* e.g. add3 $dr,$sr,$hash$slo16 */
{
#define OPRND(f) par_exec->operands.fmt_add3.f
EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_ADD3_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_AND3) : /* e.g. and3 $dr,$sr,$uimm16 */
{
#define OPRND(f) par_exec->operands.fmt_and3.f
EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_AND3_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (uimm16) = f_uimm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_OR3) : /* e.g. or3 $dr,$sr,$hash$ulo16 */
{
#define OPRND(f) par_exec->operands.fmt_or3.f
EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_OR3_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (ulo16) = f_uimm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ADDI) : /* e.g. addi $dr,$simm8 */
{
#define OPRND(f) par_exec->operands.fmt_addi.f
EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
EXTRACT_FMT_ADDI_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (dr) = CPU (h_gr[f_r1]);
OPRND (simm8) = f_simm8;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ADDV) : /* e.g. addv $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_addv.f
EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADDV_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (dr) = CPU (h_gr[f_r1]);
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ADDV3) : /* e.g. addv3 $dr,$sr,$simm16 */
{
#define OPRND(f) par_exec->operands.fmt_addv3.f
EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_ADDV3_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (simm16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ADDX) : /* e.g. addx $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_addx.f
EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ADDX_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (dr) = CPU (h_gr[f_r1]);
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (condbit) = CPU (h_cond);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BC8) : /* e.g. bc.s $disp8 */
{
#define OPRND(f) par_exec->operands.fmt_bc8.f
EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BC8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BC24) : /* e.g. bc.l $disp24 */
{
#define OPRND(f) par_exec->operands.fmt_bc24.f
EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BC24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BEQ) : /* e.g. beq $src1,$src2,$disp16 */
{
#define OPRND(f) par_exec->operands.fmt_beq.f
EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQ_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (disp16) = f_disp16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BEQZ) : /* e.g. beqz $src2,$disp16 */
{
#define OPRND(f) par_exec->operands.fmt_beqz.f
EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
EXTRACT_FMT_BEQZ_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (disp16) = f_disp16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BL8) : /* e.g. bl.s $disp8 */
{
#define OPRND(f) par_exec->operands.fmt_bl8.f
EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BL8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (pc) = CPU (h_pc);
OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BL24) : /* e.g. bl.l $disp24 */
{
#define OPRND(f) par_exec->operands.fmt_bl24.f
EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BL24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (pc) = CPU (h_pc);
OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BCL8) : /* e.g. bcl.s $disp8 */
{
#define OPRND(f) par_exec->operands.fmt_bcl8.f
EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BCL8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (pc) = CPU (h_pc);
OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BCL24) : /* e.g. bcl.l $disp24 */
{
#define OPRND(f) par_exec->operands.fmt_bcl24.f
EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BCL24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (pc) = CPU (h_pc);
OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BRA8) : /* e.g. bra.s $disp8 */
{
#define OPRND(f) par_exec->operands.fmt_bra8.f
EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
EXTRACT_FMT_BRA8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (disp8) = f_disp8;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_BRA24) : /* e.g. bra.l $disp24 */
{
#define OPRND(f) par_exec->operands.fmt_bra24.f
EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
EXTRACT_FMT_BRA24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (disp24) = f_disp24;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_CMP) : /* e.g. cmp $src1,$src2 */
{
#define OPRND(f) par_exec->operands.fmt_cmp.f
EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMP_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_CMPI) : /* e.g. cmpi $src2,$simm16 */
{
#define OPRND(f) par_exec->operands.fmt_cmpi.f
EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_CMPI_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (simm16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_CMPZ) : /* e.g. cmpz $src2 */
{
#define OPRND(f) par_exec->operands.fmt_cmpz.f
EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_CMPZ_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_DIV) : /* e.g. div $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_div.f
EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_DIV_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (dr) = CPU (h_gr[f_r1]);
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_JC) : /* e.g. jc $sr */
{
#define OPRND(f) par_exec->operands.fmt_jc.f
EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JC_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_JL) : /* e.g. jl $sr */
{
#define OPRND(f) par_exec->operands.fmt_jl.f
EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JL_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (pc) = CPU (h_pc);
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_JMP) : /* e.g. jmp $sr */
{
#define OPRND(f) par_exec->operands.fmt_jmp.f
EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_JMP_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LD) : /* e.g. ld $dr,@$sr */
{
#define OPRND(f) par_exec->operands.fmt_ld.f
EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LD_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LD_D) : /* e.g. ld $dr,@($slo16,$sr) */
{
#define OPRND(f) par_exec->operands.fmt_ld_d.f
EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LD_D_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_add__VM_sr_slo16) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LDB) : /* e.g. ldb $dr,@$sr */
{
#define OPRND(f) par_exec->operands.fmt_ldb.f
EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LDB_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_sr) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LDB_D) : /* e.g. ldb $dr,@($slo16,$sr) */
{
#define OPRND(f) par_exec->operands.fmt_ldb_d.f
EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDB_D_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_add__VM_sr_slo16) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LDH) : /* e.g. ldh $dr,@$sr */
{
#define OPRND(f) par_exec->operands.fmt_ldh.f
EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LDH_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_sr) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LDH_D) : /* e.g. ldh $dr,@($slo16,$sr) */
{
#define OPRND(f) par_exec->operands.fmt_ldh_d.f
EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDH_D_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_add__VM_sr_slo16) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LD_PLUS) : /* e.g. ld $dr,@$sr+ */
{
#define OPRND(f) par_exec->operands.fmt_ld_plus.f
EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LD_PLUS_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LD24) : /* e.g. ld24 $dr,$uimm24 */
{
#define OPRND(f) par_exec->operands.fmt_ld24.f
EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
EXTRACT_FMT_LD24_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (uimm24) = f_uimm24;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LDI8) : /* e.g. ldi8 $dr,$simm8 */
{
#define OPRND(f) par_exec->operands.fmt_ldi8.f
EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
EXTRACT_FMT_LDI8_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (simm8) = f_simm8;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LDI16) : /* e.g. ldi16 $dr,$hash$slo16 */
{
#define OPRND(f) par_exec->operands.fmt_ldi16.f
EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_LDI16_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (slo16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_LOCK) : /* e.g. lock $dr,@$sr */
{
#define OPRND(f) par_exec->operands.fmt_lock.f
EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_LOCK_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
{
#define OPRND(f) par_exec->operands.fmt_machi_a.f
EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
EXTRACT_FMT_MACHI_A_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc);
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
{
#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
EXTRACT_FMT_MULHI_A_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MV) : /* e.g. mv $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_mv.f
EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MV_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
{
#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVFACHI_A_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MVFC) : /* e.g. mvfc $dr,$scr */
{
#define OPRND(f) par_exec->operands.fmt_mvfc.f
EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MVFC_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
{
#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
EXTRACT_FMT_MVTACHI_A_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MVTC) : /* e.g. mvtc $sr,$dcr */
{
#define OPRND(f) par_exec->operands.fmt_mvtc.f
EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MVTC_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_NOP) : /* e.g. nop */
{
#define OPRND(f) par_exec->operands.fmt_nop.f
EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_NOP_CODE
/* Fetch the input operands for the semantic handler. */
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_RAC_DSI) : /* e.g. rac $accd,$accs,$imm1 */
{
#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
EXTRACT_FMT_RAC_DSI_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
OPRND (imm1) = f_imm1;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_RTE) : /* e.g. rte */
{
#define OPRND(f) par_exec->operands.fmt_rte.f
EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_RTE_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_cr_6) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 6));
OPRND (h_cr_14) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 14));
OPRND (h_bpsw_0) = CPU (h_bpsw);
OPRND (h_bbpsw_0) = CPU (h_bbpsw);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SETH) : /* e.g. seth $dr,$hash$hi16 */
{
#define OPRND(f) par_exec->operands.fmt_seth.f
EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
EXTRACT_FMT_SETH_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (hi16) = f_hi16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SLL3) : /* e.g. sll3 $dr,$sr,$simm16 */
{
#define OPRND(f) par_exec->operands.fmt_sll3.f
EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_SLL3_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
OPRND (simm16) = f_simm16;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SLLI) : /* e.g. slli $dr,$uimm5 */
{
#define OPRND(f) par_exec->operands.fmt_slli.f
EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
EXTRACT_FMT_SLLI_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (dr) = CPU (h_gr[f_r1]);
OPRND (uimm5) = f_uimm5;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ST) : /* e.g. st $src1,@$src2 */
{
#define OPRND(f) par_exec->operands.fmt_st.f
EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ST_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
{
#define OPRND(f) par_exec->operands.fmt_st_d.f
EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_ST_D_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_STB) : /* e.g. stb $src1,@$src2 */
{
#define OPRND(f) par_exec->operands.fmt_stb.f
EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_STB_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_STB_D) : /* e.g. stb $src1,@($slo16,$src2) */
{
#define OPRND(f) par_exec->operands.fmt_stb_d.f
EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_STB_D_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_STH) : /* e.g. sth $src1,@$src2 */
{
#define OPRND(f) par_exec->operands.fmt_sth.f
EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_STH_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_STH_D) : /* e.g. sth $src1,@($slo16,$src2) */
{
#define OPRND(f) par_exec->operands.fmt_sth_d.f
EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
EXTRACT_FMT_STH_D_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (slo16) = f_simm16;
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_ST_PLUS) : /* e.g. st $src1,@+$src2 */
{
#define OPRND(f) par_exec->operands.fmt_st_plus.f
EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_ST_PLUS_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_TRAP) : /* e.g. trap $uimm4 */
{
#define OPRND(f) par_exec->operands.fmt_trap.f
EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
EXTRACT_FMT_TRAP_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_cr_6) = m32rx_h_cr_get (current_cpu, ((HOSTUINT) 6));
OPRND (h_bpsw_0) = CPU (h_bpsw);
OPRND (h_psw_0) = m32rx_h_psw_get (current_cpu);
OPRND (pc) = CPU (h_pc);
OPRND (uimm4) = f_uimm4;
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_UNLOCK) : /* e.g. unlock $src1,@$src2 */
{
#define OPRND(f) par_exec->operands.fmt_unlock.f
EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_UNLOCK_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_lock_0) = CPU (h_lock);
OPRND (src2) = CPU (h_gr[f_r2]);
OPRND (src1) = CPU (h_gr[f_r1]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SATB) : /* e.g. satb $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_satb.f
EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_SATB_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SAT) : /* e.g. sat $dr,$sr */
{
#define OPRND(f) par_exec->operands.fmt_sat.f
EXTRACT_FMT_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
EXTRACT_FMT_SAT_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
OPRND (sr) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SADD) : /* e.g. sadd */
{
#define OPRND(f) par_exec->operands.fmt_sadd.f
EXTRACT_FMT_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_SADD_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, ((HOSTUINT) 1));
OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, ((HOSTUINT) 0));
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MACWU1) : /* e.g. macwu1 $src1,$src2 */
{
#define OPRND(f) par_exec->operands.fmt_macwu1.f
EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MACWU1_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, ((HOSTUINT) 1));
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MSBLO) : /* e.g. msblo $src1,$src2 */
{
#define OPRND(f) par_exec->operands.fmt_msblo.f
EXTRACT_FMT_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MSBLO_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (accum) = m32rx_h_accum_get (current_cpu);
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_MULWU1) : /* e.g. mulwu1 $src1,$src2 */
{
#define OPRND(f) par_exec->operands.fmt_mulwu1.f
EXTRACT_FMT_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_MULWU1_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (src1) = CPU (h_gr[f_r1]);
OPRND (src2) = CPU (h_gr[f_r2]);
#undef OPRND
}
BREAK (read);
CASE (read, READ_FMT_SC) : /* e.g. sc */
{
#define OPRND(f) par_exec->operands.fmt_sc.f
EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
EXTRACT_FMT_SC_CODE
/* Fetch the input operands for the semantic handler. */
OPRND (condbit) = CPU (h_cond);
#undef OPRND
}
BREAK (read);
}
ENDSWITCH (read) /* End of read switch. */
}
#endif /* DEFINE_SWITCH */

4299
sim/m32r/semx.c
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