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power9 mfupmc/mtupmc

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PR 23419
	* ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
	opcode variants for mtspr/mfspr encodings.
This commit is contained in:
Alan Modra 2018-07-23 12:59:23 +09:30
parent cf4088a92f
commit bb71536f28
2 changed files with 24 additions and 0 deletions
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6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2018-07-23 Alan Modra <amodra@gmail.com>
PR 23419
* ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
opcode variants for mtspr/mfspr encodings.
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
Maciej W. Rozycki <macro@mips.com>

18
opcodes/ppc-opc.c
View File

@ -5900,6 +5900,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
{"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}},
{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}},
{"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}},
{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}},
{"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}},
{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}},
{"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}},
{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}},
{"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}},
{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}},
{"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}},
{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}},
{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
@ -6243,6 +6255,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
{"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}},
{"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}},
{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},