[arm] Check for neon and condition in vcvt.f16.f32
VCVT between f16 and f32 is an Advanced SIMD instruction.
Not all the VCVT alternatives need neon, hence the check for neon is in
the encode function.
The check on neon for VCVT.f16.f32 (and vice versa) is missing.
vshcmd: > echo 'vcvt.f16.f32 d1, q1' | gas/as-new -mfpu=vfpxd -march=armv8.5-a -
testdir [15:59:10] $
Also, the handling of the condition code behaves differently to other
SIMD instructions -- no error message is produced when assembling an
instruction with a condition code suffix despite the arm encoding not
allowing a condition code. (n.b. the actual binary produced is
independent of the suffix).
The instruction should be treated similarly to VSUBL that has the same
caveat of "must be unconditional" describing the {<c>} symbol. vcvt
half-precision to single precision found in F6.1.58 in the ARM
Architecture Reference Manual issue C.a, vsubl found in F6.1.240 in
the ARM Architecture Reference Manual issue C.a
2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition
codes to half-precision conversion.
* testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed.
* testsuite/gas/arm/neon-cond-bad.l: Likewise.
* testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT
block.
* testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon.
* testsuite/gas/arm/vfp-bad.s: Likewise.
This commit is contained in:
Matthew Malcomson
Richard Earnshaw
parent
0632eeea6e
commit
bc52d49c1d
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@ -1,3 +1,14 @@
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2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition
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codes to half-precision conversion.
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* testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed.
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* testsuite/gas/arm/neon-cond-bad.l: Likewise.
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* testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT
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block.
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* testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon.
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* testsuite/gas/arm/vfp-bad.s: Likewise.
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2018-11-06 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (insn_validate): Don't ignore mask in
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@ -15914,6 +15914,8 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
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/* Half-precision conversions for Advanced SIMD -- neon. */
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case NS_QD:
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case NS_DQ:
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if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
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return;
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if ((rs == NS_DQ)
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&& (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
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@ -30,6 +30,10 @@ func:
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dyadic_eq vadd
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dyadic_eq vsub
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itblock 2 eq
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vcvteq.f16.f32 d1, q1
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vcvteq.f32.f16 q1, d1
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.macro monadic_eq op eq="eq" f32=".f32"
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itblock 2 eq
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\op\eq\f32 d0,d1
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@ -13,17 +13,19 @@
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[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2'
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[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
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[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2'
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[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
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[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1'
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[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
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[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1'
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[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
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[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1'
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[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'
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[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1'
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[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'
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[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1'
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[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1'
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[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1'
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[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]'
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[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]'
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[^:]*:34: Error: instruction cannot be conditional -- `vcvteq\.f16\.f32 d1,q1'
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[^:]*:35: Error: instruction cannot be conditional -- `vcvteq\.f32\.f16 q1,d1'
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[^:]*:43: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
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[^:]*:43: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1'
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[^:]*:44: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
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[^:]*:44: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1'
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[^:]*:52: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
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[^:]*:52: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1'
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[^:]*:53: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'
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[^:]*:53: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1'
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[^:]*:54: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'
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[^:]*:54: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1'
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[^:]*:55: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1'
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[^:]*:55: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1'
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[^:]*:60: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]'
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[^:]*:61: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]'
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@ -31,6 +31,9 @@ Disassembly of section \.text:
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0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2
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0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q2
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0[0-9a-f]+ <[^>]+> bf04 itt eq
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0[0-9a-f]+ <[^>]+> ffb6 1602 vcvteq.f16.f32 d1, q1
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0[0-9a-f]+ <[^>]+> ffb6 2701 vcvteq.f32.f16 q1, d1
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0[0-9a-f]+ <[^>]+> bf04 itt eq
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0[0-9a-f]+ <[^>]+> ffb9 0701 vabseq\.f32 d0, d1
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0[0-9a-f]+ <[^>]+> ffb9 0742 vabseq\.f32 q0, q1
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0[0-9a-f]+ <[^>]+> bf04 itt eq
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@ -9,3 +9,5 @@
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[^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!'
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[^:]*:12: Error: selected FPU does not support instruction -- `vmrs r0,MVFR2'
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[^:]*:13: Error: selected FPU does not support instruction -- `vmsr MVFR2,r2'
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[^:]*:14: Error: selected FPU does not support instruction -- `vcvt.f16.f32 d1,q1'
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[^:]*:15: Error: selected FPU does not support instruction -- `vcvt.f32.f16 q1,d1'
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@ -11,3 +11,5 @@ entry:
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flds s0, [r0, #-8]!
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vmrs r0, MVFR2
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vmsr MVFR2, r2
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vcvt.f16.f32 d1, q1
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vcvt.f32.f16 q1, d1
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