include/opcode/
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com> * mips.h (INSN_TRAP): Rename to... (INSN_NO_DELAY_SLOT): ... this. (INSN_SYNC): Remove macro. gas/ 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com> * config/tc-mips.c (can_swap_branch_p): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. Remove the check for INSN_SYNC as well as explicit checks for ERET and DERET when scheduling branch delay slots. opcodes/ 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com> * mips-opc.c (NODS): New macro. (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. (DSP_VOLA): Likewise. (mips_builtin_opcodes): Add NODS annotation to "deret" and "eret". Replace INSN_SYNC with NODS throughout. Use NODS in place of TRAP for "wait", "waiti" and "yield". * mips16-opc.c (NODS): New macro. (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT. (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc", "restore" and "save".
This commit is contained in:
Richard Sandiford
parent
bbc40cf228
commit
bcd530a713
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@ -1,3 +1,10 @@
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2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (can_swap_branch_p): Adjust for the rename of
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INSN_TRAP to INSN_NO_DELAY_SLOT. Remove the check for INSN_SYNC
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as well as explicit checks for ERET and DERET when scheduling
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branch delay slots.
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2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add k1om.
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@ -3148,21 +3148,13 @@ can_swap_branch_p (struct mips_cl_insn *ip)
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&& history[0].frag->fr_type == rs_machine_dependent)
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return FALSE;
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/* We do not swap with a trap instruction, since it complicates trap
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handlers to have the trap instruction be in a delay slot. */
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/* We do not swap with instructions that cannot architecturally
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be placed in a branch delay slot, such as SYNC or ERET. We
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also refrain from swapping with a trap instruction, since it
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complicates trap handlers to have the trap instruction be in
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a delay slot. */
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prev_pinfo = history[0].insn_mo->pinfo;
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if (prev_pinfo & INSN_TRAP)
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return FALSE;
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/* If the previous instruction is a sync, sync.l, or sync.p, we can
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not swap. */
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if (prev_pinfo & INSN_SYNC)
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return FALSE;
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/* If the previous instruction is an ERET or DERET, avoid the swap. */
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if (history[0].insn_opcode == INSN_ERET)
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return FALSE;
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if (history[0].insn_opcode == INSN_DERET)
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if (prev_pinfo & INSN_NO_DELAY_SLOT)
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return FALSE;
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/* Check for conflicts between the branch and the instructions
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@ -1,3 +1,9 @@
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2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (INSN_TRAP): Rename to...
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(INSN_NO_DELAY_SLOT): ... this.
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(INSN_SYNC): Remove macro.
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2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
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* avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
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@ -489,8 +489,9 @@ struct mips_opcode
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#define INSN_WRITE_HI 0x01000000
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/* Modifies the LO register. */
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#define INSN_WRITE_LO 0x02000000
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/* Takes a trap (easier to keep out of delay slot). */
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#define INSN_TRAP 0x04000000
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/* Not to be placed in a branch delay slot, either architecturally
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or for ease of handling (such as with instructions that take a trap). */
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#define INSN_NO_DELAY_SLOT 0x04000000
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/* Instruction stores value into memory. */
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#define INSN_STORE_MEMORY 0x08000000
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/* Instruction uses single precision floating point. */
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@ -499,8 +500,6 @@ struct mips_opcode
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#define FP_D 0x20000000
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/* Instruction is part of the tx39's integer multiply family. */
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#define INSN_MULT 0x40000000
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/* Instruction synchronize shared memory. */
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#define INSN_SYNC 0x80000000
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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@ -1,3 +1,16 @@
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2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
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* mips-opc.c (NODS): New macro.
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(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
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(DSP_VOLA): Likewise.
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(mips_builtin_opcodes): Add NODS annotation to "deret" and
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"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
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place of TRAP for "wait", "waiti" and "yield".
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* mips16-opc.c (NODS): New macro.
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(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
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(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
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"restore" and "save".
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2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
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* configure.in: Handle bfd_k1om_arch.
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@ -37,7 +37,8 @@
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#define COD INSN_COPROC_MOVE_DELAY
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#define CLD INSN_COPROC_MEMORY_DELAY
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#define CBL INSN_COND_BRANCH_LIKELY
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#define TRAP INSN_TRAP
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#define NODS INSN_NO_DELAY_SLOT
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#define TRAP INSN_NO_DELAY_SLOT
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#define SM INSN_STORE_MEMORY
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#define WR_d INSN_WRITE_GPR_D
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@ -150,13 +151,14 @@
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to track dependencies of these fields.
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However, "bposge32" is a branch instruction that depends on the "pos"
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field. In order to make sure that GAS does not reorder DSP instructions
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that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
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attribute to those instructions that write the "pos" field. */
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that writes the "pos" field and "bposge32", we add DSP_VOLA
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(INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos"
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field. */
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#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
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#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
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#define MOD_a WR_a|RD_a
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#define DSP_VOLA INSN_TRAP
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#define DSP_VOLA INSN_NO_DELAY_SLOT
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#define D32 INSN_DSP
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#define D33 INSN_DSPR2
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#define D64 INSN_DSP64
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@ -631,7 +633,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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/* dctr and dctw are used on the r5000. */
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{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
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{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
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{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
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{"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2 },
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{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
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{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
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{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
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@ -763,7 +765,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
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{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
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{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
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{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 },
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{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
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{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
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{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
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{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
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@ -1400,19 +1402,19 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
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{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
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{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 },
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{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0, IOCT },
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{"sync_acquire", "", 0x0000044f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_mb", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_release", "", 0x0000048f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_rmb", "", 0x000004cf, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync_wmb", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, I33 },
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{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
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{"sync", "1", 0x0000000f, 0xfffff83f, INSN_SYNC, 0, I32 },
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{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
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{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
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{"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT },
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{"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT },
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{"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT },
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{"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT },
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{"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33 },
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{"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33 },
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{"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33 },
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{"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33 },
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{"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33 },
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{"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1 },
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{"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32 },
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{"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2 },
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{"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2 },
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{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
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{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
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{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
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@ -1481,9 +1483,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
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{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
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{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
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{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3_32 },
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{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
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{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
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{"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32 },
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{"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 },
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{"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 },
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{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
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{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
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{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
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@ -1496,8 +1498,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
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{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
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{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
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{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
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{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
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{"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, MT32 },
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{"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, MT32 },
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/* User Defined Instruction. */
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{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
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@ -58,7 +58,8 @@
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#define RD_HI INSN_READ_HI
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#define RD_LO INSN_READ_LO
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#define TRAP INSN_TRAP
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#define NODS INSN_NO_DELAY_SLOT
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#define TRAP INSN_NO_DELAY_SLOT
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#define I1 INSN_ISA1
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#define I3 INSN_ISA3
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@ -174,10 +175,10 @@ const struct mips_opcode mips16_opcodes[] =
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/* MIPS16e compact branches. We keep them near the ordinary branches
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so that we easily find them when converting a normal branch to a
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compact one. */
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{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|TRAP, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|TRAP, 0, I32 },
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{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32 },
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{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 },
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{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 },
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{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
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@ -234,8 +235,8 @@ const struct mips_opcode mips16_opcodes[] =
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{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
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{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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/* MIPS16e additions */
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{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 },
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{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 },
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{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32 },
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{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32 },
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{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
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{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 },
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{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 },
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