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include/opcode/ 

2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips.h (INSN_TRAP): Rename to...
	(INSN_NO_DELAY_SLOT): ... this.
	(INSN_SYNC): Remove macro.

gas/
2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* config/tc-mips.c (can_swap_branch_p): Adjust for the rename of
	INSN_TRAP to INSN_NO_DELAY_SLOT.  Remove the check for INSN_SYNC
	as well as explicit checks for ERET and DERET when scheduling
	branch delay slots.

opcodes/
2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (NODS): New macro.
	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	(DSP_VOLA): Likewise.
	(mips_builtin_opcodes): Add NODS annotation to "deret" and
	"eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
	place of TRAP for "wait", "waiti" and "yield".
	* mips16-opc.c (NODS): New macro.
	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	(mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
	"restore" and "save".
This commit is contained in:
Richard Sandiford 2011-07-24 14:04:51 +00:00
parent bbc40cf228
commit bcd530a713
7 changed files with 69 additions and 49 deletions
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7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.c (can_swap_branch_p): Adjust for the rename of
INSN_TRAP to INSN_NO_DELAY_SLOT. Remove the check for INSN_SYNC
as well as explicit checks for ERET and DERET when scheduling
branch delay slots.
2011-07-22 H.J. Lu <hongjiu.lu@intel.com> 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Add k1om. * config/tc-i386.c (cpu_arch): Add k1om.

20
gas/config/tc-mips.c
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@ -3148,21 +3148,13 @@ can_swap_branch_p (struct mips_cl_insn *ip)
&& history[0].frag->fr_type == rs_machine_dependent) && history[0].frag->fr_type == rs_machine_dependent)
return FALSE; return FALSE;
/* We do not swap with a trap instruction, since it complicates trap /* We do not swap with instructions that cannot architecturally
handlers to have the trap instruction be in a delay slot. */ be placed in a branch delay slot, such as SYNC or ERET. We
also refrain from swapping with a trap instruction, since it
complicates trap handlers to have the trap instruction be in
a delay slot. */
prev_pinfo = history[0].insn_mo->pinfo; prev_pinfo = history[0].insn_mo->pinfo;
if (prev_pinfo & INSN_TRAP) if (prev_pinfo & INSN_NO_DELAY_SLOT)
return FALSE;
/* If the previous instruction is a sync, sync.l, or sync.p, we can
not swap. */
if (prev_pinfo & INSN_SYNC)
return FALSE;
/* If the previous instruction is an ERET or DERET, avoid the swap. */
if (history[0].insn_opcode == INSN_ERET)
return FALSE;
if (history[0].insn_opcode == INSN_DERET)
return FALSE; return FALSE;
/* Check for conflicts between the branch and the instructions /* Check for conflicts between the branch and the instructions

6
include/opcode/ChangeLog
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@ -1,3 +1,9 @@
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (INSN_TRAP): Rename to...
(INSN_NO_DELAY_SLOT): ... this.
(INSN_SYNC): Remove macro.
2011-07-01 Eric B. Weddington <eric.weddington@atmel.com> 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
* avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually

7
include/opcode/mips.h
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@ -489,8 +489,9 @@ struct mips_opcode
#define INSN_WRITE_HI 0x01000000 #define INSN_WRITE_HI 0x01000000
/* Modifies the LO register. */ /* Modifies the LO register. */
#define INSN_WRITE_LO 0x02000000 #define INSN_WRITE_LO 0x02000000
/* Takes a trap (easier to keep out of delay slot). */ /* Not to be placed in a branch delay slot, either architecturally
#define INSN_TRAP 0x04000000 or for ease of handling (such as with instructions that take a trap). */
#define INSN_NO_DELAY_SLOT 0x04000000
/* Instruction stores value into memory. */ /* Instruction stores value into memory. */
#define INSN_STORE_MEMORY 0x08000000 #define INSN_STORE_MEMORY 0x08000000
/* Instruction uses single precision floating point. */ /* Instruction uses single precision floating point. */
@ -499,8 +500,6 @@ struct mips_opcode
#define FP_D 0x20000000 #define FP_D 0x20000000
/* Instruction is part of the tx39's integer multiply family. */ /* Instruction is part of the tx39's integer multiply family. */
#define INSN_MULT 0x40000000 #define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
/* Instruction is actually a macro. It should be ignored by the /* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */ disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff #define INSN_MACRO 0xffffffff

13
opcodes/ChangeLog
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@ -1,3 +1,16 @@
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (NODS): New macro.
(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
(DSP_VOLA): Likewise.
(mips_builtin_opcodes): Add NODS annotation to "deret" and
"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
place of TRAP for "wait", "waiti" and "yield".
* mips16-opc.c (NODS): New macro.
(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
"restore" and "save".
2011-07-22 H.J. Lu <hongjiu.lu@intel.com> 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
* configure.in: Handle bfd_k1om_arch. * configure.in: Handle bfd_k1om_arch.

50
opcodes/mips-opc.c
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@ -37,7 +37,8 @@
#define COD INSN_COPROC_MOVE_DELAY #define COD INSN_COPROC_MOVE_DELAY
#define CLD INSN_COPROC_MEMORY_DELAY #define CLD INSN_COPROC_MEMORY_DELAY
#define CBL INSN_COND_BRANCH_LIKELY #define CBL INSN_COND_BRANCH_LIKELY
#define TRAP INSN_TRAP #define NODS INSN_NO_DELAY_SLOT
#define TRAP INSN_NO_DELAY_SLOT
#define SM INSN_STORE_MEMORY #define SM INSN_STORE_MEMORY
#define WR_d INSN_WRITE_GPR_D #define WR_d INSN_WRITE_GPR_D
@ -150,13 +151,14 @@
to track dependencies of these fields. to track dependencies of these fields.
However, "bposge32" is a branch instruction that depends on the "pos" However, "bposge32" is a branch instruction that depends on the "pos"
field. In order to make sure that GAS does not reorder DSP instructions field. In order to make sure that GAS does not reorder DSP instructions
that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) that writes the "pos" field and "bposge32", we add DSP_VOLA
attribute to those instructions that write the "pos" field. */ (INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos"
field. */
#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
#define MOD_a WR_a|RD_a #define MOD_a WR_a|RD_a
#define DSP_VOLA INSN_TRAP #define DSP_VOLA INSN_NO_DELAY_SLOT
#define D32 INSN_DSP #define D32 INSN_DSP
#define D33 INSN_DSPR2 #define D33 INSN_DSPR2
#define D64 INSN_DSP64 #define D64 INSN_DSP64
@ -631,7 +633,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* dctr and dctw are used on the r5000. */ /* dctr and dctw are used on the r5000. */
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, {"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2 },
{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
@ -763,7 +765,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT}, {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 }, {"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
@ -1400,19 +1402,19 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 }, {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 },
{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0, IOCT }, {"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT },
{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0, IOCT }, {"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT },
{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, IOCT }, {"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT },
{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0, IOCT }, {"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT },
{"sync_acquire", "", 0x0000044f, 0xffffffff, INSN_SYNC, 0, I33 }, {"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33 },
{"sync_mb", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I33 }, {"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33 },
{"sync_release", "", 0x0000048f, 0xffffffff, INSN_SYNC, 0, I33 }, {"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33 },
{"sync_rmb", "", 0x000004cf, 0xffffffff, INSN_SYNC, 0, I33 }, {"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33 },
{"sync_wmb", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, I33 }, {"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33 },
{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, {"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1 },
{"sync", "1", 0x0000000f, 0xfffff83f, INSN_SYNC, 0, I32 }, {"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32 },
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, {"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2 },
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, {"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2 },
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
@ -1481,9 +1483,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3_32 }, {"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32 },
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, {"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, {"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 },
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
@ -1496,8 +1498,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, {"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, MT32 },
{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, {"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, MT32 },
/* User Defined Instruction. */ /* User Defined Instruction. */
{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },

15
opcodes/mips16-opc.c
View File

@ -58,7 +58,8 @@
#define RD_HI INSN_READ_HI #define RD_HI INSN_READ_HI
#define RD_LO INSN_READ_LO #define RD_LO INSN_READ_LO
#define TRAP INSN_TRAP #define NODS INSN_NO_DELAY_SLOT
#define TRAP INSN_NO_DELAY_SLOT
#define I1 INSN_ISA1 #define I1 INSN_ISA1
#define I3 INSN_ISA3 #define I3 INSN_ISA3
@ -174,10 +175,10 @@ const struct mips_opcode mips16_opcodes[] =
/* MIPS16e compact branches. We keep them near the ordinary branches /* MIPS16e compact branches. We keep them near the ordinary branches
so that we easily find them when converting a normal branch to a so that we easily find them when converting a normal branch to a
compact one. */ compact one. */
{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 }, {"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 }, {"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|TRAP, 0, I32 }, {"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32 },
{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|TRAP, 0, I32 }, {"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32 },
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 }, {"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 },
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 }, {"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 },
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 }, {"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
@ -234,8 +235,8 @@ const struct mips_opcode mips16_opcodes[] =
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 }, {"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, {"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
/* MIPS16e additions */ /* MIPS16e additions */
{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 }, {"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32 },
{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 }, {"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32 },
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 }, {"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 }, {"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 },
{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 }, {"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 },