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* emultempl/ppc64elf.em (ppc_add_stub_section): Align to 32 bytes.
ld/testsuite/
	* ld-powerpc/relbrlt.d: Update for stub alignment change.
	* ld-powerpc/tlsexe.g: Likewise.
	* ld-powerpc/tlsexe.r: Likewise.
	* ld-powerpc/tlsexetoc.g: Likewise.
	* ld-powerpc/tlsexetoc.r: Likewise.
	* ld-powerpc/tlsso.g: Likewise.
	* ld-powerpc/tlsso.r: Likewise.
This commit is contained in:
Alan Modra 2011-10-10 09:05:41 +00:00
parent 6501578cfe
commit bd518033e9
10 changed files with 36 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
ld/ChangeLog
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@ -1,3 +1,7 @@
2011-10-10 Alan Modra <amodra@gmail.com>
* emultempl/ppc64elf.em (ppc_add_stub_section): Align to 32 bytes.
2011-10-09 Alan Modra <amodra@gmail.com>
* emultempl/ppc64elf.em (ppc_create_output_section_statements): Add

3
ld/emultempl/ppc64elf.em
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@ -378,7 +378,8 @@ ppc_add_stub_section (const char *stub_sec_name, asection *input_section)
| SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_KEEP);
stub_sec = bfd_make_section_anyway_with_flags (stub_file->the_bfd,
stub_sec_name, flags);
if (stub_sec == NULL)
if (stub_sec == NULL
|| !bfd_set_section_alignment (stub_file->the_bfd, stub_sec, 5))
goto err_ret;
output_section = input_section->output_section;

10
ld/testsuite/ChangeLog
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@ -1,3 +1,13 @@
2011-10-10 Alan Modra <amodra@gmail.com>
* ld-powerpc/relbrlt.d: Update for stub alignment change.
* ld-powerpc/tlsexe.g: Likewise.
* ld-powerpc/tlsexe.r: Likewise.
* ld-powerpc/tlsexetoc.g: Likewise.
* ld-powerpc/tlsexetoc.r: Likewise.
* ld-powerpc/tlsso.g: Likewise.
* ld-powerpc/tlsso.r: Likewise.
2011-10-08 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13250

24
ld/testsuite/ld-powerpc/relbrlt.d
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@ -7,7 +7,7 @@
Disassembly of section \.text:
0*100000b0 <_start>:
0*100000c0 <_start>:
[0-9a-f ]*: 49 bf 00 2d bl .*
[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e003c
[0-9a-f ]*: 60 00 00 00 nop
@ -23,38 +23,38 @@ Disassembly of section \.text:
[0-9a-f ]*<.*plt_branch.*>:
[0-9a-f ]*: e9 62 80 00 ld r11,-32768\(r2\)
[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00d8
[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00e8
[0-9a-f ]*: 7d 69 03 a6 mtctr r11
[0-9a-f ]*: 4e 80 04 20 bctr
[0-9a-f ]*<.*long_branch.*>:
[0-9a-f ]*: 49 bf 00 10 b .* <far>
[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00ec
[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00fc
[0-9a-f ]*<.*plt_branch.*>:
[0-9a-f ]*: e9 62 80 08 ld r11,-32760\(r2\)
[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00e0
[0-9a-f ]*: R_PPC64_TOC16_DS \*ABS\*\+0x157f00f0
[0-9a-f ]*: 7d 69 03 a6 mtctr r11
[0-9a-f ]*: 4e 80 04 20 bctr
\.\.\.
0*137e00ec <far>:
0*137e00fc <far>:
[0-9a-f ]*: 4e 80 00 20 blr
\.\.\.
0*13bf00d0 <far2far>:
0*13bf00e0 <far2far>:
[0-9a-f ]*: 4e 80 00 20 blr
\.\.\.
0*157e00d4 <huge>:
0*157e00e4 <huge>:
[0-9a-f ]*: 4e 80 00 20 blr
Disassembly of section \.branch_lt:
0*157f00d8 <\.branch_lt>:
0*157f00e8 <\.branch_lt>:
[0-9a-f ]*: 00 00 00 00 .*
[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x13bf00d0
[0-9a-f ]*: 13 bf 00 d0 .*
[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x13bf00e0
[0-9a-f ]*: 13 bf 00 e0 .*
[0-9a-f ]*: 00 00 00 00 .*
[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x157e00d4
[0-9a-f ]*: 15 7e 00 d4 .*
[0-9a-f ]*: R_PPC64_RELATIVE \*ABS\*\+0x157e00e4
[0-9a-f ]*: 15 7e 00 e4 .*

2
ld/testsuite/ld-powerpc/tlsexe.g
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@ -7,6 +7,6 @@
.*: +file format elf64-powerpc
Contents of section \.got:
.* 00000000 10018610 ffffffff ffff8018 .*
.* 00000000 10018620 ffffffff ffff8018 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*

2
ld/testsuite/ld-powerpc/tlsexe.r
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@ -16,7 +16,7 @@ Section Headers:
+\[[ 0-9]+\] \.dynstr +.*
+\[[ 0-9]+\] \.rela\.dyn +.*
+\[[ 0-9]+\] \.rela\.plt +.*
+\[[ 0-9]+\] \.text +PROGBITS .* 0+128 0+ +AX +0 +0 +8
+\[[ 0-9]+\] \.text +PROGBITS .* 0+128 0+ +AX +0 +0 +32
+\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+160 10 +WA +4 +0 +8

2
ld/testsuite/ld-powerpc/tlsexetoc.g
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@ -7,7 +7,7 @@
.*: +file format elf64-powerpc
Contents of section \.got:
.* 00000000 100185a8 00000000 00000000 .*
.* 00000000 100185c0 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000001 .*
.* 00000000 00000000 00000000 00000001 .*

2
ld/testsuite/ld-powerpc/tlsexetoc.r
View File

@ -16,7 +16,7 @@ Section Headers:
+\[[ 0-9]+\] \.dynstr +.*
+\[[ 0-9]+\] \.rela\.dyn +.*
+\[[ 0-9]+\] \.rela\.plt +.*
+\[[ 0-9]+\] \.text +PROGBITS .* 0+e8 0+ +AX +0 +0 +8
+\[[ 0-9]+\] \.text +PROGBITS .* 0+e8 0+ +AX +0 +0 +32
+\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+160 10 +WA +4 +0 +8

2
ld/testsuite/ld-powerpc/tlsso.g
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@ -7,7 +7,7 @@
.*: +file format elf64-powerpc
Contents of section \.got:
.* 00000000 00018778 00000000 00000000 .*
.* 00000000 00018780 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*
.* 00000000 00000000 00000000 00000000 .*

6
ld/testsuite/ld-powerpc/tlsso.r
View File

@ -48,9 +48,9 @@ Relocation section '\.rela\.dyn' at offset .* contains 16 entries:
[0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0
[0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0
[0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0
[0-9a-f ]+R_PPC64_TPREL16_DS +0+105f0 \.tdata \+ 28
[0-9a-f ]+R_PPC64_TPREL16_HA +0+105f0 \.tdata \+ 30
[0-9a-f ]+R_PPC64_TPREL16_LO +0+105f0 \.tdata \+ 30
[0-9a-f ]+R_PPC64_TPREL16_DS +0+105f8 \.tdata \+ 28
[0-9a-f ]+R_PPC64_TPREL16_HA +0+105f8 \.tdata \+ 30
[0-9a-f ]+R_PPC64_TPREL16_LO +0+105f8 \.tdata \+ 30
[0-9a-f ]+R_PPC64_DTPMOD64 +0+
[0-9a-f ]+R_PPC64_DTPREL64 +0+
[0-9a-f ]+R_PPC64_DTPREL64 +0+18