x86: Remove support for old (<= 2.8.1) versions of gcc
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and fdivrp instructions. Assembler translates them to correct ones with a warning: [hjl@gnu-cfl-1 gas]$ cat x.s fsubp %st(3),%st [hjl@gnu-cfl-1 gas]$ gcc -c x.s x.s: Assembler messages: x.s:1: Warning: translating to `fsubp %st,%st(3)' [hjl@gnu-cfl-1 gas]$ This patch removes support for old (<= 2.8.1) versions of gcc: [hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s x.s: Assembler messages: x.s:1: Error: operand type mismatch for `fsubp' [hjl@gnu-cfl-1 gas]$ gas/ * NEWS: Mention -mold-gcc removal. * config/tc-i386.c (i386_error): Remove old_gcc_only. (old_gcc): Removed. (match_template): Remove old gcc support. (OPTION_MOLD_GCC): Removed. (OPTION_MRELAX_RELOCATIONS): Updated. (md_longopts): Remove OPTION_MOLD_GCC. (md_parse_option): Likewise. (md_show_usage): Remove -mold-gcc. * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old (<= 2.8.1) versions of gcc. * testsuite/gas/i386/intel.s: Likewise. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intel.e: Likewise. * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general. include/ * opcode/i386 (OLDGCC_COMPAT): Removed. opcodes/ * i386-gen.c (opcode_modifiers): Remove OldGcc. * i386-opc.h (OldGcc): Removed. (i386_opcode_modifier): Remove oldgcc. * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp instructions for old (<= 2.8.1) versions of gcc. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
4ef0bef68c
commit
bd5dea8822
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@ -1,3 +1,23 @@
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2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention -mold-gcc removal.
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* config/tc-i386.c (i386_error): Remove old_gcc_only.
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(old_gcc): Removed.
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(match_template): Remove old gcc support.
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(OPTION_MOLD_GCC): Removed.
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(OPTION_MRELAX_RELOCATIONS): Updated.
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(md_longopts): Remove OPTION_MOLD_GCC.
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(md_parse_option): Likewise.
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(md_show_usage): Remove -mold-gcc.
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* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
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(<= 2.8.1) versions of gcc.
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* testsuite/gas/i386/intel.s: Likewise.
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* testsuite/gas/i386/general.l: Updated.
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* testsuite/gas/i386/intel-intel.d: Likewise.
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* testsuite/gas/i386/intel.d: Likewise.
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* testsuite/gas/i386/intel.e: Likewise.
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* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.
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2018-03-08 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (is_evex_encoding): New.
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2
gas/NEWS
2
gas/NEWS
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@ -1,5 +1,7 @@
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-*- text -*-
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* Remove -mold-gcc command-line option for x86 targets.
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* Add -O[2|s] command-line options to x86 assembler to enable alternate
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shorter instruction encoding.
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@ -262,7 +262,6 @@ enum i386_error
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number_of_operands_mismatch,
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invalid_instruction_suffix,
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bad_imm4,
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old_gcc_only,
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unsupported_with_intel_mnemonic,
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unsupported_syntax,
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unsupported,
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@ -562,9 +561,6 @@ static int intel64;
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0 if att mnemonic. */
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static int intel_mnemonic = !SYSV386_COMPAT;
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/* 1 if support old (<= 2.8.1) versions of gcc. */
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static int old_gcc = OLDGCC_COMPAT;
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/* 1 if pseudo registers are permitted. */
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static int allow_pseudo_reg = 0;
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@ -5280,11 +5276,6 @@ match_template (char mnem_suffix)
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if (!found_cpu_match)
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continue;
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/* Check old gcc support. */
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i.error = old_gcc_only;
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if (!old_gcc && t->opcode_modifier.oldgcc)
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continue;
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/* Check AT&T mnemonic. */
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i.error = unsupported_with_intel_mnemonic;
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if (intel_mnemonic && t->opcode_modifier.attmnemonic)
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@ -5583,9 +5574,6 @@ check_reverse:
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case bad_imm4:
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err_msg = _("constant doesn't fit in 4 bits");
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break;
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case old_gcc_only:
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err_msg = _("only supported with old gcc");
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break;
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case unsupported_with_intel_mnemonic:
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err_msg = _("unsupported with Intel mnemonic");
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break;
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@ -10312,7 +10300,7 @@ const char *md_shortopts = "qnO::";
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#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
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#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
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#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
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#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
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#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
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#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
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#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
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#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
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@ -10328,7 +10316,6 @@ const char *md_shortopts = "qnO::";
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#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
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#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
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#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
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#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
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struct option md_longopts[] =
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{
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@ -10348,7 +10335,6 @@ struct option md_longopts[] =
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{"msyntax", required_argument, NULL, OPTION_MSYNTAX},
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{"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
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{"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
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{"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
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{"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
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{"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
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{"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
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@ -10620,10 +10606,6 @@ md_parse_option (int c, const char *arg)
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allow_naked_reg = 1;
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break;
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case OPTION_MOLD_GCC:
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old_gcc = 1;
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break;
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case OPTION_MSSE2AVX:
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sse2avx = 1;
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break;
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@ -10934,8 +10916,6 @@ md_show_usage (FILE *stream)
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fprintf (stream, _("\
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-mnaked-reg don't require `%%' prefix for registers\n"));
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fprintf (stream, _("\
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-mold-gcc support old (<= 2.8.1) versions of gcc\n"));
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fprintf (stream, _("\
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-madd-bnd-prefix add BND prefix for all valid branches\n"));
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fprintf (stream, _("\
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-mshared disable branch optimization for shared code\n"));
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@ -24,10 +24,6 @@
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.*:132: Warning:.*
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.*:133: Warning:.*
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.*:134: Warning:.*
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.*:135: Warning:.*
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.*:136: Warning:.*
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.*:137: Warning:.*
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.*:138: Warning:.*
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.*:139: Warning:.*
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.*:140: Warning:.*
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.*:141: Warning:.*
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@ -194,14 +190,10 @@
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.*Warning:.*
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134 014a DECA fmulp %st\(2\),%st
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.*Warning:.*
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135 014c DEE3 fsubp %st\(3\),%st
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.*Warning:.*
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136 014e DEEC fsubrp %st\(4\),%st
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.*Warning:.*
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137 0150 DEF5 fdivp %st\(5\),%st
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.*Warning:.*
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138 0152 DEFE fdivrp %st\(6\),%st
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.*Warning:.*
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135 014c D8E3 fsub %st\(3\),%st
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136 014e D8EC fsubr %st\(4\),%st
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137 0150 D8F5 fdiv %st\(5\),%st
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138 0152 D8FE fdivr %st\(6\),%st
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139 0154 DEC1 fadd
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.*Warning:.*
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140 0156 DEE1 fsub
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@ -132,10 +132,10 @@
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fcompl %st(5)
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faddp %st(1),%st
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fmulp %st(2),%st
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fsubp %st(3),%st
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fsubrp %st(4),%st
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fdivp %st(5),%st
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fdivrp %st(6),%st
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fsub %st(3),%st
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fsubr %st(4),%st
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fdiv %st(5),%st
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fdivr %st(6),%st
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fadd
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fsub
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fmul
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@ -40,7 +40,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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set ASFLAGS "$ASFLAGS --32"
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run_list_test "float" "-al -mmnemonic=att"
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run_list_test "general" "-al --listing-lhs-width=2 -mold-gcc"
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run_list_test "general" "-al --listing-lhs-width=2"
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run_list_test "inval" "-al"
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run_list_test "inval-16" "-al"
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run_list_test "segment" "-al"
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@ -653,7 +653,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de f9 + fdivp st\(1\),st
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[ ]*[a-f0-9]+: de fb + fdivp st\(3\),st
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[ ]*[a-f0-9]+: de fb + fdivp st\(3\),st
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[ ]*[a-f0-9]+: de fb + fdivp st\(3\),st
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[ ]*[a-f0-9]+: d8 f3 + fdiv st,st\(3\)
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[ ]*[a-f0-9]+: de f1 + fdivrp st\(1\),st
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[ ]*[a-f0-9]+: d8 fb + fdivr st,st\(3\)
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[ ]*[a-f0-9]+: d8 fb + fdivr st,st\(3\)
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@ -663,7 +663,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de f1 + fdivrp st\(1\),st
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[ ]*[a-f0-9]+: de f3 + fdivrp st\(3\),st
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[ ]*[a-f0-9]+: de f3 + fdivrp st\(3\),st
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[ ]*[a-f0-9]+: de f3 + fdivrp st\(3\),st
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[ ]*[a-f0-9]+: d8 fb + fdivr st,st\(3\)
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[ ]*[a-f0-9]+: de c9 + fmulp st\(1\),st
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[ ]*[a-f0-9]+: d8 cb + fmul st,st\(3\)
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[ ]*[a-f0-9]+: d8 cb + fmul st,st\(3\)
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@ -682,7 +682,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: dc 23 + fsub QWORD PTR \[ebx\]
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[ ]*[a-f0-9]+: de e9 + fsubp st\(1\),st
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[ ]*[a-f0-9]+: de eb + fsubp st\(3\),st
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[ ]*[a-f0-9]+: de eb + fsubp st\(3\),st
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[ ]*[a-f0-9]+: d8 e3 + fsub st,st\(3\)
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[ ]*[a-f0-9]+: de eb + fsubp st\(3\),st
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[ ]*[a-f0-9]+: d8 eb + fsubr st,st\(3\)
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[ ]*[a-f0-9]+: d8 eb + fsubr st,st\(3\)
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@ -692,7 +692,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de e1 + fsubrp st\(1\),st
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[ ]*[a-f0-9]+: de e3 + fsubrp st\(3\),st
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[ ]*[a-f0-9]+: de e3 + fsubrp st\(3\),st
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[ ]*[a-f0-9]+: de e3 + fsubrp st\(3\),st
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[ ]*[a-f0-9]+: d8 eb + fsubr st,st\(3\)
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[ ]*[a-f0-9]+: de 3b + fidivr WORD PTR \[ebx\]
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[ ]*[a-f0-9]+: da 3b + fidivr DWORD PTR \[ebx\]
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[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\]
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@ -652,7 +652,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de f9 fdivrp %st,%st\(1\)
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[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
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[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
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[ ]*[a-f0-9]+: de fb fdivrp %st,%st\(3\)
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[ ]*[a-f0-9]+: d8 f3 fdiv %st\(3\),%st
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[ ]*[a-f0-9]+: de f1 fdivp %st,%st\(1\)
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[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
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[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
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@ -662,7 +662,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de f1 fdivp %st,%st\(1\)
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[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
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[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
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[ ]*[a-f0-9]+: de f3 fdivp %st,%st\(3\)
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[ ]*[a-f0-9]+: d8 fb fdivr %st\(3\),%st
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[ ]*[a-f0-9]+: de c9 fmulp %st,%st\(1\)
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[ ]*[a-f0-9]+: d8 cb fmul %st\(3\),%st
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[ ]*[a-f0-9]+: d8 cb fmul %st\(3\),%st
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@ -681,7 +681,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: dc 23 fsubl \(%ebx\)
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[ ]*[a-f0-9]+: de e9 fsubrp %st,%st\(1\)
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[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
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[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
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[ ]*[a-f0-9]+: d8 e3 fsub %st\(3\),%st
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[ ]*[a-f0-9]+: de eb fsubrp %st,%st\(3\)
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[ ]*[a-f0-9]+: d8 eb fsubr %st\(3\),%st
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[ ]*[a-f0-9]+: d8 eb fsubr %st\(3\),%st
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@ -691,7 +691,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de e1 fsubp %st,%st\(1\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: d8 eb fsubr %st\(3\),%st
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[ ]*[a-f0-9]+: de 3b fidivrs \(%ebx\)
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[ ]*[a-f0-9]+: da 3b fidivrl \(%ebx\)
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[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx
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@ -1,11 +1,7 @@
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.*: Assembler messages:
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.*:635: Warning: translating to `faddp'
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.*:644: Warning: translating to `fdivp'
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.*:653: Warning: translating to `fdivp st\(3\),st'
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.*:654: Warning: translating to `fdivrp'
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.*:663: Warning: translating to `fdivrp st\(3\),st'
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.*:664: Warning: translating to `fmulp'
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.*:673: Warning: translating to `fsubp'
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.*:674: Warning: translating to `fsubrp'
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.*:682: Warning: translating to `fsubp st\(3\),st'
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.*:692: Warning: translating to `fsubrp st\(3\),st'
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@ -650,7 +650,7 @@ fdiv QWORD PTR [ebx]
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fdivp
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fdivp st(3)
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fdivp st(3),st
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fdivp st,st(3)
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fdiv st,st(3)
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fdivr
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fdivr st(3)
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fdivr st,st(3)
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@ -660,7 +660,7 @@ fdivr QWORD PTR [ebx]
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fdivrp
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fdivrp st(3)
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fdivrp st(3),st
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fdivrp st,st(3)
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fdivr st,st(3)
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fmul
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fmul st(3)
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fmul st,st(3)
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@ -679,7 +679,7 @@ fsub DWORD PTR [ebx]
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fsub QWORD PTR [ebx]
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fsubp
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fsubp st(3)
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fsubp st,st(3)
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fsub st,st(3)
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fsubp st(3),st
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fsubr st(3)
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fsubr st,st(3)
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@ -689,7 +689,7 @@ fsubr QWORD PTR [ebx]
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fsubrp
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fsubrp st(3)
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fsubrp st(3),st
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fsubrp st,st(3)
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fsubr st,st(3)
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fidivr word ptr [ebx]
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fidivr dword ptr [ebx]
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@ -1,3 +1,7 @@
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2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
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* opcode/i386 (OLDGCC_COMPAT): Removed.
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2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
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@ -43,12 +43,6 @@
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compatible instructions. */
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#define SYSV386_COMPAT 1
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#endif
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#ifndef OLDGCC_COMPAT
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/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
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generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
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reversed. */
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#define OLDGCC_COMPAT SYSV386_COMPAT
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#endif
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#define MOV_AX_DISP32 0xa0
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#define POP_SEG_SHORT 0x07
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@ -1,3 +1,12 @@
|
|||
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-gen.c (opcode_modifiers): Remove OldGcc.
|
||||
* i386-opc.h (OldGcc): Removed.
|
||||
(i386_opcode_modifier): Remove oldgcc.
|
||||
* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
|
||||
instructions for old (<= 2.8.1) versions of gcc.
|
||||
* i386-tbl.h: Regenerated.
|
||||
|
||||
2018-03-08 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-opc.h (EVEXDYN): New.
|
||||
|
|
|
|||
|
|
@ -646,7 +646,6 @@ static bitfield opcode_modifiers[] =
|
|||
BITFIELD (NoDefMask),
|
||||
BITFIELD (ImplicitQuadGroup),
|
||||
BITFIELD (Optimize),
|
||||
BITFIELD (OldGcc),
|
||||
BITFIELD (ATTMnemonic),
|
||||
BITFIELD (ATTSyntax),
|
||||
BITFIELD (IntelSyntax),
|
||||
|
|
|
|||
|
|
@ -604,8 +604,6 @@ enum
|
|||
/* Support encoding optimization. */
|
||||
Optimize,
|
||||
|
||||
/* Compatible with old (<= 2.8.1) versions of gcc */
|
||||
OldGcc,
|
||||
/* AT&T mnemonic. */
|
||||
ATTMnemonic,
|
||||
/* AT&T syntax. */
|
||||
|
|
@ -681,7 +679,6 @@ typedef struct i386_opcode_modifier
|
|||
unsigned int nodefmask:1;
|
||||
unsigned int implicitquadgroup:1;
|
||||
unsigned int optimize:1;
|
||||
unsigned int oldgcc:1;
|
||||
unsigned int attmnemonic:1;
|
||||
unsigned int attsyntax:1;
|
||||
unsigned int intelsyntax:1;
|
||||
|
|
|
|||
|
|
@ -631,8 +631,6 @@ fisub, 1, 0xde, 0x4, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, {
|
|||
fsubp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
|
||||
fsubp, 1, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
|
||||
fsubp, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
|
||||
fsubp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
|
||||
fsubp, 2, 0xdee9, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||
fsubp, 2, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
||||
fsubp, 1, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
||||
fsubp, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
|
@ -650,8 +648,6 @@ fisubr, 1, 0xde, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf,
|
|||
fsubrp, 2, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
|
||||
fsubrp, 1, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
|
||||
fsubrp, 0, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
|
||||
fsubrp, 2, 0xdee8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
|
||||
fsubrp, 2, 0xdee0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||
fsubrp, 2, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
||||
fsubrp, 1, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
||||
fsubrp, 0, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
||||
|
|
@ -682,8 +678,6 @@ fidiv, 1, 0xde, 0x6, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, {
|
|||
fdivp, 2, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
|
||||
fdivp, 1, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
|
||||
fdivp, 0, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
|
||||
fdivp, 2, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
|
||||
fdivp, 2, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||
fdivp, 2, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
||||
fdivp, 1, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
||||
fdivp, 0, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
||||
|
|
@ -701,8 +695,6 @@ fidivr, 1, 0xde, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf,
|
|||
fdivrp, 2, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
|
||||
fdivrp, 1, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
|
||||
fdivrp, 0, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { 0 }
|
||||
fdivrp, 2, 0xdef8, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax|OldGcc, { FloatReg, FloatAcc }
|
||||
fdivrp, 2, 0xdef0, None, 2, CpuFP, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|OldGcc, { FloatReg, FloatAcc }
|
||||
fdivrp, 2, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg }
|
||||
fdivrp, 1, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm, { FloatReg }
|
||||
fdivrp, 0, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { 0 }
|
||||
|
|
|
|||
10314
opcodes/i386-tbl.h
10314
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue