include/opcode/
* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. Renumber other PPC_OPCODE defines. gas/ * config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags. (ppc_setup_opcodes): Likewise. Simplify opcode selection. opcodes/ * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. (PPC64, MFDEC2): Update. (NON32, NO371): Define. (powerpc_opcode): Update to not use old opcode flags, and avoid -m601 duplicates.
This commit is contained in:
Alan Modra
parent
21375995bd
commit
bdc70b4a03
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@ -1,3 +1,8 @@
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2010-07-03 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags.
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(ppc_setup_opcodes): Likewise. Simplify opcode selection.
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2010-07-02 DJ Delorie <dj@redhat.com>
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* config/tc-rx.h (md_do_align): New.
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@ -1251,16 +1251,16 @@ ppc_set_cpu (void)
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if ((ppc_cpu & ~PPC_OPCODE_ANY) == 0)
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{
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if (ppc_obj64)
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ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64;
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ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
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else if (strncmp (default_os, "aix", 3) == 0
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&& default_os[3] >= '4' && default_os[3] <= '9')
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ppc_cpu |= PPC_OPCODE_COMMON | PPC_OPCODE_32;
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ppc_cpu |= PPC_OPCODE_COMMON;
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else if (strncmp (default_os, "aix3", 4) == 0)
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ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
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ppc_cpu |= PPC_OPCODE_POWER;
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else if (strcmp (default_cpu, "rs6000") == 0)
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ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
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ppc_cpu |= PPC_OPCODE_POWER;
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else if (strncmp (default_cpu, "powerpc", 7) == 0)
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ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
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ppc_cpu |= PPC_OPCODE_PPC;
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else
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as_fatal (_("Unknown default cpu = %s, os = %s"),
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default_cpu, default_os);
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@ -1473,11 +1473,7 @@ ppc_setup_opcodes (void)
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}
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}
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if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
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&& ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
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|| ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
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== (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
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|| (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
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if ((ppc_cpu & op->flags) != 0
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&& !(ppc_cpu & op->deprecated))
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{
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const char *retval;
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@ -1485,11 +1481,6 @@ ppc_setup_opcodes (void)
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retval = hash_insert (ppc_hash, op->name, (void *) op);
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if (retval != NULL)
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{
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/* Ignore Power duplicates for -m601. */
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if ((ppc_cpu & PPC_OPCODE_601) != 0
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&& (op->flags & PPC_OPCODE_POWER) != 0)
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continue;
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as_bad (_("duplicate instruction %s"),
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op->name);
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bad_insn = TRUE;
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@ -1,3 +1,8 @@
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2010-07-03 Alan Modra <amodra@gmail.com>
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* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
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Renumber other PPC_OPCODE defines.
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2010-07-03 Alan Modra <amodra@gmail.com>
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* ppc.h (PPC_OPCODE_COMMON): Expand comment.
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@ -77,111 +77,102 @@ extern const int powerpc_num_opcodes;
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/* Opcode is defined for the POWER2 (Rios 2) architecture. */
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#define PPC_OPCODE_POWER2 4
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/* Opcode is only defined on 32 bit architectures. */
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#define PPC_OPCODE_32 8
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/* Opcode is only defined on 64 bit architectures. */
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#define PPC_OPCODE_64 0x10
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/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
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is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
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but it also supports many additional POWER instructions. */
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#define PPC_OPCODE_601 0x20
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#define PPC_OPCODE_601 8
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/* Opcode is supported in both the Power and PowerPC architectures
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(ie, compiler's -mcpu=common or assembler's -mcom). More than just
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the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
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and PPC_OPCODE_POWER2 because many instructions changed mnemonics
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between POWER and POWERPC. */
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#define PPC_OPCODE_COMMON 0x40
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#define PPC_OPCODE_COMMON 0x10
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/* Opcode is supported for any Power or PowerPC platform (this is
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for the assembler's -many option, and it eliminates duplicates). */
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#define PPC_OPCODE_ANY 0x80
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#define PPC_OPCODE_ANY 0x20
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/* Opcode is only defined on 64 bit architectures. */
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#define PPC_OPCODE_64 0x40
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/* Opcode is supported as part of the 64-bit bridge. */
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#define PPC_OPCODE_64_BRIDGE 0x100
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#define PPC_OPCODE_64_BRIDGE 0x80
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/* Opcode is supported by Altivec Vector Unit */
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#define PPC_OPCODE_ALTIVEC 0x200
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#define PPC_OPCODE_ALTIVEC 0x100
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/* Opcode is supported by PowerPC 403 processor. */
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#define PPC_OPCODE_403 0x400
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#define PPC_OPCODE_403 0x200
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/* Opcode is supported by PowerPC BookE processor. */
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#define PPC_OPCODE_BOOKE 0x800
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/* Opcode is only supported by 64-bit PowerPC BookE processor. */
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#define PPC_OPCODE_BOOKE64 0x1000
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#define PPC_OPCODE_BOOKE 0x400
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/* Opcode is supported by PowerPC 440 processor. */
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#define PPC_OPCODE_440 0x2000
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#define PPC_OPCODE_440 0x800
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/* Opcode is only supported by Power4 architecture. */
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#define PPC_OPCODE_POWER4 0x4000
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#define PPC_OPCODE_POWER4 0x1000
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/* Opcode is only supported by Power7 architecture. */
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#define PPC_OPCODE_POWER7 0x8000
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/* Opcode is only supported by POWERPC Classic architecture. */
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#define PPC_OPCODE_CLASSIC 0x10000
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#define PPC_OPCODE_POWER7 0x2000
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/* Opcode is only supported by e500x2 Core. */
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#define PPC_OPCODE_SPE 0x20000
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#define PPC_OPCODE_SPE 0x4000
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/* Opcode is supported by e500x2 Integer select APU. */
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#define PPC_OPCODE_ISEL 0x40000
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#define PPC_OPCODE_ISEL 0x8000
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/* Opcode is an e500 SPE floating point instruction. */
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#define PPC_OPCODE_EFS 0x80000
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#define PPC_OPCODE_EFS 0x10000
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/* Opcode is supported by branch locking APU. */
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#define PPC_OPCODE_BRLOCK 0x100000
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#define PPC_OPCODE_BRLOCK 0x20000
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/* Opcode is supported by performance monitor APU. */
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#define PPC_OPCODE_PMR 0x200000
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#define PPC_OPCODE_PMR 0x40000
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/* Opcode is supported by cache locking APU. */
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#define PPC_OPCODE_CACHELCK 0x400000
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#define PPC_OPCODE_CACHELCK 0x80000
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/* Opcode is supported by machine check APU. */
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#define PPC_OPCODE_RFMCI 0x800000
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#define PPC_OPCODE_RFMCI 0x100000
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/* Opcode is only supported by Power5 architecture. */
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#define PPC_OPCODE_POWER5 0x1000000
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#define PPC_OPCODE_POWER5 0x200000
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/* Opcode is supported by PowerPC e300 family. */
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#define PPC_OPCODE_E300 0x2000000
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#define PPC_OPCODE_E300 0x400000
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/* Opcode is only supported by Power6 architecture. */
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#define PPC_OPCODE_POWER6 0x4000000
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#define PPC_OPCODE_POWER6 0x800000
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/* Opcode is only supported by PowerPC Cell family. */
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#define PPC_OPCODE_CELL 0x8000000
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#define PPC_OPCODE_CELL 0x1000000
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/* Opcode is supported by CPUs with paired singles support. */
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#define PPC_OPCODE_PPCPS 0x10000000
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#define PPC_OPCODE_PPCPS 0x2000000
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/* Opcode is supported by Power E500MC */
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#define PPC_OPCODE_E500MC 0x20000000
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#define PPC_OPCODE_E500MC 0x4000000
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/* Opcode is supported by PowerPC 405 processor. */
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#define PPC_OPCODE_405 0x40000000
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#define PPC_OPCODE_405 0x8000000
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/* Opcode is supported by Vector-Scalar (VSX) Unit */
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#define PPC_OPCODE_VSX 0x80000000
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#define PPC_OPCODE_VSX 0x10000000
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/* Opcode is supported by A2. */
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#define PPC_OPCODE_A2 0x100000000ULL
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#define PPC_OPCODE_A2 0x20000000
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/* Opcode is supported by PowerPC 476 processor. */
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#define PPC_OPCODE_476 0x200000000ULL
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#define PPC_OPCODE_476 0x40000000
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/* Opcode is supported by AppliedMicro Titan core */
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#define PPC_OPCODE_TITAN 0x400000000ULL
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#define PPC_OPCODE_TITAN 0x80000000
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/* Opcode which is supported by the e500 family */
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#define PPC_OPCODE_E500 0x800000000ULL
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#define PPC_OPCODE_E500 0x100000000ull
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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@ -1,3 +1,12 @@
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2010-07-03 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
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* ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
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(PPC64, MFDEC2): Update.
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(NON32, NO371): Define.
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(powerpc_opcode): Update to not use old opcode flags, and avoid
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-m601 duplicates.
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2010-07-03 DJ Delorie <dj@delorie.com>
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* m32c-ibld.c: Regenerate.
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@ -50,64 +50,55 @@ struct ppc_mopt {
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};
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struct ppc_mopt ppc_opts[] = {
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{ "403", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
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| PPC_OPCODE_32),
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{ "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
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0 },
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{ "405", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_403
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| PPC_OPCODE_405 | PPC_OPCODE_32),
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{ "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
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0 },
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{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
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| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
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| PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
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| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
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0 },
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{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
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| PPC_OPCODE_440 | PPC_OPCODE_476 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
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| PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
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0 },
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{ "601", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_601
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| PPC_OPCODE_32),
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{ "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
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0 },
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{ "603", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
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{ "603", (PPC_OPCODE_PPC),
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0 },
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{ "604", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
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{ "604", (PPC_OPCODE_PPC),
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0 },
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{ "620", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64),
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{ "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
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0 },
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{ "7400", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_32),
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{ "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "7410", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_32),
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{ "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "7450", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_32),
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{ "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "7455", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ALTIVEC
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| PPC_OPCODE_32),
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{ "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
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0 },
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{ "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
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, 0 },
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{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK
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| PPC_OPCODE_64 | PPC_OPCODE_A2),
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{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
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| PPC_OPCODE_A2),
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0 },
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{ "altivec", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
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{ "altivec", (PPC_OPCODE_PPC),
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PPC_OPCODE_ALTIVEC },
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{ "any", 0,
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PPC_OPCODE_ANY },
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{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32),
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{ "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
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0 },
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{ "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32),
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{ "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
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0 },
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{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
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{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
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0 },
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{ "com", (PPC_OPCODE_COMMON | PPC_OPCODE_32),
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{ "com", (PPC_OPCODE_COMMON),
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0 },
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{ "e300", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32
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| PPC_OPCODE_E300),
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{ "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
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0 },
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{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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@ -130,62 +121,55 @@ struct ppc_mopt ppc_opts[] = {
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0 },
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{ "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
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0 },
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{ "power4", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
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| PPC_OPCODE_POWER4),
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{ "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
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0 },
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{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
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{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5),
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0 },
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{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
|
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{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
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0 },
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{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
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| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ALTIVEC),
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| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
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0 },
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{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
|
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| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
|
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| PPC_OPCODE_VSX),
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{ "ppc", (PPC_OPCODE_PPC),
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0 },
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{ "ppc", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
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{ "ppc32", (PPC_OPCODE_PPC),
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0 },
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{ "ppc32", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32),
|
||||
{ "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
|
||||
0 },
|
||||
{ "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64),
|
||||
0 },
|
||||
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64_BRIDGE
|
||||
| PPC_OPCODE_64),
|
||||
{ "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
|
||||
0 },
|
||||
{ "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
|
||||
0 },
|
||||
{ "pwr", (PPC_OPCODE_POWER | PPC_OPCODE_32),
|
||||
{ "pwr", (PPC_OPCODE_POWER),
|
||||
0 },
|
||||
{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
|
||||
{ "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
|
||||
0 },
|
||||
{ "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4),
|
||||
{ "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
|
||||
0 },
|
||||
{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
|
||||
{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
||||
| PPC_OPCODE_POWER5),
|
||||
0 },
|
||||
{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
|
||||
{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
||||
| PPC_OPCODE_POWER5),
|
||||
0 },
|
||||
{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64
|
||||
{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
|
||||
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
|
||||
0 },
|
||||
{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
|
||||
| PPC_OPCODE_ALTIVEC),
|
||||
| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
|
||||
0 },
|
||||
{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_ISEL
|
||||
| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
|
||||
| PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC
|
||||
| PPC_OPCODE_VSX),
|
||||
0 },
|
||||
{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_32),
|
||||
{ "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
|
||||
0 },
|
||||
{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
|
||||
PPC_OPCODE_SPE },
|
||||
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
|
||||
| PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
|
||||
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
|
||||
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
|
||||
0 },
|
||||
{ "vsx", (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC),
|
||||
{ "vsx", (PPC_OPCODE_PPC),
|
||||
PPC_OPCODE_VSX },
|
||||
};
|
||||
|
||||
|
|
@ -243,15 +227,9 @@ powerpc_init_dialect (struct disassemble_info *info)
|
|||
if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
|
||||
dialect = new_cpu;
|
||||
else if (strcmp (arg, "32") == 0)
|
||||
{
|
||||
dialect &= ~PPC_OPCODE_64;
|
||||
dialect |= PPC_OPCODE_32;
|
||||
}
|
||||
dialect &= ~PPC_OPCODE_64;
|
||||
else if (strcmp (arg, "64") == 0)
|
||||
{
|
||||
dialect |= PPC_OPCODE_64;
|
||||
dialect &= ~PPC_OPCODE_32;
|
||||
}
|
||||
dialect |= PPC_OPCODE_64;
|
||||
else
|
||||
fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
|
||||
|
||||
|
|
@ -260,15 +238,15 @@ powerpc_init_dialect (struct disassemble_info *info)
|
|||
arg = end;
|
||||
}
|
||||
|
||||
if ((dialect & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) == 0)
|
||||
if ((dialect & ~PPC_OPCODE_64) == 0)
|
||||
{
|
||||
if (info->mach == bfd_mach_ppc64)
|
||||
dialect |= PPC_OPCODE_64;
|
||||
else
|
||||
dialect |= PPC_OPCODE_32;
|
||||
dialect &= ~PPC_OPCODE_64;
|
||||
/* Choose a reasonable default. */
|
||||
dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_CLASSIC
|
||||
| PPC_OPCODE_601 | PPC_OPCODE_ALTIVEC);
|
||||
dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
|
||||
| PPC_OPCODE_ALTIVEC);
|
||||
}
|
||||
|
||||
info->private_data = priv;
|
||||
|
|
|
|||
|
|
@ -1908,8 +1908,9 @@ extract_dm (unsigned long insn,
|
|||
#define POWER6 PPC_OPCODE_POWER6
|
||||
#define POWER7 PPC_OPCODE_POWER7
|
||||
#define CELL PPC_OPCODE_CELL
|
||||
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
|
||||
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
|
||||
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
|
||||
#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_PPCPS \
|
||||
| PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
|
||||
#define PPC403 PPC_OPCODE_403
|
||||
#define PPC405 PPC_OPCODE_405
|
||||
#define PPC440 PPC_OPCODE_440
|
||||
|
|
@ -1925,15 +1926,13 @@ extract_dm (unsigned long insn,
|
|||
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
|
||||
#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
|
||||
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
|
||||
#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
|
||||
#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
|
||||
#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
|
||||
#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
|
||||
#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
|
||||
#define MFDEC1 PPC_OPCODE_POWER
|
||||
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
|
||||
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
|
||||
#define BOOKE PPC_OPCODE_BOOKE
|
||||
#define CLASSIC PPC_OPCODE_CLASSIC
|
||||
#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
|
||||
#define PPCE300 PPC_OPCODE_E300
|
||||
#define PPCSPE PPC_OPCODE_SPE
|
||||
#define PPCISEL PPC_OPCODE_ISEL
|
||||
|
|
@ -2622,12 +2621,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}},
|
||||
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}},
|
||||
{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}},
|
||||
{"cmpli", OP(10), OP_MASK, PWRCOM, PPCNONE, {BF, RA, UI}},
|
||||
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC, {BF, RA, UI}},
|
||||
|
||||
{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}},
|
||||
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}},
|
||||
{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}},
|
||||
{"cmpi", OP(11), OP_MASK, PWRCOM, PPCNONE, {BF, RA, SI}},
|
||||
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC, {BF, RA, SI}},
|
||||
|
||||
{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}},
|
||||
{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}},
|
||||
|
|
@ -3429,7 +3428,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
|
||||
{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
|
||||
{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
|
||||
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}},
|
||||
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
|
||||
|
||||
{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}},
|
||||
{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}},
|
||||
|
|
@ -3530,7 +3529,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}},
|
||||
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}},
|
||||
{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}},
|
||||
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}},
|
||||
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
|
||||
|
||||
{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
|
||||
{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
|
||||
|
|
@ -3726,7 +3725,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}},
|
||||
|
||||
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, TITAN, {SR, RS}},
|
||||
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
|
||||
|
||||
{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
|
||||
|
||||
|
|
@ -3769,8 +3768,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
|
||||
{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}},
|
||||
{"mtsrin", X(31,242), XRA_MASK, PPC32, TITAN, {RS, RB}},
|
||||
{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}},
|
||||
{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
|
||||
{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
|
||||
|
||||
{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}},
|
||||
{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}},
|
||||
|
|
@ -3893,7 +3892,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}},
|
||||
{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
|
||||
{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
|
||||
{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN, PPCNONE, {RT}},
|
||||
{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
|
||||
{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}},
|
||||
{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
|
||||
{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}},
|
||||
|
|
@ -4097,9 +4096,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"tlbia", X(31,370), 0xffffffff, PPC, TITAN, {0}},
|
||||
|
||||
{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
|
||||
{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}},
|
||||
{"mftb", X(31,371), X_MASK, CLASSIC|PPCA2, POWER7, {RT, TBR}},
|
||||
{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371, {RT}},
|
||||
{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}},
|
||||
{"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}},
|
||||
|
||||
{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}},
|
||||
|
||||
|
|
@ -4465,7 +4464,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
|
||||
|
||||
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, TITAN, {RT, SR}},
|
||||
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
|
||||
|
||||
{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}},
|
||||
{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
|
||||
|
|
@ -4514,7 +4513,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
|
||||
{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
|
||||
|
||||
{"mfsrin", X(31,659), XRA_MASK, PPC32, TITAN, {RT, RB}},
|
||||
{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
|
||||
|
||||
{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue