2000-12-05 Kazu Hirata <kazu@hxi.com>
* config/tc-mips.c: Fix formatting.
This commit is contained in:
Kazu Hirata
parent
8157b96704
commit
beae10d5eb
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@ -1,3 +1,7 @@
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2000-12-05 Kazu Hirata <kazu@hxi.com>
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* config/tc-mips.c: Fix formatting.
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2000-12-04 Matthew Hiller <hiller@redhat.com>
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* config/tc-d10v.c (flag_allow_gstabs_packing): New variable.
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@ -110,6 +110,7 @@ extern int target_big_endian;
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static int mips_64;
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/* The default target format to use. */
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const char *
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mips_target_format ()
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{
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@ -152,8 +153,7 @@ mips_target_format ()
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pseudo-op. We use a struct so that .set push and .set pop are more
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reliable. */
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struct mips_set_options
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{
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struct mips_set_options {
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/* MIPS ISA (Instruction Set Architecture) level. This is set to -1
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if it has not been initialized. Changed by `.set mipsN', and the
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-mipsN command line option, and the default CPU. */
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@ -190,8 +190,7 @@ struct mips_set_options
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that we must set the isa field to ISA_UNKNOWN and the mips16 field to
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-1 to indicate that they have not been initialized. */
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static struct mips_set_options mips_opts =
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{
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static struct mips_set_options mips_opts = {
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ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0
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};
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@ -208,7 +207,7 @@ static int file_mips_isa = ISA_UNKNOWN;
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static int mips_cpu = CPU_UNKNOWN;
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/* The argument of the -mabi= flag. */
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static char* mips_abi_string = 0;
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static char *mips_abi_string = 0;
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/* Wether we should mark the file EABI64 or EABI32. */
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static int mips_eabi64 = 0;
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@ -290,8 +289,7 @@ static int mips_gp32 = 0;
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/* MIPS PIC level. */
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enum mips_pic_level
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{
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enum mips_pic_level {
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/* Do not generate PIC code. */
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NO_PIC,
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@ -485,8 +483,7 @@ static int prev_nop_frag_since;
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relocation. We then sort them so that they immediately precede the
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corresponding LO relocation. */
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struct mips_hi_fixup
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{
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struct mips_hi_fixup {
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/* Next HI fixup. */
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struct mips_hi_fixup *next;
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/* This fixup. */
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@ -502,8 +499,7 @@ static struct mips_hi_fixup *mips_hi_fixup_list;
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/* Map normal MIPS register numbers to mips16 register numbers. */
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#define X ILLEGAL_REG
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static const int mips32_to_16_reg_map[] =
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{
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static const int mips32_to_16_reg_map[] = {
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X, X, 2, 3, 4, 5, 6, 7,
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X, X, X, X, X, X, X, X,
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0, 1, X, X, X, X, X, X,
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@ -513,8 +509,7 @@ static const int mips32_to_16_reg_map[] =
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/* Map mips16 register numbers to normal MIPS register numbers. */
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static const unsigned int mips16_to_32_reg_map[] =
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{
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static const unsigned int mips16_to_32_reg_map[] = {
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16, 17, 2, 3, 4, 5, 6, 7
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};
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@ -589,8 +584,8 @@ static const unsigned int mips16_to_32_reg_map[] =
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| ((warn) ? 1 : 0)))
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#define RELAX_OLD(i) (((i) >> 23) & 0x7f)
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#define RELAX_NEW(i) (((i) >> 16) & 0x7f)
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#define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
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#define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
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#define RELAX_RELOC1(i) ((bfd_vma) (((i) >> 9) & 0x7f) - 64)
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#define RELAX_RELOC2(i) ((bfd_vma) (((i) >> 2) & 0x7f) - 64)
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#define RELAX_RELOC3(i) (((i) >> 1) & 1)
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#define RELAX_WARN(i) ((i) & 1)
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@ -718,8 +713,7 @@ static int validate_mips_insn PARAMS ((const struct mips_opcode *));
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/* Table and functions used to map between CPU/ISA names, and
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ISA levels, and CPU numbers. */
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struct mips_cpu_info
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{
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struct mips_cpu_info {
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const char *name; /* CPU or ISA name. */
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int is_isa; /* Is this an ISA? (If 0, a CPU.) */
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int isa; /* ISA level. */
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@ -748,8 +742,7 @@ static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
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they are not currently supported: .asm0, .endr, .lab, .repeat,
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.struct. */
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static const pseudo_typeS mips_pseudo_table[] =
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{
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static const pseudo_typeS mips_pseudo_table[] = {
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/* MIPS specific pseudo-ops. */
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{"option", s_option, 0},
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{"set", s_mipsset, 0},
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@ -823,8 +816,7 @@ mips_pop_insert ()
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/* Symbols labelling the current insn. */
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struct insn_label_list
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{
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struct insn_label_list {
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struct insn_label_list *next;
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symbolS *label;
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};
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@ -998,7 +990,7 @@ md_begin ()
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the best, but then neither is basing the abi on the isa. */
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if (ISA_HAS_64BIT_REGS (mips_opts.isa)
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&& mips_abi_string
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&& 0 == strcmp (mips_abi_string,"eabi"))
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&& 0 == strcmp (mips_abi_string, "eabi"))
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mips_eabi64 = 1;
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/* If they asked for mips1 or mips2 and a cpu that is
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@ -1224,7 +1216,7 @@ md_assemble (str)
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else
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{
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mips_ip (str, &insn);
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DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
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DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
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str, insn.insn_opcode));
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}
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@ -1893,7 +1885,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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instruction. May want to add this support in the future. */
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}
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/* Never set the bit for $0, which is always zero. */
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mips_gprmask &=~ 1 << 0;
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mips_gprmask &= ~1 << 0;
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}
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else
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{
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@ -3083,8 +3075,8 @@ load_register (counter, reg, ep, dbl)
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himask = 0xffff << (shift - 32);
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lomask = 0;
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}
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if ((hi32.X_add_number & ~ (offsetT) himask) == 0
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&& (lo32.X_add_number & ~ (offsetT) lomask) == 0)
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if ((hi32.X_add_number & ~(offsetT) himask) == 0
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&& (lo32.X_add_number & ~(offsetT) lomask) == 0)
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{
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expressionS tmp;
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@ -3094,7 +3086,8 @@ load_register (counter, reg, ep, dbl)
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| (lo32.X_add_number >> shift));
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else
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tmp.X_add_number = hi32.X_add_number >> (shift - 32);
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macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
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macro_build ((char *) NULL, counter, &tmp,
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"ori", "t,r,i", reg, 0,
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(int) BFD_RELOC_LO16);
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macro_build ((char *) NULL, counter, NULL,
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(shift >= 32) ? "dsll32" : "dsll",
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@ -3103,7 +3096,8 @@ load_register (counter, reg, ep, dbl)
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return;
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}
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shift++;
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} while (shift <= (64 - 16));
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}
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while (shift <= (64 - 16));
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/* Find the bit number of the lowest one bit, and store the
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shifted value in hi/lo. */
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@ -3166,7 +3160,7 @@ load_register (counter, reg, ep, dbl)
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/* Sign extend hi32 before calling load_register, because we can
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generally get better code when we load a sign extended value. */
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if ((hi32.X_add_number & 0x80000000) != 0)
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hi32.X_add_number |= ~ (offsetT) 0xffffffff;
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hi32.X_add_number |= ~(offsetT) 0xffffffff;
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load_register (counter, reg, &hi32, 0);
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freg = reg;
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}
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@ -8467,8 +8461,7 @@ mips16_ip (str, ip)
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/* This structure holds information we know about a mips16 immediate
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argument type. */
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struct mips16_immed_operand
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{
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struct mips16_immed_operand {
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/* The type code used in the argument string in the opcode table. */
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int type;
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/* The number of bits in the short form of the opcode. */
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@ -8583,7 +8576,8 @@ mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
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needext = false;
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if (warn && ext && ! needext)
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as_warn_where (file, line, _("extended operand requested but not required"));
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as_warn_where (file, line,
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_("extended operand requested but not required"));
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if (small && needext)
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as_bad_where (file, line, _("invalid unextended operand value"));
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@ -8825,8 +8819,7 @@ md_number_to_chars (buf, val, n)
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CONST char *md_shortopts = "O::g::G:";
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struct option md_longopts[] =
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{
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struct option md_longopts[] = {
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#define OPTION_MIPS1 (OPTION_MD_BASE + 1)
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{"mips0", no_argument, NULL, OPTION_MIPS1},
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{"mips1", no_argument, NULL, OPTION_MIPS1},
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@ -9138,21 +9131,25 @@ md_parse_option (c, arg)
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gcc, but to set this flag before gcc is built with such
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multilibs will break too many systems. */
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/* mips_32bitmode = 1; */
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#if 0
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mips_32bitmode = 1;
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#endif
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break;
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case OPTION_GP64:
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mips_gp32 = 0;
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mips_64 = 1;
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/* mips_32bitmode = 0; */
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#if 0
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mips_32bitmode = 0;
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#endif
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break;
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case OPTION_MABI:
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if (strcmp (arg,"32") == 0
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|| strcmp (arg,"n32") == 0
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|| strcmp (arg,"64") == 0
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|| strcmp (arg,"o64") == 0
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|| strcmp (arg,"eabi") == 0)
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if (strcmp (arg, "32") == 0
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|| strcmp (arg, "n32") == 0
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|| strcmp (arg, "64") == 0
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|| strcmp (arg, "o64") == 0
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|| strcmp (arg, "eabi") == 0)
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mips_abi_string = arg;
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break;
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@ -9207,7 +9204,7 @@ md_show_usage (stream)
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{
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int column, first;
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fprintf(stream, _("\
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fprintf (stream, _("\
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MIPS options:\n\
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-membedded-pic generate embedded position independent code\n\
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-EB generate big endian output\n\
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@ -9215,7 +9212,7 @@ MIPS options:\n\
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-g, -g2 do not remove uneeded NOPs or swap branches\n\
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-G NUM allow referencing objects up to NUM bytes\n\
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implicitly with the gp register [default 8]\n"));
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fprintf(stream, _("\
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fprintf (stream, _("\
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-mips1 generate MIPS ISA I instructions\n\
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-mips2 generate MIPS ISA II instructions\n\
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-mips3 generate MIPS ISA III instructions\n\
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@ -9259,17 +9256,17 @@ MIPS options:\n\
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show (stream, "4650", &column, &first);
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fputc ('\n', stream);
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fprintf(stream, _("\
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fprintf (stream, _("\
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-mips16 generate mips16 instructions\n\
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-no-mips16 do not generate mips16 instructions\n"));
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fprintf(stream, _("\
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fprintf (stream, _("\
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-O0 remove unneeded NOPs, do not swap branches\n\
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-O remove unneeded NOPs and swap branches\n\
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--[no-]construct-floats [dis]allow floating point values to be constructed\n\
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--trap, --no-break trap exception on div by 0 and mult overflow\n\
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--break, --no-trap break exception on div by 0 and mult overflow\n"));
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#ifdef OBJ_ELF
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fprintf(stream, _("\
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fprintf (stream, _("\
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-KPIC, -call_shared generate SVR4 position independent code\n\
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-non_shared do not generate position independent code\n\
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-xgot assume a 32 bit GOT\n\
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@ -9283,7 +9280,7 @@ mips_init_after_args ()
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{
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/* initialize opcodes */
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bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
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mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes;
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mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
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}
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long
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@ -9452,7 +9449,6 @@ mips_frob_file ()
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relocations, in case the linker has to relax a call. We also need
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to keep relocations for switch table entries. */
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/*ARGSUSED*/
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int
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mips_force_relocation (fixp)
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fixS *fixp;
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@ -10162,8 +10158,7 @@ s_option (x)
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/* This structure is used to hold a stack of .set values. */
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struct mips_option_stack
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{
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struct mips_option_stack {
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struct mips_option_stack *next;
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struct mips_set_options options;
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};
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@ -10921,7 +10916,6 @@ mips16_extended_frag (fragp, sec, stretch)
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encoded in the subtype information. For the mips16, we have to
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decide whether we are using an extended opcode or not. */
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/*ARGSUSED*/
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int
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md_estimate_size_before_relax (fragp, segtype)
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fragS *fragp;
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@ -11511,11 +11505,11 @@ mips_elf_final_processing ()
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/* Set the MIPS ELF ABI flags. */
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if (mips_abi_string == 0)
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;
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else if (strcmp (mips_abi_string,"32") == 0)
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else if (strcmp (mips_abi_string, "32") == 0)
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elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
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else if (strcmp (mips_abi_string,"o64") == 0)
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else if (strcmp (mips_abi_string, "o64") == 0)
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elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
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else if (strcmp (mips_abi_string,"eabi") == 0)
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else if (strcmp (mips_abi_string, "eabi") == 0)
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{
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if (mips_eabi64)
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elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
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@ -11529,8 +11523,7 @@ mips_elf_final_processing ()
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#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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typedef struct proc
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{
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typedef struct proc {
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symbolS *isym;
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unsigned long reg_mask;
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unsigned long reg_offset;
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@ -11539,8 +11532,7 @@ typedef struct proc
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unsigned long frame_offset;
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unsigned long frame_reg;
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unsigned long pc_reg;
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}
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procS;
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} procS;
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static procS cur_proc;
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static procS *cur_proc_ptr;
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@ -11720,21 +11712,21 @@ s_mips_end (x)
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assert (pdr_seg);
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subseg_set (pdr_seg, 0);
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/* Write the symbol */
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/* Write the symbol. */
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exp.X_op = O_symbol;
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exp.X_add_symbol = p;
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exp.X_add_number = 0;
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emit_expr (&exp, 4);
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fragp = frag_more (7*4);
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fragp = frag_more (7 * 4);
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md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
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md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
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md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
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md_number_to_chars (fragp +12, (valueT) cur_proc_ptr->fpreg_offset, 4);
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md_number_to_chars (fragp +16, (valueT) cur_proc_ptr->frame_offset, 4);
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md_number_to_chars (fragp +20, (valueT) cur_proc_ptr->frame_reg, 4);
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md_number_to_chars (fragp +24, (valueT) cur_proc_ptr->pc_reg, 4);
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md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
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md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
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md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
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md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
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subseg_set (saved_seg, saved_subseg);
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}
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@ -11916,8 +11908,7 @@ s_loc (x)
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Case is ignored in comparison, so put the canonical entry in the
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appropriate case but everything else in lower case to ease eye pain. */
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static const struct mips_cpu_info mips_cpu_info_table[] =
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{
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static const struct mips_cpu_info mips_cpu_info_table[] = {
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||||
/* MIPS1 ISA */
|
||||
{ "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
|
||||
{ "mips", 1, ISA_MIPS1, CPU_R3000, },
|
||||
|
|
@ -12066,7 +12057,7 @@ mips_cpu_info_from_name (name)
|
|||
int i;
|
||||
|
||||
for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
|
||||
if (strcasecmp(name, mips_cpu_info_table[i].name) == 0)
|
||||
if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
|
||||
return (&mips_cpu_info_table[i]);
|
||||
|
||||
return (NULL);
|
||||
|
|
|
|||
Loading…
Reference in New Issue