x86: fix indentation in build_modrm_byte()
The VEX3SOURCES code was (originally) written with just space indentation, which is not in line with general coding style as well as the style later in the function.
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@ -1,3 +1,7 @@
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2018-04-26 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (build_modrm_byte): Use tabs for indentation.
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2018-04-26 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (build_modrm_byte): Move and fold
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@ -6577,15 +6577,15 @@ build_modrm_byte (void)
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nds = dest - 1;
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/* There are 2 kinds of instructions:
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1. 5 operands: 4 register operands or 3 register operands
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plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
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VexW0 or VexW1. The destination must be either XMM, YMM or
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1. 5 operands: 4 register operands or 3 register operands
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plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
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VexW0 or VexW1. The destination must be either XMM, YMM or
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ZMM register.
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2. 4 operands: 4 register operands or 3 register operands
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2. 4 operands: 4 register operands or 3 register operands
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plus 1 memory operand, with VexXDS. */
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gas_assert ((i.reg_operands == 4
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS
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|| (i.reg_operands == 3 && i.mem_operands == 1))
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS
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&& i.tm.opcode_modifier.vexw
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&& i.tm.operand_types[dest].bitfield.regsimd);
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@ -6603,46 +6603,46 @@ build_modrm_byte (void)
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}
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if (i.imm_operands == 0)
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{
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/* When there is no immediate operand, generate an 8bit
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immediate operand to encode the first operand. */
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exp = &im_expressions[i.imm_operands++];
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i.op[i.operands].imms = exp;
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i.types[i.operands] = imm8;
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i.operands++;
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{
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/* When there is no immediate operand, generate an 8bit
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immediate operand to encode the first operand. */
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exp = &im_expressions[i.imm_operands++];
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i.op[i.operands].imms = exp;
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i.types[i.operands] = imm8;
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i.operands++;
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gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
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exp->X_op = O_constant;
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exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
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gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
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exp->X_op = O_constant;
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exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
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gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
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}
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else
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{
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unsigned int imm_slot;
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{
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unsigned int imm_slot;
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gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
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if (i.tm.opcode_modifier.immext)
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{
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/* When ImmExt is set, the immediate byte is the last
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operand. */
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imm_slot = i.operands - 1;
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source--;
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reg_slot--;
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}
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else
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{
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imm_slot = 0;
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if (i.tm.opcode_modifier.immext)
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{
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/* When ImmExt is set, the immediate byte is the last
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operand. */
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imm_slot = i.operands - 1;
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source--;
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reg_slot--;
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}
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else
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{
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imm_slot = 0;
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/* Turn on Imm8 so that output_imm will generate it. */
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i.types[imm_slot].bitfield.imm8 = 1;
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}
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/* Turn on Imm8 so that output_imm will generate it. */
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i.types[imm_slot].bitfield.imm8 = 1;
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}
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gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
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i.op[imm_slot].imms->X_add_number
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|= register_number (i.op[reg_slot].regs) << 4;
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gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
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i.op[imm_slot].imms->X_add_number
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|= register_number (i.op[reg_slot].regs) << 4;
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gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
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}
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}
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gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
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i.vex.register_specifier = i.op[nds].regs;
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