Fix bit/bif instructions.
sim/aarch64/ * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. sim/testsuite/sim/aarch64 * bit.s: New.
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@ -1,5 +1,9 @@
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2017-02-14 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
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2. Move test_false if inside loop. Fix logic for computing result
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stored to vd.
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* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
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(do_vec_LDn_single, do_vec_STn_single): New.
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(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
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@ -4085,17 +4085,17 @@ do_vec_bit (sim_cpu *cpu)
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NYI_assert (15, 10, 0x07);
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (test_false)
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for (i = 0; i < (full ? 4 : 2); i++)
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{
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for (i = 0; i < (full ? 16 : 8); i++)
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if (aarch64_get_vec_u32 (cpu, vn, i) == 0)
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aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vm, i));
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}
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else
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{
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for (i = 0; i < (full ? 16 : 8); i++)
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if (aarch64_get_vec_u32 (cpu, vn, i) != 0)
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aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vm, i));
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uint32_t vd_val = aarch64_get_vec_u32 (cpu, vd, i);
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uint32_t vn_val = aarch64_get_vec_u32 (cpu, vn, i);
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uint32_t vm_val = aarch64_get_vec_u32 (cpu, vm, i);
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if (test_false)
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aarch64_set_vec_u32 (cpu, vd, i,
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(vd_val & vm_val) | (vn_val & ~vm_val));
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else
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aarch64_set_vec_u32 (cpu, vd, i,
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(vd_val & ~vm_val) | (vn_val & vm_val));
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}
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}
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@ -1,5 +1,7 @@
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2017-02-14 Jim Wilson <jim.wilson@linaro.org>
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* bit.s: New.
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* ldn_single.s: New.
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* ldnr.s: New.
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* stn_single.s: New.
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@ -0,0 +1,91 @@
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# mach: aarch64
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# Check the bitwise vector instructions: bif, bit, bsl, eor.
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.include "testutils.inc"
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.data
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.align 4
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inputa:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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inputb:
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.word 0x40302010
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.word 0x80706050
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.word 0xc0b0a090
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.word 0x01f0e0d0
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mask:
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.word 0xFF00FF00
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.word 0x00FF00FF
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.word 0xF0F0F0F0
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.word 0x0F0F0F0F
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start
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adrp x0, inputa
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ldr q0, [x0, #:lo12:inputa]
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adrp x0, inputb
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ldr q1, [x0, #:lo12:inputb]
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adrp x0, mask
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ldr q2, [x0, #:lo12:mask]
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mov v3.8b, v0.8b
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bif v3.8b, v1.8b, v2.8b
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addv b4, v3.8b
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mov x1, v4.d[0]
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cmp x1, #306
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bne .Lfailure
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mov v3.16b, v0.16b
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bif v3.16b, v1.16b, v2.16b
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addv b4, v3.16b
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mov x1, v4.d[0]
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cmp x1, #1020
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bne .Lfailure
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mov v3.8b, v0.8b
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bit v3.8b, v1.8b, v2.8b
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addv b4, v3.8b
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mov x1, v4.d[0]
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cmp x1, #306
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bne .Lfailure
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mov v3.16b, v0.16b
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bit v3.16b, v1.16b, v2.16b
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addv b4, v3.16b
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mov x1, v4.d[0]
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cmp x1, #1037
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bne .Lfailure
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mov v3.8b, v2.8b
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bsl v3.8b, v0.8b, v1.8b
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addv b4, v3.8b
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mov x1, v4.d[0]
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cmp x1, #306
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bne .Lfailure
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mov v3.16b, v2.16b
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bsl v3.16b, v0.16b, v1.16b
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addv b4, v3.16b
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mov x1, v4.d[0]
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cmp x1, #1020
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bne .Lfailure
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mov v3.8b, v0.8b
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eor v3.8b, v1.8b, v2.8b
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addv b4, v3.8b
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mov x1, v4.d[0]
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cmp x1, #1020
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bne .Lfailure
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mov v3.16b, v0.16b
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eor v3.16b, v1.16b, v2.16b
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addv b4, v3.16b
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mov x1, v4.d[0]
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cmp x1, #2039
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bne .Lfailure
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pass
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.Lfailure:
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fail
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