MIPS is always multi-arch enabled.
This commit is contained in:
Andrew Cagney
parent
b0069a1775
commit
bf64bfd6ba
@ -1,12 +1,33 @@
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Thu Jun 8 15:26:44 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* config/mips/tm-mips.h (GDB_MULTI_ARCH): Define as 1.
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(CALL_DUMMY, TARGET_BYTE_ORDER_SELECTABLE_P,
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COERCE_FLOAT_TO_DOUBLE): Delete.
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* config/mips/tm-vr5000el.h, config/mips/tm-vr5000.h,
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config/mips/tm-vr4xxxel.h, config/mips/tm-vr4xxx.h,
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config/mips/tm-vr4100.h, config/mips/tm-tx39l.h
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config/mips/tm-tx39.h, config/mips/tm-irix5.h: Delete
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GDB_MULTI_ARCH.
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* config/mips/tm-mips64.h (TARGET_LONG_BIT, TARGET_LONG_LONG_BIT,
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TARGET_PTR_BIT): Delete definitions.
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* config/mips/tm-vr5000el.h, config/mips/tm-vr5000.h,
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config/mips/tm-tx39l.h, config/mips/tm-vr4100.h,
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config/mips/tm-tx39.h: Delete definition of MIPS_EABI.
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* mips-tdep.c (mips_gdbarch_init): Use the ISA to determine the
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ABI. If all else fails, assume O32.
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* TODO, NEWS: Update. Mention MIPS is multi-arch.
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Thu Jun 8 14:23:12 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* config/mips/tm-vr4xxxel.h, config/mips/tm-vr4xxx.h,
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config/mips/tm-vr4100.h, config/mips/tm-tx39l.h,
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config/mips/tm-tx39.h: Delete definition of
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MIPS_DEFAULT_FPU. Enable multi-arch.
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MIPS_DEFAULT_FPU_TYPE. Enable multi-arch.
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* mips-tdep.c: (mips_gdbarch_init): The bfd_mach_mips3900 has no
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FPU.
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FPU. bfd_mach_mips4650 FPU is single precision.
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* config/mips/tm-mips.h (MIPS_FPU_SINGLE_REGSIZE):
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(MIPS_FPU_DOUBLE_REGSIZE): Move from here.
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* mips-tdep.c: To here. Change to an enum.
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15
gdb/NEWS
15
gdb/NEWS
@ -8,7 +8,20 @@
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Alpha FreeBSD alpha*-*-freebsd*
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x86 FreeBSD 3.x and 4.x i[3456]86*-freebsd[34]*
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FreeBSD versions before 2.2 are no longer supported.
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* New targets
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* OBSOLETE configurations
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x86 FreeBSD before 2.2 i[3456]86*-freebsd{1,2.[01]}*,
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* Deleted configurations
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* Other news:
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* All MIPS configurations are multi-arched.
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Multi-arch support is enabled for all MIPS configurations.
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*** Changes in GDB 5.0:
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10
gdb/TODO
10
gdb/TODO
@ -328,6 +328,10 @@ http://sourceware.cygnus.com/ml/gdb-patches/2000-06/msg00062.html
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See also ``Fix implementation of ``target xxx''.'' below.
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--
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IRIX 3.x support is probably broken.
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--
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New Features and Fixes
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@ -971,6 +975,12 @@ name.
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--
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Make MIPS pure multi-arch.
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It is only at the multi-arch enabled stage.
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--
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Truly multi-arch.
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Enable the code to recognize --enable-targets=.... like BINUTILS does.
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@ -18,17 +18,6 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* If we're being built for n32, enable multi-arch. */
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/* FIXME: cagney/2000-04-04: Testing the _MIPS_SIM_NABI32 and
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_MIPS_SIM in a tm-*.h file is simply wrong! Those are
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host-dependant macros (provided by /usr/include) and stop any
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chance of the target being cross compiled */
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#if 0 && defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
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/* FIXME: Don't enable multi-arch for IRIX/n32. The test
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``gdb.base/corefile.exp: up in corefile.exp'' fails. */
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#define GDB_MULTI_ARCH 1
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#endif
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#include "mips/tm-irix3.h"
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/* FIXME: cagney/2000-04-04: Testing the _MIPS_SIM_NABI32 and
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@ -24,6 +24,8 @@
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#ifndef TM_MIPS_H
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#define TM_MIPS_H 1
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#define GDB_MULTI_ARCH 1
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struct frame_info;
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struct symbol;
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struct type;
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@ -407,10 +409,6 @@ extern void mips_push_dummy_frame (void);
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#define POP_FRAME mips_pop_frame()
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extern void mips_pop_frame (void);
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#if !GDB_MULTI_ARCH
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#define CALL_DUMMY { 0 }
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#endif
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#define CALL_DUMMY_START_OFFSET (0)
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#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
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@ -487,22 +485,6 @@ extern struct frame_info *setup_arbitrary_frame (int, CORE_ADDR *);
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#define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
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#if !GDB_MULTI_ARCH
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/* If the current gcc for for this target does not produce correct debugging
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information for float parameters, both prototyped and unprototyped, then
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define this macro. This forces gdb to always assume that floats are
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passed as doubles and then converted in the callee.
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For the mips chip, it appears that the debug info marks the parameters as
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floats regardless of whether the function is prototyped, but the actual
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values are passed as doubles for the non-prototyped case and floats for
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the prototyped case. Thus we choose to make the non-prototyped case work
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for C and break the prototyped case, since the non-prototyped case is
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probably much more common. (FIXME). */
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#define COERCE_FLOAT_TO_DOUBLE(formal, actual) (current_language -> la_language == language_c)
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#endif
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/* Select the default mips disassembler */
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#define TM_PRINT_INSN_MACH 0
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@ -579,9 +561,3 @@ extern void mips_set_processor_type_command (char *, int);
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/* MIPS sign extends addresses */
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#define POINTER_TO_ADDRESS(TYPE,BUF) (signed_pointer_to_address (TYPE, BUF))
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#define ADDRESS_TO_POINTER(TYPE,BUF,ADDR) (address_to_signed_pointer (TYPE, BUF, ADDR))
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/* MIPS is always bi-endian */
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#if !GDB_MULTI_ARCH
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#define TARGET_BYTE_ORDER_SELECTABLE_P 1
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#endif
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@ -35,21 +35,5 @@
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#define OP_LDFPR 065 /* ldc1 */
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#define OP_LDGPR 067 /* ld */
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#if defined(MIPS_EABI) && (MIPS_EABI != 0)
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/* Define sizes for 64-bit data types, allow specific targets to override
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these values. Doing so may violate the strict EABI, but it's necessary
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for some MIPS III and MIPS IV machines that want 64bit longs, but 32bit
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pointers. */
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#ifndef TARGET_LONG_BIT
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#define TARGET_LONG_BIT 64
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#endif
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#ifndef TARGET_LONG_LONG_BIT
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#define TARGET_LONG_LONG_BIT 64
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#endif
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#ifndef TARGET_PTR_BIT
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#define TARGET_PTR_BIT 64
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#endif
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#endif /* MIPS_EABI */
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/* Get the basic MIPS definitions. */
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#include "tm-mips.h"
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@ -17,9 +17,6 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define GDB_MULTI_ARCH 1
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#define MIPS_EABI 1
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#include "mips/tm-bigmips.h"
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#undef MIPS_REGISTER_NAMES
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@ -17,9 +17,6 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define GDB_MULTI_ARCH 1
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#define MIPS_EABI 1
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#include "mips/tm-mips.h"
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#undef MIPS_REGISTER_NAMES
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@ -17,7 +17,4 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define MIPS_EABI 1
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#define TARGET_PTR_BIT 64
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#include "mips/tm-bigmips64.h"
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@ -17,6 +17,4 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define GDB_MULTI_ARCH 1
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#include "mips/tm-bigmips64.h"
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@ -17,6 +17,4 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define GDB_MULTI_ARCH 1
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#include "mips/tm-mips64.h"
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@ -17,7 +17,4 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define GDB_MULTI_ARCH 1
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#define MIPS_EABI 1
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#include "mips/tm-bigmips64.h"
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@ -17,7 +17,4 @@
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define GDB_MULTI_ARCH 1
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#define MIPS_EABI 1
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#include "mips/tm-mips64.h"
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@ -1,5 +1,8 @@
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/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
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Copyright 1988-1999, Free Software Foundation, Inc.
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Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
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1997, 1998, 1999, 2000, Free Software Foundation, Inc.
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Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
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and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
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@ -3868,10 +3871,28 @@ mips_gdbarch_init (info, arches)
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mips_abi = MIPS_ABI_UNKNOWN;
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break;
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}
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/* Try the architecture for any hint of the corect ABI */
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if (mips_abi == MIPS_ABI_UNKNOWN
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&& info.bfd_arch_info != NULL
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&& info.bfd_arch_info->arch == bfd_arch_mips)
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{
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switch (info.bfd_arch_info->mach)
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{
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case bfd_mach_mips3900:
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mips_abi = MIPS_ABI_EABI32;
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break;
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case bfd_mach_mips4100:
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case bfd_mach_mips5000:
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mips_abi = MIPS_ABI_EABI64;
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break;
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}
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}
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#ifdef MIPS_DEFAULT_ABI
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if (mips_abi == MIPS_ABI_UNKNOWN)
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mips_abi = MIPS_DEFAULT_ABI;
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#endif
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if (mips_abi == MIPS_ABI_UNKNOWN)
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mips_abi = MIPS_ABI_O32;
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/* try to find a pre-existing architecture */
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for (arches = gdbarch_list_lookup_by_info (arches, &info);
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@ -4043,6 +4064,9 @@ mips_gdbarch_init (info, arches)
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case bfd_mach_mips4111:
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tdep->mips_fpu_type = MIPS_FPU_NONE;
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break;
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case bfd_mach_mips4650:
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tdep->mips_fpu_type = MIPS_FPU_SINGLE;
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break;
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default:
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tdep->mips_fpu_type = MIPS_FPU_DOUBLE;
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break;
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