Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.
sim/aarch64/ * cpustate.c: Include math.h. (aarch64_set_FP_float): Use signbit to check for signed zero. (aarch64_set_FP_double): Likewise. * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. (fmaxnm): Use isnan instead of fpclassify. (fminnm, dmaxnm, dminnm): Likewise. (do_vec_MLS): Reverse order of subtraction operands. (dexSimpleFPCondSelect): Call aarch64_get_FP_double or aarch64_get_FP_float to get source register contents. (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in raise_exception calls. sim/testsuite/sim/aarch64/ * fcsel.s: New. * fcvtz.s: New. * fminnm.s: New. * mls.s: New. * mul.s: New.
This commit is contained in:
Jim Wilson
parent
6ed0191f65
commit
c0386d4d54
@ -1,3 +1,22 @@
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2017-01-04 Jim Wilson <jim.wilson@linaro.org>
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* cpustate.c: Include math.h.
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(aarch64_set_FP_float): Use signbit to check for signed zero.
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(aarch64_set_FP_double): Likewise.
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* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
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(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
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args same size as third arg.
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(fmaxnm): Use isnan instead of fpclassify.
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(fminnm, dmaxnm, dminnm): Likewise.
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(do_vec_MLS): Reverse order of subtraction operands.
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(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
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aarch64_get_FP_float to get source register contents.
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(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
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DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
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DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
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(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
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raise_exception calls.
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2016-12-21 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
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@ -20,6 +20,7 @@
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <stdio.h>
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#include <math.h>
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#include "sim-main.h"
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#include "cpustate.h"
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@ -369,7 +370,9 @@ aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
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void
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aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
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{
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if (val != cpu->fr[reg].s)
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if (val != cpu->fr[reg].s
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/* Handle +/- zero. */
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|| signbit (val) != signbit (cpu->fr[reg].s))
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{
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FRegister v;
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@ -385,7 +388,9 @@ aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
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void
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aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
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{
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if (val != cpu->fr[reg].d)
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if (val != cpu->fr[reg].d
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/* Handle +/- zero. */
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|| signbit (val) != signbit (cpu->fr[reg].d))
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{
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FRegister v;
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@ -3221,7 +3221,8 @@ do_vec_MOV_immediate (sim_cpu *cpu)
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case 0x8: /* 16-bit, no shift. */
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for (i = 0; i < (full ? 8 : 4); i++)
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aarch64_set_vec_u16 (cpu, vd, i, val);
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/* Fall through. */
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break;
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case 0xd: /* 32-bit, mask shift by 16. */
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val <<= 8;
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val |= 0xFF;
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@ -3724,15 +3725,15 @@ do_vec_mul (sim_cpu *cpu)
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switch (INSTR (23, 22))
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{
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case 0:
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DO_VEC_WIDENING_MUL (full ? 16 : 8, uint16_t, u8, u16);
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DO_VEC_WIDENING_MUL (full ? 16 : 8, uint8_t, u8, u8);
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return;
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case 1:
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DO_VEC_WIDENING_MUL (full ? 8 : 4, uint32_t, u16, u32);
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DO_VEC_WIDENING_MUL (full ? 8 : 4, uint16_t, u16, u16);
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return;
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case 2:
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DO_VEC_WIDENING_MUL (full ? 4 : 2, uint64_t, u32, u64);
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DO_VEC_WIDENING_MUL (full ? 4 : 2, uint32_t, u32, u32);
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return;
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case 3:
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@ -3831,13 +3832,13 @@ do_vec_MLA (sim_cpu *cpu)
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static float
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fmaxnm (float a, float b)
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{
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if (fpclassify (a) == FP_NORMAL)
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if (! isnan (a))
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{
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if (fpclassify (b) == FP_NORMAL)
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if (! isnan (b))
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return a > b ? a : b;
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return a;
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}
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else if (fpclassify (b) == FP_NORMAL)
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else if (! isnan (b))
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return b;
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return a;
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}
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@ -3845,13 +3846,13 @@ fmaxnm (float a, float b)
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static float
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fminnm (float a, float b)
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{
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if (fpclassify (a) == FP_NORMAL)
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if (! isnan (a))
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{
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if (fpclassify (b) == FP_NORMAL)
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if (! isnan (b))
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return a < b ? a : b;
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return a;
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}
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else if (fpclassify (b) == FP_NORMAL)
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else if (! isnan (b))
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return b;
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return a;
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}
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@ -3859,13 +3860,13 @@ fminnm (float a, float b)
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static double
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dmaxnm (double a, double b)
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{
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if (fpclassify (a) == FP_NORMAL)
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if (! isnan (a))
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{
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if (fpclassify (b) == FP_NORMAL)
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if (! isnan (b))
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return a > b ? a : b;
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return a;
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}
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else if (fpclassify (b) == FP_NORMAL)
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else if (! isnan (b))
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return b;
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return a;
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}
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@ -3873,13 +3874,13 @@ dmaxnm (double a, double b)
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static double
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dminnm (double a, double b)
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{
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if (fpclassify (a) == FP_NORMAL)
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if (! isnan (a))
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{
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if (fpclassify (b) == FP_NORMAL)
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if (! isnan (b))
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return a < b ? a : b;
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return a;
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}
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else if (fpclassify (b) == FP_NORMAL)
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else if (! isnan (b))
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return b;
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return a;
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}
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@ -6346,25 +6347,25 @@ do_vec_MLS (sim_cpu *cpu)
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case 0:
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for (i = 0; i < (full ? 16 : 8); i++)
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aarch64_set_vec_u8 (cpu, vd, i,
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(aarch64_get_vec_u8 (cpu, vn, i)
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* aarch64_get_vec_u8 (cpu, vm, i))
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- aarch64_get_vec_u8 (cpu, vd, i));
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aarch64_get_vec_u8 (cpu, vd, i)
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- (aarch64_get_vec_u8 (cpu, vn, i)
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* aarch64_get_vec_u8 (cpu, vm, i)));
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return;
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case 1:
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for (i = 0; i < (full ? 8 : 4); i++)
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aarch64_set_vec_u16 (cpu, vd, i,
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(aarch64_get_vec_u16 (cpu, vn, i)
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* aarch64_get_vec_u16 (cpu, vm, i))
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- aarch64_get_vec_u16 (cpu, vd, i));
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aarch64_get_vec_u16 (cpu, vd, i)
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- (aarch64_get_vec_u16 (cpu, vn, i)
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* aarch64_get_vec_u16 (cpu, vm, i)));
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return;
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case 2:
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for (i = 0; i < (full ? 4 : 2); i++)
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aarch64_set_vec_u32 (cpu, vd, i,
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(aarch64_get_vec_u32 (cpu, vn, i)
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* aarch64_get_vec_u32 (cpu, vm, i))
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- aarch64_get_vec_u32 (cpu, vd, i));
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aarch64_get_vec_u32 (cpu, vd, i)
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- (aarch64_get_vec_u32 (cpu, vn, i)
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* aarch64_get_vec_u32 (cpu, vm, i)));
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return;
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default:
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@ -7463,9 +7464,11 @@ dexSimpleFPCondSelect (sim_cpu *cpu)
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TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
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if (INSTR (22, 22))
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aarch64_set_FP_double (cpu, sd, set ? sn : sm);
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aarch64_set_FP_double (cpu, sd, (set ? aarch64_get_FP_double (cpu, sn)
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: aarch64_get_FP_double (cpu, sm)));
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else
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aarch64_set_FP_float (cpu, sd, set ? sn : sm);
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aarch64_set_FP_float (cpu, sd, (set ? aarch64_get_FP_float (cpu, sn)
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: aarch64_get_FP_float (cpu, sm)));
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}
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/* Store 32 bit unscaled signed 9 bit. */
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@ -8117,6 +8120,17 @@ static const float FLOAT_LONG_MIN = (float) LONG_MIN;
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static const double DOUBLE_LONG_MAX = (double) LONG_MAX;
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static const double DOUBLE_LONG_MIN = (double) LONG_MIN;
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#define UINT_MIN 0
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#define ULONG_MIN 0
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static const float FLOAT_UINT_MAX = (float) UINT_MAX;
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static const float FLOAT_UINT_MIN = (float) UINT_MIN;
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static const double DOUBLE_UINT_MAX = (double) UINT_MAX;
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static const double DOUBLE_UINT_MIN = (double) UINT_MIN;
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static const float FLOAT_ULONG_MAX = (float) ULONG_MAX;
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static const float FLOAT_ULONG_MIN = (float) ULONG_MIN;
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static const double DOUBLE_ULONG_MAX = (double) ULONG_MAX;
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static const double DOUBLE_ULONG_MIN = (double) ULONG_MIN;
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/* Check for FP exception conditions:
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NaN raises IO
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Infinity raises IO
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@ -8262,7 +8276,7 @@ do_fcvtzu (sim_cpu *cpu)
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/* Do not raise an exception if we have reached ULONG_MAX. */
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if (value != (1UL << 63))
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RAISE_EXCEPTIONS (d, value, DOUBLE, LONG);
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RAISE_EXCEPTIONS (d, value, DOUBLE, ULONG);
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aarch64_set_reg_u64 (cpu, rd, NO_SP, value);
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}
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@ -8273,7 +8287,7 @@ do_fcvtzu (sim_cpu *cpu)
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/* Do not raise an exception if we have reached ULONG_MAX. */
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if (value != (1UL << 63))
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RAISE_EXCEPTIONS (f, value, FLOAT, LONG);
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RAISE_EXCEPTIONS (f, value, FLOAT, ULONG);
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aarch64_set_reg_u64 (cpu, rd, NO_SP, value);
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}
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@ -8290,7 +8304,7 @@ do_fcvtzu (sim_cpu *cpu)
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value = (uint32_t) d;
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/* Do not raise an exception if we have reached UINT_MAX. */
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if (value != (1UL << 31))
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RAISE_EXCEPTIONS (d, value, DOUBLE, INT);
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RAISE_EXCEPTIONS (d, value, DOUBLE, UINT);
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}
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else
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{
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@ -8299,7 +8313,7 @@ do_fcvtzu (sim_cpu *cpu)
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value = (uint32_t) f;
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/* Do not raise an exception if we have reached UINT_MAX. */
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if (value != (1UL << 31))
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RAISE_EXCEPTIONS (f, value, FLOAT, INT);
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RAISE_EXCEPTIONS (f, value, FLOAT, UINT);
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}
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aarch64_set_reg_u64 (cpu, rd, NO_SP, value);
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@ -1,3 +1,11 @@
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2017-01-04 Jim Wilson <jim.wilson@linaro.org>
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* fcsel.s: New.
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* fcvtz.s: New.
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* fminnm.s: New.
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* mls.s: New.
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* mul.s: New.
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2016-12-21 Jim Wilson <jim.wilson@linaro.org>
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* fcmp.s: New.
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53
sim/testsuite/sim/aarch64/fcsel.s
Normal file
53
sim/testsuite/sim/aarch64/fcsel.s
Normal file
@ -0,0 +1,53 @@
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# mach: aarch64
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# Check the FP Conditional Select instruction: fcsel.
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# Check 1/1 eq/neg, and 1/2 lt/gt.
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.include "testutils.inc"
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start
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fmov s0, #1.0
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fmov s1, #1.0
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fmov s2, #-1.0
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fcmp s0, s1
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fcsel s3, s0, s2, eq
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fcmp s3, s0
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bne .Lfailure
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fcsel s3, s0, s2, ne
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fcmp s3, s2
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bne .Lfailure
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fmov s0, #1.0
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fmov s1, #2.0
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fcmp s0, s1
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fcsel s3, s0, s2, lt
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fcmp s3, s0
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bne .Lfailure
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fcsel s3, s0, s2, gt
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fcmp s3, s2
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bne .Lfailure
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fmov d0, #1.0
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fmov d1, #1.0
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fmov d2, #-1.0
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fcmp d0, d1
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fcsel d3, d0, d2, eq
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fcmp d3, d0
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bne .Lfailure
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fcsel d3, d0, d2, ne
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fcmp d3, d2
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bne .Lfailure
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fmov d0, #1.0
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fmov d1, #2.0
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fcmp d0, d1
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fcsel d3, d0, d2, lt
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fcmp d3, d0
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bne .Lfailure
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fcsel d3, d0, d2, gt
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fcmp d3, d2
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bne .Lfailure
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pass
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.Lfailure:
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fail
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202
sim/testsuite/sim/aarch64/fcvtz.s
Normal file
202
sim/testsuite/sim/aarch64/fcvtz.s
Normal file
@ -0,0 +1,202 @@
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# mach: aarch64
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# Check the FP convert to int round toward zero instructions: fcvtszs32,
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# fcvtszs, fcvtszd32, fcvtszd, fcvtzu.
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# For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN.
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# For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN.
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# For 32-bit unsigned convert, test values 1.5, INT_MAX, and UINT_MAX.
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# For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX.
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.data
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fm1p5:
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.word 3217031168
|
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fimax:
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.word 1325400064
|
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fimin:
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.word 3472883712
|
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flmax:
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.word 1593835520
|
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flmin:
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.word 3741319168
|
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f1p5:
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.word 1069547520
|
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fuimax:
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.word 1333788672
|
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fulmax:
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.word 1602224128
|
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|
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dm1p5:
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.word 0
|
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.word -1074266112
|
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dimax:
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.word 4290772992
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.word 1105199103
|
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dimin:
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.word 0
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.word -1042284544
|
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dlmax:
|
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.word 0
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.word 1138753536
|
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dlmin:
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.word 0
|
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.word -1008730112
|
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d1p5:
|
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.word 0
|
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.word 1073217536
|
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duimax:
|
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.word 4292870144
|
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.word 1106247679
|
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dulmax:
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.word 0
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.word 1139802112
|
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.include "testutils.inc"
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start
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adrp x0, fm1p5
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ldr s0, [x0, #:lo12:fm1p5]
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fcvtzs w1, s0
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cmp w1, #-1
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bne .Lfailure
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adrp x0, fimax
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ldr s0, [x0, #:lo12:fimax]
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fcvtzs w1, s0
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mov w2, #0x7fffffff
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cmp w1, w2
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bne .Lfailure
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adrp x0, fimin
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ldr s0, [x0, #:lo12:fimin]
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fcvtzs w1, s0
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mov w2, #0x80000000
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cmp w1, w2
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bne .Lfailure
|
||||
|
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adrp x0, fm1p5
|
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ldr s0, [x0, #:lo12:fm1p5]
|
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fcvtzs x1, s0
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cmp x1, #-1
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bne .Lfailure
|
||||
adrp x0, flmax
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ldr s0, [x0, #:lo12:flmax]
|
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fcvtzs x1, s0
|
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mov x2, #0x7fffffffffffffff
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cmp x1, x2
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bne .Lfailure
|
||||
adrp x0, flmin
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ldr s0, [x0, #:lo12:flmin]
|
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fcvtzs x1, s0
|
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mov x2, #0x8000000000000000
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cmp x1, x2
|
||||
bne .Lfailure
|
||||
|
||||
adrp x0, dm1p5
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||||
ldr d0, [x0, #:lo12:dm1p5]
|
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fcvtzs w1, d0
|
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cmp w1, #-1
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bne .Lfailure
|
||||
adrp x0, dimax
|
||||
ldr d0, [x0, #:lo12:dimax]
|
||||
fcvtzs w1, d0
|
||||
mov w2, #0x7fffffff
|
||||
cmp w1, w2
|
||||
bne .Lfailure
|
||||
adrp x0, dimin
|
||||
ldr d0, [x0, #:lo12:dimin]
|
||||
fcvtzs w1, d0
|
||||
mov w2, #0x80000000
|
||||
cmp w1, w2
|
||||
bne .Lfailure
|
||||
|
||||
adrp x0, dm1p5
|
||||
ldr d0, [x0, #:lo12:dm1p5]
|
||||
fcvtzs x1, d0
|
||||
cmp x1, #-1
|
||||
bne .Lfailure
|
||||
adrp x0, dlmax
|
||||
ldr d0, [x0, #:lo12:dlmax]
|
||||
fcvtzs x1, d0
|
||||
mov x2, #0x7fffffffffffffff
|
||||
cmp x1, x2
|
||||
bne .Lfailure
|
||||
adrp x0, dlmin
|
||||
ldr d0, [x0, #:lo12:dlmin]
|
||||
fcvtzs x1, d0
|
||||
mov x2, #0x8000000000000000
|
||||
cmp x1, x2
|
||||
bne .Lfailure
|
||||
|
||||
adrp x0, f1p5
|
||||
ldr s0, [x0, #:lo12:f1p5]
|
||||
fcvtzu w1, s0
|
||||
cmp w1, #1
|
||||
bne .Lfailure
|
||||
adrp x0, fimax
|
||||
ldr s0, [x0, #:lo12:fimax]
|
||||
fcvtzu w1, s0
|
||||
mov w2, #0x80000000
|
||||
cmp w1, w2
|
||||
bne .Lfailure
|
||||
adrp x0, fuimax
|
||||
ldr s0, [x0, #:lo12:fuimax]
|
||||
fcvtzu w1, s0
|
||||
mov w2, #0xffffffff
|
||||
cmp w1, w2
|
||||
bne .Lfailure
|
||||
|
||||
adrp x0, f1p5
|
||||
ldr s0, [x0, #:lo12:f1p5]
|
||||
fcvtzu x1, s0
|
||||
cmp x1, #1
|
||||
bne .Lfailure
|
||||
adrp x0, flmax
|
||||
ldr s0, [x0, #:lo12:flmax]
|
||||
fcvtzu x1, s0
|
||||
mov x2, #0x8000000000000000
|
||||
cmp x1, x2
|
||||
bne .Lfailure
|
||||
adrp x0, fulmax
|
||||
ldr s0, [x0, #:lo12:fulmax]
|
||||
fcvtzu x1, s0
|
||||
mov x2, #0xffffffffffffffff
|
||||
cmp x1, x2
|
||||
bne .Lfailure
|
||||
|
||||
adrp x0, d1p5
|
||||
ldr d0, [x0, #:lo12:d1p5]
|
||||
fcvtzu w1, d0
|
||||
cmp w1, #1
|
||||
bne .Lfailure
|
||||
adrp x0, dimax
|
||||
ldr d0, [x0, #:lo12:dimax]
|
||||
fcvtzu w1, d0
|
||||
mov w2, #0x7fffffff
|
||||
cmp w1, w2
|
||||
bne .Lfailure
|
||||
adrp x0, duimax
|
||||
ldr d0, [x0, #:lo12:duimax]
|
||||
fcvtzu w1, d0
|
||||
mov w2, #0xffffffff
|
||||
cmp w1, w2
|
||||
bne .Lfailure
|
||||
|
||||
adrp x0, d1p5
|
||||
ldr d0, [x0, #:lo12:d1p5]
|
||||
fcvtzu x1, d0
|
||||
cmp x1, #1
|
||||
bne .Lfailure
|
||||
adrp x0, dlmax
|
||||
ldr d0, [x0, #:lo12:dlmax]
|
||||
fcvtzu x1, d0
|
||||
mov x2, #0x8000000000000000
|
||||
cmp x1, x2
|
||||
bne .Lfailure
|
||||
adrp x0, dulmax
|
||||
ldr d0, [x0, #:lo12:dulmax]
|
||||
fcvtzu x1, d0
|
||||
mov x2, #0xffffffffffffffff
|
||||
cmp x1, x2
|
||||
bne .Lfailure
|
||||
|
||||
pass
|
||||
.Lfailure:
|
||||
fail
|
||||
82
sim/testsuite/sim/aarch64/fminnm.s
Normal file
82
sim/testsuite/sim/aarch64/fminnm.s
Normal file
@ -0,0 +1,82 @@
|
||||
# mach: aarch64
|
||||
|
||||
# Check the FP min/max number instructions: fminnm, fmaxnm, dminnm, dmaxnm.
|
||||
# For min, check 2/1, 1/0, -1/-Inf.
|
||||
# For max, check 1/2, -1/0, 1/+inf.
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
start
|
||||
fmov s0, #2.0
|
||||
fmov s1, #1.0
|
||||
fminnm s2, s0, s1
|
||||
fcmp s2, s1
|
||||
bne .Lfailure
|
||||
fmov d0, #2.0
|
||||
fmov d1, #1.0
|
||||
fminnm d2, d0, d1
|
||||
fcmp d2, d1
|
||||
bne .Lfailure
|
||||
|
||||
fmov s0, #1.0
|
||||
fmov s1, wzr
|
||||
fminnm s2, s0, s1
|
||||
fcmp s2, s1
|
||||
bne .Lfailure
|
||||
fmov d0, #1.0
|
||||
fmov d1, xzr
|
||||
fminnm d2, d0, d1
|
||||
fcmp d2, d1
|
||||
bne .Lfailure
|
||||
|
||||
fmov s0, #-1.0
|
||||
fmov s1, wzr
|
||||
fdiv s1, s0, s1
|
||||
fminnm s2, s0, s1
|
||||
fcmp s2, s1
|
||||
bne .Lfailure
|
||||
fmov d0, #-1.0
|
||||
fmov d1, xzr
|
||||
fdiv d1, d0, d1
|
||||
fminnm d1, d0, d1
|
||||
fcmp d0, d0
|
||||
bne .Lfailure
|
||||
|
||||
fmov s0, #1.0
|
||||
fmov s1, #2.0
|
||||
fmaxnm s2, s0, s1
|
||||
fcmp s2, s1
|
||||
bne .Lfailure
|
||||
fmov d0, #1.0
|
||||
fmov d1, #2.0
|
||||
fmaxnm d2, d0, d1
|
||||
fcmp d2, d1
|
||||
bne .Lfailure
|
||||
|
||||
fmov s0, #-1.0
|
||||
fmov s1, wzr
|
||||
fmaxnm s2, s0, s1
|
||||
fcmp s2, s1
|
||||
bne .Lfailure
|
||||
fmov d0, #-1.0
|
||||
fmov d1, xzr
|
||||
fmaxnm d2, d0, d1
|
||||
fcmp d2, d1
|
||||
bne .Lfailure
|
||||
|
||||
fmov s0, #1.0
|
||||
fmov s1, wzr
|
||||
fdiv s1, s0, s1
|
||||
fmaxnm s2, s0, s1
|
||||
fcmp s2, s1
|
||||
bne .Lfailure
|
||||
fmov d0, #1.0
|
||||
fmov d1, xzr
|
||||
fdiv d1, d0, d1
|
||||
fmaxnm d1, d0, d1
|
||||
fcmp d0, d0
|
||||
bne .Lfailure
|
||||
|
||||
pass
|
||||
.Lfailure:
|
||||
fail
|
||||
103
sim/testsuite/sim/aarch64/mls.s
Normal file
103
sim/testsuite/sim/aarch64/mls.s
Normal file
@ -0,0 +1,103 @@
|
||||
# mach: aarch64
|
||||
|
||||
# Check the vector multiply subtract instruction: mls.
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
input:
|
||||
.word 0x04030201
|
||||
.word 0x08070605
|
||||
.word 0x0c0b0a09
|
||||
.word 0x100f0e0d
|
||||
m8b:
|
||||
.word 0xf1f8fd00
|
||||
.word 0xc1d0dde8
|
||||
m16b:
|
||||
.word 0xf1f8fd00
|
||||
.word 0xc1d0dde8
|
||||
.word 0x71889db0
|
||||
.word 0x01203d58
|
||||
m4h:
|
||||
.word 0xe7f8fc00
|
||||
.word 0x8fd0c3e8
|
||||
m8h:
|
||||
.word 0xe7f8fc00
|
||||
.word 0x8fd0c3e8
|
||||
.word 0xf7884bb0
|
||||
.word 0x1f209358
|
||||
m2s:
|
||||
.word 0xebf5fc00
|
||||
.word 0x5b95c3e8
|
||||
m4s:
|
||||
.word 0xebf5fc00
|
||||
.word 0x5b95c3e8
|
||||
.word 0x4ad54bb0
|
||||
.word 0xb9b49358
|
||||
|
||||
start
|
||||
adrp x0, input
|
||||
ldr q0, [x0, #:lo12:input]
|
||||
|
||||
movi v1.8b, #1
|
||||
mls v1.8b, v0.8b, v0.8b
|
||||
mov x1, v1.d[0]
|
||||
adrp x3, m8b
|
||||
ldr x4, [x3, #:lo12:m8b]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
|
||||
movi v1.16b, #1
|
||||
mls v1.16b, v0.16b, v0.16b
|
||||
mov x1, v1.d[0]
|
||||
mov x2, v1.d[1]
|
||||
adrp x3, m16b
|
||||
ldr x4, [x3, #:lo12:m16b]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
ldr x5, [x3, #:lo12:m16b+8]
|
||||
cmp x2, x5
|
||||
bne .Lfailure
|
||||
|
||||
movi v1.4h, #1
|
||||
mls v1.4h, v0.4h, v0.4h
|
||||
mov x1, v1.d[0]
|
||||
adrp x3, m4h
|
||||
ldr x4, [x3, #:lo12:m4h]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
|
||||
movi v1.8h, #1
|
||||
mls v1.8h, v0.8h, v0.8h
|
||||
mov x1, v1.d[0]
|
||||
mov x2, v1.d[1]
|
||||
adrp x3, m8h
|
||||
ldr x4, [x3, #:lo12:m8h]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
ldr x5, [x3, #:lo12:m8h+8]
|
||||
cmp x2, x5
|
||||
bne .Lfailure
|
||||
|
||||
movi v1.2s, #1
|
||||
mls v1.2s, v0.2s, v0.2s
|
||||
mov x1, v1.d[0]
|
||||
adrp x3, m2s
|
||||
ldr x4, [x3, #:lo12:m2s]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
|
||||
movi v1.4s, #1
|
||||
mls v1.4s, v0.4s, v0.4s
|
||||
mov x1, v1.d[0]
|
||||
mov x2, v1.d[1]
|
||||
adrp x3, m4s
|
||||
ldr x4, [x3, #:lo12:m4s]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
ldr x5, [x3, #:lo12:m4s+8]
|
||||
cmp x2, x5
|
||||
bne .Lfailure
|
||||
|
||||
pass
|
||||
.Lfailure:
|
||||
fail
|
||||
99
sim/testsuite/sim/aarch64/mul.s
Normal file
99
sim/testsuite/sim/aarch64/mul.s
Normal file
@ -0,0 +1,99 @@
|
||||
# mach: aarch64
|
||||
|
||||
# Check the non-widening multiply vector instruction: mul.
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
.data
|
||||
.align 4
|
||||
input:
|
||||
.word 0x04030201
|
||||
.word 0x08070605
|
||||
.word 0x0c0b0a09
|
||||
.word 0x100f0e0d
|
||||
m8b:
|
||||
.word 0x10090401
|
||||
.word 0x40312419
|
||||
m16b:
|
||||
.word 0x10090401
|
||||
.word 0x40312419
|
||||
.word 0x90796451
|
||||
.word 0x00e1c4a9
|
||||
m4h:
|
||||
.word 0x18090401
|
||||
.word 0x70313c19
|
||||
m8h:
|
||||
.word 0x18090401
|
||||
.word 0x70313c19
|
||||
.word 0x0879b451
|
||||
.word 0xe0e16ca9
|
||||
m2s:
|
||||
.word 0x140a0401
|
||||
.word 0xa46a3c19
|
||||
m4s:
|
||||
.word 0x140a0401
|
||||
.word 0xa46a3c19
|
||||
.word 0xb52ab451
|
||||
.word 0x464b6ca9
|
||||
|
||||
start
|
||||
adrp x0, input
|
||||
ldr q0, [x0, #:lo12:input]
|
||||
|
||||
mul v1.8b, v0.8b, v0.8b
|
||||
mov x1, v1.d[0]
|
||||
adrp x3, m8b
|
||||
ldr x4, [x0, #:lo12:m8b]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
|
||||
mul v1.16b, v0.16b, v0.16b
|
||||
mov x1, v1.d[0]
|
||||
mov x2, v1.d[1]
|
||||
adrp x3, m16b
|
||||
ldr x4, [x0, #:lo12:m16b]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
ldr x5, [x0, #:lo12:m16b+8]
|
||||
cmp x2, x5
|
||||
bne .Lfailure
|
||||
|
||||
mul v1.4h, v0.4h, v0.4h
|
||||
mov x1, v1.d[0]
|
||||
adrp x3, m4h
|
||||
ldr x4, [x0, #:lo12:m4h]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
|
||||
mul v1.8h, v0.8h, v0.8h
|
||||
mov x1, v1.d[0]
|
||||
mov x2, v1.d[1]
|
||||
adrp x3, m8h
|
||||
ldr x4, [x0, #:lo12:m8h]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
ldr x5, [x0, #:lo12:m8h+8]
|
||||
cmp x2, x5
|
||||
bne .Lfailure
|
||||
|
||||
mul v1.2s, v0.2s, v0.2s
|
||||
mov x1, v1.d[0]
|
||||
adrp x3, m2s
|
||||
ldr x4, [x0, #:lo12:m2s]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
|
||||
mul v1.4s, v0.4s, v0.4s
|
||||
mov x1, v1.d[0]
|
||||
mov x2, v1.d[1]
|
||||
adrp x3, m4s
|
||||
ldr x4, [x0, #:lo12:m4s]
|
||||
cmp x1, x4
|
||||
bne .Lfailure
|
||||
ldr x5, [x0, #:lo12:m4s+8]
|
||||
cmp x2, x5
|
||||
bne .Lfailure
|
||||
|
||||
pass
|
||||
.Lfailure:
|
||||
fail
|
||||
Loading…
x
Reference in New Issue
Block a user