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[AArch64][SVE 31/32] Add SVE instructions 

This patch adds the SVE instruction definitions and associated OP_*
enum values.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
	(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
	(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
	(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.

opcodes/
	* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
	(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
	(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
	(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
	(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
	(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
	(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
	(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
	(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
	(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
	(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
	(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
	(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
	(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
	(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
	(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
	(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
	(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
	(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
	(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
	(OP_SVE_XWU, OP_SVE_XXU): New macros.
	(aarch64_feature_sve): New variable.
	(SVE): New macro.
	(_SVE_INSN): Likewise.
	(aarch64_opcode_table): Add SVE instructions.
	* aarch64-opc.h (extract_fields): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.c (extract_fields): Make global.
	(do_misc_decoding): Handle the new SVE aarch64_ops.
	* aarch64-dis-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document the "sve" feature.
	* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
	(get_reg_expected_msg): Handle it.
	(parse_operands): When parsing operands of an SVE instruction,
	disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
	(aarch64_features): Add an entry for SVE.
This commit is contained in:
Richard Sandiford 2016-09-21 16:58:48 +01:00
parent 116b601937
commit c0890d2628
13 changed files with 9530 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* config/tc-aarch64.c (parse_operands): Handle the new SVE core

17
gas/config/tc-aarch64.c
View File

@ -297,6 +297,14 @@ struct reloc_entry
| REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
/* Typecheck: as above, but also Zn and Pn. This should only be \
used for SVE instructions, since Zn and Pn are valid symbols \
in other contexts. */ \
MULTI_REG_TYPE(R_Z_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
| REG_TYPE(ZN) | REG_TYPE(PN)) \
/* Any integer register; used for error messages only. */ \
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
@ -403,6 +411,7 @@ get_reg_expected_msg (aarch64_reg_type reg_type)
msg = N_("C0 - C15 expected");
break;
case REG_TYPE_R_Z_BHSDQ_V:
case REG_TYPE_R_Z_BHSDQ_VZP:
msg = N_("register expected");
break;
case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
@ -5246,7 +5255,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
clear_error ();
skip_whitespace (str);
imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant))
imm_reg_type = REG_TYPE_R_Z_BHSDQ_VZP;
else
imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
{
@ -8385,6 +8397,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
AARCH64_ARCH_NONE},
{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
AARCH64_FEATURE (AARCH64_FEATURE_FP
| AARCH64_FEATURE_SIMD, 0)},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};

2
gas/doc/c-aarch64.texi
View File

@ -154,6 +154,8 @@ automatically cause those extensions to be disabled.
@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
@item @code{sve} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable the Scalable Vector Extensions.
@end multitable
@node AArch64 Syntax

7
include/ChangeLog
View File

@ -1,3 +1,10 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)

13
include/opcode/aarch64.h
View File

@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@ -587,6 +588,18 @@ enum aarch64_op
OP_UXTL,
OP_UXTL2,
OP_MOV_P_P,
OP_MOV_Z_P_Z,
OP_MOV_Z_V,
OP_MOV_Z_Z,
OP_MOV_Z_Zi,
OP_MOVM_P_P_P,
OP_MOVS_P_P,
OP_MOVZS_P_P_P,
OP_MOVZ_P_P_P,
OP_NOTS_P_P_P_Z,
OP_NOT_P_P_P_Z,
OP_TOTAL_NUM, /* Pseudo. */
};

35
opcodes/ChangeLog
View File

@ -1,3 +1,38 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
(OP_SVE_XWU, OP_SVE_XXU): New macros.
(aarch64_feature_sve): New variable.
(SVE): New macro.
(_SVE_INSN): Likewise.
(aarch64_opcode_table): Add SVE instructions.
* aarch64-opc.h (extract_fields): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.c (extract_fields): Make global.
(do_misc_decoding): Handle the new SVE aarch64_ops.
* aarch64-dis-2.c: Regenerate.
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)

119
opcodes/aarch64-asm-2.c
View File

@ -440,6 +440,125 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1131: /* sys */
value = 1131; /* --> sys. */
break;
case 1881: /* bic */
case 1186: /* and */
value = 1186; /* --> and. */
break;
case 1169: /* mov */
case 1188: /* and */
value = 1188; /* --> and. */
break;
case 1173: /* movs */
case 1189: /* ands */
value = 1189; /* --> ands. */
break;
case 1882: /* cmple */
case 1224: /* cmpge */
value = 1224; /* --> cmpge. */
break;
case 1885: /* cmplt */
case 1227: /* cmpgt */
value = 1227; /* --> cmpgt. */
break;
case 1883: /* cmplo */
case 1229: /* cmphi */
value = 1229; /* --> cmphi. */
break;
case 1884: /* cmpls */
case 1232: /* cmphs */
value = 1232; /* --> cmphs. */
break;
case 1166: /* mov */
case 1254: /* cpy */
value = 1254; /* --> cpy. */
break;
case 1168: /* mov */
case 1255: /* cpy */
value = 1255; /* --> cpy. */
break;
case 1892: /* fmov */
case 1171: /* mov */
case 1256: /* cpy */
value = 1256; /* --> cpy. */
break;
case 1161: /* mov */
case 1268: /* dup */
value = 1268; /* --> dup. */
break;
case 1163: /* mov */
case 1160: /* mov */
case 1269: /* dup */
value = 1269; /* --> dup. */
break;
case 1891: /* fmov */
case 1165: /* mov */
case 1270: /* dup */
value = 1270; /* --> dup. */
break;
case 1164: /* mov */
case 1271: /* dupm */
value = 1271; /* --> dupm. */
break;
case 1886: /* eon */
case 1273: /* eor */
value = 1273; /* --> eor. */
break;
case 1174: /* not */
case 1275: /* eor */
value = 1275; /* --> eor. */
break;
case 1175: /* nots */
case 1276: /* eors */
value = 1276; /* --> eors. */
break;
case 1887: /* facle */
case 1281: /* facge */
value = 1281; /* --> facge. */
break;
case 1888: /* faclt */
case 1282: /* facgt */
value = 1282; /* --> facgt. */
break;
case 1889: /* fcmle */
case 1291: /* fcmge */
value = 1291; /* --> fcmge. */
break;
case 1890: /* fcmlt */
case 1293: /* fcmgt */
value = 1293; /* --> fcmgt. */
break;
case 1158: /* fmov */
case 1299: /* fcpy */
value = 1299; /* --> fcpy. */
break;
case 1157: /* fmov */
case 1316: /* fdup */
value = 1316; /* --> fdup. */
break;
case 1159: /* mov */
case 1614: /* orr */
value = 1614; /* --> orr. */
break;
case 1893: /* orn */
case 1615: /* orr */
value = 1615; /* --> orr. */
break;
case 1162: /* mov */
case 1617: /* orr */
value = 1617; /* --> orr. */
break;
case 1172: /* movs */
case 1618: /* orrs */
value = 1618; /* --> orrs. */
break;
case 1167: /* mov */
case 1674: /* sel */
value = 1674; /* --> sel. */
break;
case 1170: /* mov */
case 1675: /* sel */
value = 1675; /* --> sel. */
break;
default: return NULL;
}

43
opcodes/aarch64-asm.c
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@ -1167,6 +1167,8 @@ aarch64_get_variant (struct aarch64_inst *inst)
static void
do_misc_encoding (aarch64_inst *inst)
{
unsigned int value;
switch (inst->opcode->op)
{
case OP_FCVT:
@ -1181,6 +1183,47 @@ do_misc_encoding (aarch64_inst *inst)
case OP_FCVTXN_S:
encode_asisd_fcvtxn (inst);
break;
case OP_MOV_P_P:
case OP_MOVS_P_P:
/* Copy Pn to Pm and Pg. */
value = extract_field (FLD_SVE_Pn, inst->value, 0);
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
insert_field (FLD_SVE_Pg4_10, &inst->value, value, 0);
break;
case OP_MOV_Z_P_Z:
/* Copy Zd to Zm. */
value = extract_field (FLD_SVE_Zd, inst->value, 0);
insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
break;
case OP_MOV_Z_V:
/* Fill in the zero immediate. */
insert_field (FLD_SVE_tsz, &inst->value,
1 << aarch64_get_variant (inst), 0);
break;
case OP_MOV_Z_Z:
/* Copy Zn to Zm. */
value = extract_field (FLD_SVE_Zn, inst->value, 0);
insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
break;
case OP_MOV_Z_Zi:
break;
case OP_MOVM_P_P_P:
/* Copy Pd to Pm. */
value = extract_field (FLD_SVE_Pd, inst->value, 0);
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
break;
case OP_MOVZS_P_P_P:
case OP_MOVZ_P_P_P:
/* Copy Pn to Pm. */
value = extract_field (FLD_SVE_Pn, inst->value, 0);
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
break;
case OP_NOTS_P_P_P_Z:
case OP_NOT_P_P_P_Z:
/* Copy Pg to Pm. */
value = extract_field (FLD_SVE_Pg4_10, inst->value, 0);
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
break;
default: break;
}
}

8104
opcodes/aarch64-dis-2.c
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44
opcodes/aarch64-dis.c
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@ -123,7 +123,7 @@ parse_aarch64_dis_options (const char *options)
is encoded in H:L:M in some cases, the fields H:L:M should be passed in
the order of H, L, M. */
static inline aarch64_insn
aarch64_insn
extract_fields (aarch64_insn code, aarch64_insn mask, ...)
{
uint32_t num;
@ -1811,17 +1811,59 @@ decode_fcvt (aarch64_inst *inst)
static int
do_misc_decoding (aarch64_inst *inst)
{
unsigned int value;
switch (inst->opcode->op)
{
case OP_FCVT:
return decode_fcvt (inst);
case OP_FCVTN:
case OP_FCVTN2:
case OP_FCVTL:
case OP_FCVTL2:
return decode_asimd_fcvt (inst);
case OP_FCVTXN_S:
return decode_asisd_fcvtxn (inst);
case OP_MOV_P_P:
case OP_MOVS_P_P:
value = extract_field (FLD_SVE_Pn, inst->value, 0);
return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
&& value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
case OP_MOV_Z_P_Z:
return (extract_field (FLD_SVE_Zd, inst->value, 0)
== extract_field (FLD_SVE_Zm_16, inst->value, 0));
case OP_MOV_Z_V:
/* Index must be zero. */
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
return value == 1 || value == 2 || value == 4 || value == 8;
case OP_MOV_Z_Z:
return (extract_field (FLD_SVE_Zn, inst->value, 0)
== extract_field (FLD_SVE_Zm_16, inst->value, 0));
case OP_MOV_Z_Zi:
/* Index must be nonzero. */
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
return value != 1 && value != 2 && value != 4 && value != 8;
case OP_MOVM_P_P_P:
return (extract_field (FLD_SVE_Pd, inst->value, 0)
== extract_field (FLD_SVE_Pm, inst->value, 0));
case OP_MOVZS_P_P_P:
case OP_MOVZ_P_P_P:
return (extract_field (FLD_SVE_Pn, inst->value, 0)
== extract_field (FLD_SVE_Pm, inst->value, 0));
case OP_NOTS_P_P_P_Z:
case OP_NOT_P_P_P_Z:
return (extract_field (FLD_SVE_Pm, inst->value, 0)
== extract_field (FLD_SVE_Pg4_10, inst->value, 0));
default:
return 0;
}

11
opcodes/aarch64-opc-2.c
View File

@ -276,6 +276,17 @@ static const unsigned op_enum_table [] =
382,
404,
406,
1162,
1167,
1160,
1159,
1163,
1170,
1172,
1173,
1169,
1175,
1174,
};
/* Given the opcode enumerator OP, return the pointer to the corresponding

3
opcodes/aarch64-opc.h
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@ -333,6 +333,9 @@ extract_field (enum aarch64_field_kind kind, aarch64_insn code,
{
return extract_field_2 (&fields[kind], code, mask);
}
extern aarch64_insn
extract_fields (aarch64_insn code, aarch64_insn mask, ...);
/* Inline functions selecting operand to do the encoding/decoding for a
certain instruction bit-field. */

1269
opcodes/aarch64-tbl.h
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