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* mips.igen (CFC1, CTC1): Pass the correct register numbers to

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PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
This commit is contained in:
Jim Blandy 2001-04-12 14:53:20 +00:00
parent 8cc32590dd
commit c0efbca4a3
3 changed files with 12 additions and 4 deletions
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9
sim/mips/ChangeLog
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@ -1,3 +1,12 @@
2001-04-12 Jim Blandy <jimb@redhat.com>
* mips.igen (CFC1, CTC1): Pass the correct register numbers to
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2001-02-23 Ben Elliston <bje@redhat.com>
* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not

6
sim/mips/mips.igen
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@ -2839,11 +2839,11 @@
if (X)
{
if (FS == 0)
PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
else if (FS == 31)
PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
/* else NOP */
PENDING_FILL(COCIDX,0); /* special case */
PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
}
else
{ /* control from */

1
sim/mips/sim-main.h
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@ -405,7 +405,6 @@ enum float_operation
#define Debug (REGISTERS[86])
#define DEPC (REGISTERS[87])
#define EPC (REGISTERS[88])
#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
/* All internal state modified by signal_exception() that may need to be
rolled back for passing moment-of-exception image back to gdb. */