binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
deae2a14a0
commit
c0f3af977b
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@ -1,6 +1,11 @@
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
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* dwarf.c (dwarf_regnames_i386): Add AVX registers.
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(dwarf_regnames_x86_64): Likewise.
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2008-03-27 Cary Coutant <ccoutant@google.com>
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Add support for thin archives.
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Add support for thin archives.
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* ar.c (make_thin_archive): New global flag.
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(map_over_members): Deal with full pathnames in thin archives.
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(usage, main): Add 'T' option for building thin archives.
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@ -3182,7 +3182,10 @@ static const char *const dwarf_regnames_i386[] =
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"mm4", "mm5", "mm6", "mm7",
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"fcw", "fsw", "mxcsr",
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
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"tr", "ldtr"
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"tr", "ldtr",
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NULL, NULL, NULL,
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"ymm0", "ymm1", "ymm2", "ymm3",
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"ymm4", "ymm5", "ymm6", "ymm7"
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};
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static const char *const dwarf_regnames_x86_64[] =
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@ -3204,7 +3207,12 @@ static const char *const dwarf_regnames_x86_64[] =
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
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"fs.base", "gs.base", NULL, NULL,
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"tr", "ldtr",
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"mxcsr", "fcw", "fsw"
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"mxcsr", "fcw", "fsw",
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NULL, NULL, NULL,
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"ymm0", "ymm1", "ymm2", "ymm3",
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"ymm4", "ymm5", "ymm6", "ymm7",
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"ymm8", "ymm9", "ymm10", "ymm11",
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"ymm12", "ymm13", "ymm14", "ymm15"
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};
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static const char *const *dwarf_regnames;
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@ -1,3 +1,53 @@
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
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* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
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Document -msse2avx, .avx, .aes, .clmul and .fma.
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* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
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(vex_prefix): Likewise.
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(sse2avx): Likewise.
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(CPU_FLAGS_ARCH_MATCH): Likewise.
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(CPU_FLAGS_64BIT_MATCH): Likewise.
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(CPU_FLAGS_32BIT_MATCH): Likewise.
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(CPU_FLAGS_PERFECT_MATCH): Likewise.
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(regymm): Likewise.
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(vex_imm4): Likewise.
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(fits_in_imm4): Likewise.
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(build_vex_prefix): Likewise.
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(VEX_check_operands): Likewise.
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(bad_implicit_operand): Likewise.
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(OPTION_MSSE2AVX): Likewise.
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(T_YMMWORD): Likewise.
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(_i386_insn): Add vex.
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(cpu_arch): Add .avx, .aes, .clmul and .fma.
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(cpu_flags_match): Changed to take a pointer to const template.
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Enable encoding SSE instructions with VEX prefix for -msse2avx.
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(match_mem_size): Also check ymmword.
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(operand_type_match): Clear ymmword.
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(md_begin): Allow '_' in mnemonic.
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(type_names): Add OPERAND_TYPE_VEX_IMM4.
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(process_immext): Update assert.
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(md_assemble): Don't call process_immext if sse2avx and immext
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are true. Call build_vex_prefix if vex is true.
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(parse_insn): Updated for cpu_flags_match.
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(swap_operands): Handle 5 operands.
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(match_template): Handle 5 operands. Updated for cpu_flags_match.
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Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
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(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
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(check_byte_reg): Check regymm.
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(process_operands): Duplicate the destination register for
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-msse2avx if needed.
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(build_modrm_byte): Updated for instructions with VEX encoding.
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(output_insn): Output VEX prefix if needed.
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(md_longopts): Add msse2avx.
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(md_parse_option): Handle OPTION_MSSE2AVX.
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(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
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(intel_e09): Support YMMWORD.
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(intel_e11): Likewise.
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(intel_get_token): Likewise.
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2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
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* config/tc-avr.c (mcu_types): Add attiny167.
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5
gas/NEWS
5
gas/NEWS
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@ -1,4 +1,9 @@
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-*- text -*-
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* New command line option -msse2avx for x86 target to encode SSE
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instructions with VEX prefix.
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* Add Intel AES, CLMUL, AVX/FMA support for x86 target.
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* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
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-mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,
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-mnaked-reg and -mold-gcc, for x86 targets.
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File diff suppressed because it is too large
Load Diff
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@ -120,9 +120,13 @@ accept various extension mnemonics. For example,
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@code{sse4.1},
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@code{sse4.2},
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@code{sse4},
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@code{avx},
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@code{vmx},
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@code{smx},
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@code{xsave},
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@code{aes},
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@code{clmul},
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@code{fma},
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@code{3dnow},
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@code{3dnowa},
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@code{sse4a},
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@ -145,6 +149,12 @@ generated.
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Valid @var{CPU} values are identical to the processor list of
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@option{-march=@var{CPU}}.
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@cindex @samp{-msse2avx} option, i386
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@cindex @samp{-msse2avx} option, x86-64
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@item -msse2avx
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This option specifies that the assembler should encode SSE instructions
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with VEX prefix.
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@cindex @samp{-mmnemonic=} option, i386
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@cindex @samp{-mmnemonic=} option, x86-64
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@item -mmnemonic=@var{att}
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@ -821,7 +831,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{generic32} @tab @samp{generic64}
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@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@item @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
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@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
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@item @samp{.aes} @tab @samp{.clmul} @tab @samp{.fma}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.svme} @tab @samp{.abm}
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@item @samp{.padlock}
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@ -1,3 +1,59 @@
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
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x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
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x86-64-avx-intel and x86-64-inval-avx.
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* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
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* gas/cfi/cfi-x86_64.s: Likewise.
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* gas/i386/aes.d: New.
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* gas/i386/aes.s: Likewise.
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* gas/i386/aes-intel.d: Likewise.
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* gas/i386/avx.d: Likewise.
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* gas/i386/avx.s: Likewise.
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* gas/i386/avx-intel.d: Likewise.
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* gas/i386/clmul.d: Likewise.
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* gas/i386/clmul-intel.d: Likewise.
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* gas/i386/clmul.s: Likewise.
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* gas/i386/i386.exp: Likewise.
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* gas/i386/inval-avx.l: Likewise.
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* gas/i386/inval-avx.s: Likewise.
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* gas/i386/sse2avx.d: Likewise.
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* gas/i386/sse2avx.s: Likewise.
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* gas/i386/x86-64-aes.d: Likewise.
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* gas/i386/x86-64-aes.s: Likewise.
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* gas/i386/x86-64-aes-intel.d: Likewise.
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* gas/i386/x86-64-avx.d: Likewise.
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* gas/i386/x86-64-avx.s: Likewise.
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* gas/i386/x86-64-avx-intel.d: Likewise.
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* gas/i386/x86-64-clmul.d: Likewise.
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* gas/i386/x86-64-clmul-intel.d: Likewise.
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* gas/i386/x86-64-clmul.s: Likewise.
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* gas/i386/x86-64-inval-avx.l: Likewise.
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* gas/i386/x86-64-inval-avx.s: Likewise.
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* gas/i386/x86-64-sse2avx.d: Likewise.
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* gas/i386/x86-64-sse2avx.s: Likewise.
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* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
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* gas/i386/x86-64-arch-2.s: Likewise.
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* gas/i386/rexw.s: Add AVX tests.
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* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
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* gas/cfi/cfi-i386.d: Updated.
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* gas/cfi/cfi-x86_64.d: Likewise.
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* gas/i386/arch-10.d: Likewise.
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* gas/i386/arch-10-1.l: Likewise.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/rexw.d: Likewise.
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* gas/i386/x86-64-arch-2.d: Likewise.
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* gas/i386/x86-64-opcode-inval.d: Likewise.
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* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
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2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
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From Jie Zhang <jie.zhang@analog.com>
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DW_CFA_undefined: r8 \(eip\)
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DW_CFA_nop
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000000a0 00000094 00000018 FDE cie=0000008c pc=00000044..00000071
|
||||
000000a0 000000ac 00000018 FDE cie=0000008c pc=00000044..00000079
|
||||
DW_CFA_advance_loc: 1 to 00000045
|
||||
DW_CFA_undefined: r0 \(eax\)
|
||||
DW_CFA_advance_loc: 1 to 00000046
|
||||
|
|
@ -146,7 +146,24 @@ The section .eh_frame contains:
|
|||
DW_CFA_undefined: r35 \(mm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000070
|
||||
DW_CFA_undefined: r36 \(mm7\)
|
||||
DW_CFA_advance_loc: 1 to 00000071
|
||||
DW_CFA_undefined: r53 \(ymm0\)
|
||||
DW_CFA_advance_loc: 1 to 00000072
|
||||
DW_CFA_undefined: r54 \(ymm1\)
|
||||
DW_CFA_advance_loc: 1 to 00000073
|
||||
DW_CFA_undefined: r55 \(ymm2\)
|
||||
DW_CFA_advance_loc: 1 to 00000074
|
||||
DW_CFA_undefined: r56 \(ymm3\)
|
||||
DW_CFA_advance_loc: 1 to 00000075
|
||||
DW_CFA_undefined: r57 \(ymm4\)
|
||||
DW_CFA_advance_loc: 1 to 00000076
|
||||
DW_CFA_undefined: r58 \(ymm5\)
|
||||
DW_CFA_advance_loc: 1 to 00000077
|
||||
DW_CFA_undefined: r59 \(ymm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000078
|
||||
DW_CFA_undefined: r60 \(ymm7\)
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -162,4 +162,13 @@ func_all_registers:
|
|||
.cfi_undefined mm6 ; nop
|
||||
.cfi_undefined mm7 ; nop
|
||||
|
||||
.cfi_undefined ymm0 ; nop
|
||||
.cfi_undefined ymm1 ; nop
|
||||
.cfi_undefined ymm2 ; nop
|
||||
.cfi_undefined ymm3 ; nop
|
||||
.cfi_undefined ymm4 ; nop
|
||||
.cfi_undefined ymm5 ; nop
|
||||
.cfi_undefined ymm6 ; nop
|
||||
.cfi_undefined ymm7 ; nop
|
||||
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ The section .eh_frame contains:
|
|||
DW_CFA_undefined: r16 \(rip\)
|
||||
DW_CFA_nop
|
||||
|
||||
000000e8 000000cc 00000018 FDE cie=000000d4 pc=00000058..00000097
|
||||
000000e8 000000fc 00000018 FDE cie=000000d4 pc=00000058..000000a7
|
||||
DW_CFA_advance_loc: 1 to 00000059
|
||||
DW_CFA_undefined: r0 \(rax\)
|
||||
DW_CFA_advance_loc: 1 to 0000005a
|
||||
|
|
@ -219,9 +219,42 @@ The section .eh_frame contains:
|
|||
DW_CFA_undefined: r47 \(mm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000096
|
||||
DW_CFA_undefined: r48 \(mm7\)
|
||||
DW_CFA_advance_loc: 1 to 00000097
|
||||
DW_CFA_undefined: r70 \(ymm0\)
|
||||
DW_CFA_advance_loc: 1 to 00000098
|
||||
DW_CFA_undefined: r71 \(ymm1\)
|
||||
DW_CFA_advance_loc: 1 to 00000099
|
||||
DW_CFA_undefined: r72 \(ymm2\)
|
||||
DW_CFA_advance_loc: 1 to 0000009a
|
||||
DW_CFA_undefined: r73 \(ymm3\)
|
||||
DW_CFA_advance_loc: 1 to 0000009b
|
||||
DW_CFA_undefined: r74 \(ymm4\)
|
||||
DW_CFA_advance_loc: 1 to 0000009c
|
||||
DW_CFA_undefined: r75 \(ymm5\)
|
||||
DW_CFA_advance_loc: 1 to 0000009d
|
||||
DW_CFA_undefined: r76 \(ymm6\)
|
||||
DW_CFA_advance_loc: 1 to 0000009e
|
||||
DW_CFA_undefined: r77 \(ymm7\)
|
||||
DW_CFA_advance_loc: 1 to 0000009f
|
||||
DW_CFA_undefined: r78 \(ymm8\)
|
||||
DW_CFA_advance_loc: 1 to 000000a0
|
||||
DW_CFA_undefined: r79 \(ymm9\)
|
||||
DW_CFA_advance_loc: 1 to 000000a1
|
||||
DW_CFA_undefined: r80 \(ymm10\)
|
||||
DW_CFA_advance_loc: 1 to 000000a2
|
||||
DW_CFA_undefined: r81 \(ymm11\)
|
||||
DW_CFA_advance_loc: 1 to 000000a3
|
||||
DW_CFA_undefined: r82 \(ymm12\)
|
||||
DW_CFA_advance_loc: 1 to 000000a4
|
||||
DW_CFA_undefined: r83 \(ymm13\)
|
||||
DW_CFA_advance_loc: 1 to 000000a5
|
||||
DW_CFA_undefined: r84 \(ymm14\)
|
||||
DW_CFA_advance_loc: 1 to 000000a6
|
||||
DW_CFA_undefined: r85 \(ymm15\)
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -211,4 +211,21 @@ func_all_registers:
|
|||
.cfi_undefined mm6 ; nop
|
||||
.cfi_undefined mm7 ; nop
|
||||
|
||||
.cfi_undefined ymm0 ; nop
|
||||
.cfi_undefined ymm1 ; nop
|
||||
.cfi_undefined ymm2 ; nop
|
||||
.cfi_undefined ymm3 ; nop
|
||||
.cfi_undefined ymm4 ; nop
|
||||
.cfi_undefined ymm5 ; nop
|
||||
.cfi_undefined ymm6 ; nop
|
||||
.cfi_undefined ymm7 ; nop
|
||||
.cfi_undefined ymm8 ; nop
|
||||
.cfi_undefined ymm9 ; nop
|
||||
.cfi_undefined ymm10 ; nop
|
||||
.cfi_undefined ymm11 ; nop
|
||||
.cfi_undefined ymm12 ; nop
|
||||
.cfi_undefined ymm13 ; nop
|
||||
.cfi_undefined ymm14 ; nop
|
||||
.cfi_undefined ymm15 ; nop
|
||||
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -0,0 +1,34 @@
|
|||
#source: aes.s
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 AES (Intel mode)
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[ecx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[ecx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8
|
||||
#pass
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#objdump: -dw
|
||||
#name: i386 AES
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Check AES new instructions.
|
||||
|
||||
.text
|
||||
foo:
|
||||
aesenc (%ecx),%xmm0
|
||||
aesenc %xmm1,%xmm0
|
||||
aesenclast (%ecx),%xmm0
|
||||
aesenclast %xmm1,%xmm0
|
||||
aesdec (%ecx),%xmm0
|
||||
aesdec %xmm1,%xmm0
|
||||
aesdeclast (%ecx),%xmm0
|
||||
aesdeclast %xmm1,%xmm0
|
||||
aesimc (%ecx),%xmm0
|
||||
aesimc %xmm1,%xmm0
|
||||
aeskeygenassist $8,(%ecx),%xmm0
|
||||
aeskeygenassist $8,%xmm1,%xmm0
|
||||
|
||||
.intel_syntax noprefix
|
||||
aesenc xmm0,XMMWORD PTR [ecx]
|
||||
aesenc xmm0,xmm1
|
||||
aesenclast xmm0,XMMWORD PTR [ecx]
|
||||
aesenclast xmm0,xmm1
|
||||
aesdec xmm0,XMMWORD PTR [ecx]
|
||||
aesdec xmm0,xmm1
|
||||
aesdeclast xmm0,XMMWORD PTR [ecx]
|
||||
aesdeclast xmm0,xmm1
|
||||
aesimc xmm0,XMMWORD PTR [ecx]
|
||||
aesimc xmm0,xmm1
|
||||
aeskeygenassist xmm0,XMMWORD PTR [ecx],8
|
||||
aeskeygenassist xmm0,xmm1,8
|
||||
|
|
@ -17,6 +17,10 @@
|
|||
.*:34: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:46: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
|
@ -39,23 +43,31 @@ GAS LISTING .*
|
|||
[ ]*16[ ]+phminposuw %xmm1,%xmm3
|
||||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+crc32 %ecx,%ebx
|
||||
[ ]*19[ ]+\# VMX
|
||||
[ ]*20[ ]+vmxoff
|
||||
[ ]*21[ ]+\# SMX
|
||||
[ ]*22[ ]+getsec
|
||||
[ ]*23[ ]+\# Xsave
|
||||
[ ]*24[ ]+xgetbv
|
||||
[ ]*25[ ]+\# 3DNow
|
||||
[ ]*26[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*27[ ]+\# 3DNow Extensions
|
||||
[ ]*28[ ]+pswapd %mm4,%mm3
|
||||
[ ]*29[ ]+\# SSE4a
|
||||
[ ]*30[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*31[ ]+\# SVME
|
||||
[ ]*32[ ]+vmload
|
||||
[ ]*33[ ]+\# ABM
|
||||
[ ]*34[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*35[ ]+\# SSE5
|
||||
[ ]*36[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*37[ ]+\# PadLock
|
||||
[ ]*38[ ]+xstorerng
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# CLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# FMA
|
||||
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*33[ ]+\# 3DNow
|
||||
[ ]*34[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*35[ ]+\# 3DNow Extensions
|
||||
[ ]*36[ ]+pswapd %mm4,%mm3
|
||||
[ ]*37[ ]+\# SSE4a
|
||||
[ ]*38[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*39[ ]+\# SVME
|
||||
[ ]*40[ ]+vmload
|
||||
[ ]*41[ ]+\# ABM
|
||||
[ ]*42[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*43[ ]+\# SSE5
|
||||
[ ]*44[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*45[ ]+\# PadLock
|
||||
[ ]*46[ ]+xstorerng
|
||||
|
|
|
|||
|
|
@ -16,6 +16,10 @@
|
|||
.*:34: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:46: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
|
@ -38,23 +42,31 @@ GAS LISTING .*
|
|||
[ ]*16[ ]+phminposuw %xmm1,%xmm3
|
||||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+crc32 %ecx,%ebx
|
||||
[ ]*19[ ]+\# VMX
|
||||
[ ]*20[ ]+vmxoff
|
||||
[ ]*21[ ]+\# SMX
|
||||
[ ]*22[ ]+getsec
|
||||
[ ]*23[ ]+\# Xsave
|
||||
[ ]*24[ ]+xgetbv
|
||||
[ ]*25[ ]+\# 3DNow
|
||||
[ ]*26[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*27[ ]+\# 3DNow Extensions
|
||||
[ ]*28[ ]+pswapd %mm4,%mm3
|
||||
[ ]*29[ ]+\# SSE4a
|
||||
[ ]*30[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*31[ ]+\# SVME
|
||||
[ ]*32[ ]+vmload
|
||||
[ ]*33[ ]+\# ABM
|
||||
[ ]*34[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*35[ ]+\# SSE5
|
||||
[ ]*36[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*37[ ]+\# PadLock
|
||||
[ ]*38[ ]+xstorerng
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# CLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# FMA
|
||||
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*33[ ]+\# 3DNow
|
||||
[ ]*34[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*35[ ]+\# 3DNow Extensions
|
||||
[ ]*36[ ]+pswapd %mm4,%mm3
|
||||
[ ]*37[ ]+\# SSE4a
|
||||
[ ]*38[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*39[ ]+\# SVME
|
||||
[ ]*40[ ]+vmload
|
||||
[ ]*41[ ]+\# ABM
|
||||
[ ]*42[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*43[ ]+\# SSE5
|
||||
[ ]*44[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*45[ ]+\# PadLock
|
||||
[ ]*46[ ]+xstorerng
|
||||
|
|
|
|||
|
|
@ -9,6 +9,10 @@
|
|||
.*:34: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:46: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
|
@ -34,23 +38,31 @@ GAS LISTING .*
|
|||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx
|
||||
[ ]*18[ ]+D9
|
||||
[ ]*19[ ]+\# VMX
|
||||
[ ]*20[ ]+vmxoff
|
||||
[ ]*21[ ]+\# SMX
|
||||
[ ]*22[ ]+getsec
|
||||
[ ]*23[ ]+\# Xsave
|
||||
[ ]*24[ ]+xgetbv
|
||||
[ ]*25[ ]+\# 3DNow
|
||||
[ ]*26[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*27[ ]+\# 3DNow Extensions
|
||||
[ ]*28[ ]+pswapd %mm4,%mm3
|
||||
[ ]*29[ ]+\# SSE4a
|
||||
[ ]*30[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*31[ ]+\# SVME
|
||||
[ ]*32[ ]+vmload
|
||||
[ ]*33[ ]+\# ABM
|
||||
[ ]*34[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*35[ ]+\# SSE5
|
||||
[ ]*36[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*37[ ]+\# PadLock
|
||||
[ ]*38[ ]+xstorerng
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# CLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# FMA
|
||||
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*33[ ]+\# 3DNow
|
||||
[ ]*34[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*35[ ]+\# 3DNow Extensions
|
||||
[ ]*36[ ]+pswapd %mm4,%mm3
|
||||
[ ]*37[ ]+\# SSE4a
|
||||
[ ]*38[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*39[ ]+\# SVME
|
||||
[ ]*40[ ]+vmload
|
||||
[ ]*41[ ]+\# ABM
|
||||
[ ]*42[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*43[ ]+\# SSE5
|
||||
[ ]*44[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*45[ ]+\# PadLock
|
||||
[ ]*46[ ]+xstorerng
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
.*: Assembler messages:
|
||||
.*:24: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:30: Error: .*
|
||||
|
|
@ -7,6 +7,10 @@
|
|||
.*:34: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:46: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
|
|
@ -32,23 +36,31 @@ GAS LISTING .*
|
|||
[ ]*17[ ]+\# SSE4\.2
|
||||
[ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx
|
||||
[ ]*18[ ]+D9
|
||||
[ ]*19[ ]+\# VMX
|
||||
[ ]*20[ ]+\?\?\?\? 0F01C4 vmxoff
|
||||
[ ]*21[ ]+\# SMX
|
||||
[ ]*22[ ]+\?\?\?\? 0F37 getsec
|
||||
[ ]*23[ ]+\# Xsave
|
||||
[ ]*24[ ]+xgetbv
|
||||
[ ]*25[ ]+\# 3DNow
|
||||
[ ]*26[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*27[ ]+\# 3DNow Extensions
|
||||
[ ]*28[ ]+pswapd %mm4,%mm3
|
||||
[ ]*29[ ]+\# SSE4a
|
||||
[ ]*30[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*31[ ]+\# SVME
|
||||
[ ]*32[ ]+vmload
|
||||
[ ]*33[ ]+\# ABM
|
||||
[ ]*34[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*35[ ]+\# SSE5
|
||||
[ ]*36[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*37[ ]+\# PadLock
|
||||
[ ]*38[ ]+xstorerng
|
||||
[ ]*19[ ]+\# AVX
|
||||
[ ]*20[ ]+vzeroall
|
||||
[ ]*21[ ]+\# VMX
|
||||
[ ]*22[ ]+\?\?\?\? 0F01C4 vmxoff
|
||||
[ ]*23[ ]+\# SMX
|
||||
[ ]*24[ ]+\?\?\?\? 0F37 getsec
|
||||
[ ]*25[ ]+\# Xsave
|
||||
[ ]*26[ ]+xgetbv
|
||||
[ ]*27[ ]+\# AES
|
||||
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
|
||||
[ ]*29[ ]+\# CLMUL
|
||||
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
|
||||
[ ]*31[ ]+\# FMA
|
||||
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*33[ ]+\# 3DNow
|
||||
[ ]*34[ ]+pmulhrw %mm4,%mm3
|
||||
[ ]*35[ ]+\# 3DNow Extensions
|
||||
[ ]*36[ ]+pswapd %mm4,%mm3
|
||||
[ ]*37[ ]+\# SSE4a
|
||||
[ ]*38[ ]+insertq %xmm2,%xmm1
|
||||
[ ]*39[ ]+\# SVME
|
||||
[ ]*40[ ]+vmload
|
||||
[ ]*41[ ]+\# ABM
|
||||
[ ]*42[ ]+lzcnt %ecx,%ebx
|
||||
[ ]*43[ ]+\# SSE5
|
||||
[ ]*44[ ]+frczss %xmm2, %xmm1
|
||||
[ ]*45[ ]+\# PadLock
|
||||
[ ]*46[ ]+xstorerng
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
#as: -march=i686+sse4+vmx+smx+xsave+sse5+3dnowa+svme+padlock
|
||||
#as: -march=i686+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
|
||||
#objdump: -dw
|
||||
#name: i386 arch 10
|
||||
|
||||
|
|
@ -15,9 +15,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: c5 fc 77 vzeroall
|
||||
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
|
||||
[ ]*[a-f0-9]+: 0f 37 getsec
|
||||
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
|
|
|
|||
|
|
@ -16,12 +16,20 @@ phaddw %xmm4,%xmm3
|
|||
phminposuw %xmm1,%xmm3
|
||||
# SSE4.2
|
||||
crc32 %ecx,%ebx
|
||||
# AVX
|
||||
vzeroall
|
||||
# VMX
|
||||
vmxoff
|
||||
# SMX
|
||||
getsec
|
||||
# Xsave
|
||||
xgetbv
|
||||
# AES
|
||||
aesenc (%ecx),%xmm0
|
||||
# CLMUL
|
||||
pclmulqdq $8,%xmm1,%xmm0
|
||||
# FMA
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
# 3DNow
|
||||
pmulhrw %mm4,%mm3
|
||||
# 3DNow Extensions
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,30 @@
|
|||
#source: clmul.s
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 CLMUL (Intel mode)
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[ecx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[ecx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1
|
||||
#pass
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#objdump: -dw
|
||||
#name: i386 CLMUL
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%ecx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0
|
||||
#pass
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# Check CLMUL new instructions.
|
||||
|
||||
.text
|
||||
foo:
|
||||
pclmulqdq $8,(%ecx),%xmm0
|
||||
pclmulqdq $8,%xmm1,%xmm0
|
||||
pclmullqlqdq (%ecx),%xmm0
|
||||
pclmullqlqdq %xmm1,%xmm0
|
||||
pclmulhqlqdq (%ecx),%xmm0
|
||||
pclmulhqlqdq %xmm1,%xmm0
|
||||
pclmullqhqdq (%ecx),%xmm0
|
||||
pclmullqhqdq %xmm1,%xmm0
|
||||
pclmulhqhqdq (%ecx),%xmm0
|
||||
pclmulhqhqdq %xmm1,%xmm0
|
||||
|
||||
.intel_syntax noprefix
|
||||
pclmulqdq xmm0,XMMWORD PTR [ecx],8
|
||||
pclmulqdq xmm0,xmm1,8
|
||||
pclmullqlqdq xmm0,XMMWORD PTR [ecx]
|
||||
pclmullqlqdq xmm0,xmm1
|
||||
pclmulhqlqdq xmm0,XMMWORD PTR [ecx]
|
||||
pclmulhqlqdq xmm0,xmm1
|
||||
pclmullqhqdq xmm0,XMMWORD PTR [ecx]
|
||||
pclmullqhqdq xmm0,xmm1
|
||||
pclmulhqhqdq xmm0,XMMWORD PTR [ecx]
|
||||
pclmulhqhqdq xmm0,xmm1
|
||||
|
|
@ -116,6 +116,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "arch-12"
|
||||
run_dump_test "xsave"
|
||||
run_dump_test "xsave-intel"
|
||||
run_dump_test "aes"
|
||||
run_dump_test "aes-intel"
|
||||
run_dump_test "clmul"
|
||||
run_dump_test "clmul-intel"
|
||||
run_dump_test "avx"
|
||||
run_dump_test "avx-intel"
|
||||
run_dump_test "sse2avx"
|
||||
run_list_test "inval-avx" "-al"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
|
|
@ -234,6 +242,14 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-arch-2"
|
||||
run_dump_test "x86-64-xsave"
|
||||
run_dump_test "x86-64-xsave-intel"
|
||||
run_dump_test "x86-64-aes"
|
||||
run_dump_test "x86-64-aes-intel"
|
||||
run_dump_test "x86-64-clmul"
|
||||
run_dump_test "x86-64-clmul-intel"
|
||||
run_dump_test "x86-64-avx"
|
||||
run_dump_test "x86-64-avx-intel"
|
||||
run_dump_test "x86-64-sse2avx"
|
||||
run_list_test "x86-64-inval-avx" "-al"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,109 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:25: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:27: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:35: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:39: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:41: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:43: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:45: Error: .*
|
||||
.*:46: Error: .*
|
||||
.*:47: Error: .*
|
||||
.*:48: Error: .*
|
||||
.*:49: Error: .*
|
||||
.*:50: Error: .*
|
||||
.*:51: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:53: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:55: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check illegal AVX instructions
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+_start:
|
||||
[ ]*4[ ]+vcvtpd2dq \(%ecx\),%xmm2
|
||||
[ ]*5[ ]+vcvtpd2ps \(%ecx\),%xmm2
|
||||
[ ]*6[ ]+vcvttpd2dq \(%ecx\),%xmm2
|
||||
[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*29[ ]+
|
||||
[ ]*30[ ]+\.intel_syntax noprefix
|
||||
[ ]*31[ ]+vcvtpd2dq xmm2,\[ecx\]
|
||||
[ ]*32[ ]+vcvtpd2ps xmm2,\[ecx\]
|
||||
[ ]*33[ ]+vcvttpd2dq xmm2,\[ecx\]
|
||||
[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
# Check illegal AVX instructions
|
||||
.text
|
||||
_start:
|
||||
vcvtpd2dq (%ecx),%xmm2
|
||||
vcvtpd2ps (%ecx),%xmm2
|
||||
vcvttpd2dq (%ecx),%xmm2
|
||||
vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
|
||||
.intel_syntax noprefix
|
||||
vcvtpd2dq xmm2,[ecx]
|
||||
vcvtpd2ps xmm2,[ecx]
|
||||
vcvttpd2dq xmm2,[ecx]
|
||||
vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
|
|
@ -17,6 +17,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 0f c4 c1 00 pinsrw \$0x0,%ecx,%mm0
|
||||
[ ]*[a-f0-9]+: 0f d7 c5 pmovmskb %mm5,%eax
|
||||
[ ]*[a-f0-9]+: 66 0f d7 c5 pmovmskb %xmm5,%eax
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 c1 00 vextractps \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 50 ca vmovmskpd %xmm2,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 c1 00 vpextrb \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 c8 00 vpextrw \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 20 c1 00 vpinsrb \$0x0,%ecx,%xmm0,%xmm0
|
||||
[ ]*[a-f0-9]+: c5 f9 c4 c1 00 vpinsrw \$0x0,%ecx,%xmm0,%xmm0
|
||||
[ ]*[a-f0-9]+: c5 f9 d7 c5 vpmovmskb %xmm5,%eax
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 17 c1 00 extractps \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: 66 0f 50 ca movmskpd %xmm2,%ecx
|
||||
[ ]*[a-f0-9]+: 0f 50 ca movmskps %xmm2,%ecx
|
||||
|
|
@ -28,4 +36,12 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f c4 c1 00 pinsrw \$0x0,%ecx,%xmm0
|
||||
[ ]*[a-f0-9]+: 0f d7 cd pmovmskb %mm5,%ecx
|
||||
[ ]*[a-f0-9]+: 66 0f d7 cd pmovmskb %xmm5,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 c1 00 vextractps \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 50 ca vmovmskpd %xmm2,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f8 50 ca vmovmskps %xmm2,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 c1 00 vpextrb \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 c8 00 vpextrw \$0x0,%xmm0,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 20 c1 00 vpinsrb \$0x0,%ecx,%xmm0,%xmm0
|
||||
[ ]*[a-f0-9]+: c5 f9 c4 c1 00 vpinsrw \$0x0,%ecx,%xmm0,%xmm0
|
||||
[ ]*[a-f0-9]+: c5 f9 d7 cd vpmovmskb %xmm5,%ecx
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -14,6 +14,16 @@ foo:
|
|||
pmovmskb %mm5,%rax
|
||||
pmovmskb %xmm5,%rax
|
||||
|
||||
# AVX instructions
|
||||
vextractps $0x0,%xmm0,%rcx
|
||||
vmovmskpd %xmm2,%rcx
|
||||
vmovmskps %xmm2,%rcx
|
||||
vpextrb $0x0,%xmm0,%rcx
|
||||
vpextrw $0x0,%xmm0,%rcx
|
||||
vpinsrb $0x0,%rcx,%xmm0,%xmm0
|
||||
vpinsrw $0x0,%rcx,%xmm0,%xmm0
|
||||
vpmovmskb %xmm5,%rax
|
||||
|
||||
.intel_syntax noprefix
|
||||
extractps rcx,xmm0,0x0
|
||||
movmskpd rcx,xmm2
|
||||
|
|
@ -26,3 +36,13 @@ foo:
|
|||
pinsrw xmm0,rcx,0x0
|
||||
pmovmskb rcx,mm5
|
||||
pmovmskb rcx,xmm5
|
||||
|
||||
# AVX instructions
|
||||
vextractps rcx,xmm0,0x0
|
||||
vmovmskpd rcx,xmm2
|
||||
vmovmskps rcx,xmm2
|
||||
vpextrb rcx,xmm0,0x0
|
||||
vpextrw rcx,xmm0,0x0
|
||||
vpinsrb xmm0,xmm0,rcx,0x0
|
||||
vpinsrw xmm0,xmm0,rcx,0x0
|
||||
vpmovmskb rcx,xmm5
|
||||
|
|
|
|||
|
|
@ -0,0 +1,566 @@
|
|||
#as: -msse2avx
|
||||
#objdump: -dw
|
||||
#name: i386 SSE with AVX encoding
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 c9 58 f4 vaddpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 58 31 vaddpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 58 f4 vaddps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 58 31 vaddps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d0 f4 vaddsubpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d0 31 vaddsubpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb d0 f4 vaddsubps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb d0 31 vaddsubps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 55 f4 vandnpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 55 31 vandnpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 55 f4 vandnps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 55 31 vandnps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 54 f4 vandpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 54 31 vandpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 54 f4 vandps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 54 31 vandps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5e f4 vdivpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5e 31 vdivpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5e f4 vdivps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5e 31 vdivps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7c f4 vhaddpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7c 31 vhaddpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7c f4 vhaddps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7c 31 vhaddps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7d f4 vhsubpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7d 31 vhsubpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7d f4 vhsubps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7d 31 vhsubps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5f f4 vmaxpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5f 31 vmaxpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5f f4 vmaxps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5f 31 vmaxps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5d f4 vminpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5d 31 vminpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5d f4 vminps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5d 31 vminps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 59 f4 vmulpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 59 31 vmulpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 59 f4 vmulps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 59 31 vmulps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 56 f4 vorpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 56 31 vorpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 56 f4 vorps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 56 31 vorps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 63 f4 vpacksswb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 63 31 vpacksswb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6b f4 vpackssdw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6b 31 vpackssdw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 67 f4 vpackuswb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 67 31 vpackuswb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 2b f4 vpackusdw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 2b 31 vpackusdw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fc f4 vpaddb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fc 31 vpaddb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fd f4 vpaddw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fd 31 vpaddw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fe f4 vpaddd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fe 31 vpaddd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d4 f4 vpaddq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d4 31 vpaddq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ec f4 vpaddsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ec 31 vpaddsb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ed f4 vpaddsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ed 31 vpaddsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dc f4 vpaddusb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dc 31 vpaddusb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dd f4 vpaddusw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dd 31 vpaddusw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 db f4 vpand %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 db 31 vpand \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 df f4 vpandn %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 df 31 vpandn \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e0 f4 vpavgb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e0 31 vpavgb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e3 f4 vpavgw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e3 31 vpavgw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 74 f4 vpcmpeqb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 74 31 vpcmpeqb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 75 f4 vpcmpeqw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 75 31 vpcmpeqw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 76 f4 vpcmpeqd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 76 31 vpcmpeqd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 29 f4 vpcmpeqq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 29 31 vpcmpeqq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 64 f4 vpcmpgtb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 64 31 vpcmpgtb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 65 f4 vpcmpgtw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 65 31 vpcmpgtw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 66 f4 vpcmpgtd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 66 31 vpcmpgtd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 37 f4 vpcmpgtq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 37 31 vpcmpgtq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 01 f4 vphaddw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 01 31 vphaddw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 02 f4 vphaddd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 02 31 vphaddd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 03 f4 vphaddsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 03 31 vphaddsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 05 f4 vphsubw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 05 31 vphsubw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 06 f4 vphsubd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 06 31 vphsubd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 07 f4 vphsubsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 07 31 vphsubsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f5 f4 vpmaddwd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f5 31 vpmaddwd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 04 f4 vpmaddubsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 04 31 vpmaddubsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3c f4 vpmaxsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3c 31 vpmaxsb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ee f4 vpmaxsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ee 31 vpmaxsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3d f4 vpmaxsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3d 31 vpmaxsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 de f4 vpmaxub %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 de 31 vpmaxub \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3e f4 vpmaxuw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3e 31 vpmaxuw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3f f4 vpmaxud %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3f 31 vpmaxud \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 38 f4 vpminsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 38 31 vpminsb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ea f4 vpminsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ea 31 vpminsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 39 f4 vpminsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 39 31 vpminsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 da f4 vpminub %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 da 31 vpminub \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3a f4 vpminuw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3a 31 vpminuw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3b f4 vpminud %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3b 31 vpminud \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e4 f4 vpmulhuw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e4 31 vpmulhuw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0b f4 vpmulhrsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0b 31 vpmulhrsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e5 f4 vpmulhw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e5 31 vpmulhw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d5 f4 vpmullw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d5 31 vpmullw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 40 f4 vpmulld %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 40 31 vpmulld \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f4 f4 vpmuludq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f4 31 vpmuludq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 28 f4 vpmuldq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 28 31 vpmuldq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 eb f4 vpor %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 eb 31 vpor \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f6 f4 vpsadbw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f6 31 vpsadbw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 00 f4 vpshufb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 00 31 vpshufb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 08 f4 vpsignb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 08 31 vpsignb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 09 f4 vpsignw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 09 31 vpsignw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0a f4 vpsignd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0a 31 vpsignd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f1 f4 vpsllw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f1 31 vpsllw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f2 f4 vpslld %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f2 31 vpslld \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f3 f4 vpsllq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f3 31 vpsllq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e1 f4 vpsraw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e1 31 vpsraw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e2 f4 vpsrad %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e2 31 vpsrad \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d1 f4 vpsrlw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d1 31 vpsrlw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d2 f4 vpsrld %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d2 31 vpsrld \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d3 f4 vpsrlq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d3 31 vpsrlq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f8 f4 vpsubb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f8 31 vpsubb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f9 f4 vpsubw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f9 31 vpsubw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fa f4 vpsubd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fa 31 vpsubd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fb f4 vpsubq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fb 31 vpsubq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e8 f4 vpsubsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e8 31 vpsubsb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e9 f4 vpsubsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e9 31 vpsubsw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d8 f4 vpsubusb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d8 31 vpsubusb \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d9 f4 vpsubusw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d9 31 vpsubusw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 68 f4 vpunpckhbw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 68 31 vpunpckhbw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 69 f4 vpunpckhwd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 69 31 vpunpckhwd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6a f4 vpunpckhdq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6a 31 vpunpckhdq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6d f4 vpunpckhqdq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6d 31 vpunpckhqdq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 60 f4 vpunpcklbw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 60 31 vpunpcklbw \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 61 f4 vpunpcklwd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 61 31 vpunpcklwd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 62 f4 vpunpckldq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 62 31 vpunpckldq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6c f4 vpunpcklqdq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6c 31 vpunpcklqdq \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ef f4 vpxor %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ef 31 vpxor \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5c f4 vsubpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5c 31 vsubpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5c f4 vsubps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5c 31 vsubps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 15 f4 vunpckhpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 15 31 vunpckhpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 15 f4 vunpckhps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 15 31 vunpckhps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 14 f4 vunpcklpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 14 31 vunpcklpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 14 f4 vunpcklps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 14 31 vunpcklps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 57 f4 vxorpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 57 31 vxorpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 57 f4 vxorps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 57 31 vxorps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 00 vcmpeqpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 00 vcmpeqpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 00 vcmpeqps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 00 vcmpeqps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 01 vcmpltpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 01 vcmpltpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 01 vcmpltps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 01 vcmpltps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 02 vcmplepd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 02 vcmplepd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 02 vcmpleps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 02 vcmpleps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 03 vcmpunordpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 03 vcmpunordpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 03 vcmpunordps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 03 vcmpunordps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 04 vcmpneqpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 04 vcmpneqpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 04 vcmpneqps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 04 vcmpneqps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 05 vcmpnltpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 05 vcmpnltpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 05 vcmpnltps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 05 vcmpnltps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 06 vcmpnlepd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 06 vcmpnlepd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 06 vcmpnleps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 06 vcmpnleps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 07 vcmpordpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 07 vcmpordpd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 07 vcmpordps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 07 vcmpordps \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%ecx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0d f4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0d 31 64 vblendpd \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0c f4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0c 31 64 vblendps \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 64 vcmppd \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 64 vcmpps \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 41 f4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 41 31 64 vdppd \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 40 f4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 40 31 64 vdpps \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 42 f4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 42 31 64 vmpsadbw \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0f f4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0f 31 64 vpalignr \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0e f4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0e 31 64 vpblendw \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c6 f4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c6 31 64 vshufpd \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 f4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 31 64 vshufps \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%ecx\),%ecx
|
||||
[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%ecx\),%ecx
|
||||
[ ]*[a-f0-9]+: c5 d9 12 21 vmovlpd \(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d8 12 21 vmovlps \(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 16 21 vmovhpd \(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d8 16 21 vmovhps \(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 64 vcmpsd \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0b f4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0b 31 64 vroundsd \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 58 f4 vaddsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 58 31 vaddsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5a f4 vcvtsd2ss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5a 31 vcvtsd2ss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5e f4 vdivsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5e 31 vdivsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5f f4 vmaxsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5f 31 vmaxsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5d f4 vminsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5d 31 vminsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 59 f4 vmulsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 59 31 vmulsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 51 f4 vsqrtsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 51 31 vsqrtsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5c f4 vsubsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5c 31 vsubsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 00 vcmpeqsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 00 vcmpeqsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 01 vcmpltsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 01 vcmpltsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 02 vcmplesd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 02 vcmplesd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 03 vcmpunordsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 03 vcmpunordsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 04 vcmpneqsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 04 vcmpneqsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 05 vcmpnltsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 05 vcmpnltsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 06 vcmpnlesd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 06 vcmpnlesd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 07 vcmpordsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 07 vcmpordsd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 58 f4 vaddss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 58 31 vaddss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5a f4 vcvtss2sd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5a 31 vcvtss2sd \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5e f4 vdivss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5e 31 vdivss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5f f4 vmaxss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5f 31 vmaxss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5d f4 vminss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5d 31 vminss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 59 f4 vmulss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 59 31 vmulss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 53 f4 vrcpss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 53 31 vrcpss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 52 f4 vrsqrtss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 52 31 vrsqrtss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 51 f4 vsqrtss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 51 31 vsqrtss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5c f4 vsubss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5c 31 vsubss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 00 vcmpeqss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 00 vcmpeqss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 01 vcmpltss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 01 vcmpltss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 02 vcmpless %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 02 vcmpless \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 03 vcmpunordss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 03 vcmpunordss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 04 vcmpneqss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 04 vcmpneqss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 05 vcmpnltss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 05 vcmpnltss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 06 vcmpnless %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 06 vcmpnless \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 07 vcmpordss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 07 vcmpordss \(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%ecx\),%ecx
|
||||
[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%ecx\),%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 db 2a e1 vcvtsi2sd %ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 db 2a 21 vcvtsi2sdl \(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 da 2a e1 vcvtsi2ss %ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 da 2a 21 vcvtsi2ssl \(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 64 vcmpss \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 21 f4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 21 31 64 vinsertps \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0a f4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0a 31 64 vroundss \$0x64,\(%ecx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c5 d9 c4 e1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 c4 21 64 vpinsrw \$0x64,\(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%ecx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%ecx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 c8 12 f4 vmovhlps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 16 f4 vmovlhps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 d9 72 f4 64 vpslld \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
|
||||
#pass
|
||||
|
|
@ -0,0 +1,642 @@
|
|||
# Check SSE to AVX instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
# Tests for op mem64
|
||||
ldmxcsr (%ecx)
|
||||
stmxcsr (%ecx)
|
||||
|
||||
# Tests for op xmm/mem128, xmm
|
||||
cvtdq2ps %xmm4,%xmm6
|
||||
cvtdq2ps (%ecx),%xmm4
|
||||
cvtpd2dq %xmm4,%xmm6
|
||||
cvtpd2dq (%ecx),%xmm4
|
||||
cvtpd2ps %xmm4,%xmm6
|
||||
cvtpd2ps (%ecx),%xmm4
|
||||
cvtps2dq %xmm4,%xmm6
|
||||
cvtps2dq (%ecx),%xmm4
|
||||
cvttpd2dq %xmm4,%xmm6
|
||||
cvttpd2dq (%ecx),%xmm4
|
||||
cvttps2dq %xmm4,%xmm6
|
||||
cvttps2dq (%ecx),%xmm4
|
||||
movapd %xmm4,%xmm6
|
||||
movapd (%ecx),%xmm4
|
||||
movaps %xmm4,%xmm6
|
||||
movaps (%ecx),%xmm4
|
||||
movdqa %xmm4,%xmm6
|
||||
movdqa (%ecx),%xmm4
|
||||
movdqu %xmm4,%xmm6
|
||||
movdqu (%ecx),%xmm4
|
||||
movshdup %xmm4,%xmm6
|
||||
movshdup (%ecx),%xmm4
|
||||
movsldup %xmm4,%xmm6
|
||||
movsldup (%ecx),%xmm4
|
||||
movupd %xmm4,%xmm6
|
||||
movupd (%ecx),%xmm4
|
||||
movups %xmm4,%xmm6
|
||||
movups (%ecx),%xmm4
|
||||
pabsb %xmm4,%xmm6
|
||||
pabsb (%ecx),%xmm4
|
||||
pabsw %xmm4,%xmm6
|
||||
pabsw (%ecx),%xmm4
|
||||
pabsd %xmm4,%xmm6
|
||||
pabsd (%ecx),%xmm4
|
||||
phminposuw %xmm4,%xmm6
|
||||
phminposuw (%ecx),%xmm4
|
||||
ptest %xmm4,%xmm6
|
||||
ptest (%ecx),%xmm4
|
||||
rcpps %xmm4,%xmm6
|
||||
rcpps (%ecx),%xmm4
|
||||
rsqrtps %xmm4,%xmm6
|
||||
rsqrtps (%ecx),%xmm4
|
||||
sqrtpd %xmm4,%xmm6
|
||||
sqrtpd (%ecx),%xmm4
|
||||
sqrtps %xmm4,%xmm6
|
||||
sqrtps (%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm, xmm/mem128
|
||||
movapd %xmm4,%xmm6
|
||||
movapd %xmm4,(%ecx)
|
||||
movaps %xmm4,%xmm6
|
||||
movaps %xmm4,(%ecx)
|
||||
movdqa %xmm4,%xmm6
|
||||
movdqa %xmm4,(%ecx)
|
||||
movdqu %xmm4,%xmm6
|
||||
movdqu %xmm4,(%ecx)
|
||||
movupd %xmm4,%xmm6
|
||||
movupd %xmm4,(%ecx)
|
||||
movups %xmm4,%xmm6
|
||||
movups %xmm4,(%ecx)
|
||||
|
||||
# Tests for op mem128, xmm
|
||||
lddqu (%ecx),%xmm4
|
||||
movntdqa (%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm, mem128
|
||||
movntdq %xmm4,(%ecx)
|
||||
movntpd %xmm4,(%ecx)
|
||||
movntps %xmm4,(%ecx)
|
||||
|
||||
# Tests for op xmm/mem128, xmm[, xmm]
|
||||
addpd %xmm4,%xmm6
|
||||
addpd (%ecx),%xmm6
|
||||
addps %xmm4,%xmm6
|
||||
addps (%ecx),%xmm6
|
||||
addsubpd %xmm4,%xmm6
|
||||
addsubpd (%ecx),%xmm6
|
||||
addsubps %xmm4,%xmm6
|
||||
addsubps (%ecx),%xmm6
|
||||
andnpd %xmm4,%xmm6
|
||||
andnpd (%ecx),%xmm6
|
||||
andnps %xmm4,%xmm6
|
||||
andnps (%ecx),%xmm6
|
||||
andpd %xmm4,%xmm6
|
||||
andpd (%ecx),%xmm6
|
||||
andps %xmm4,%xmm6
|
||||
andps (%ecx),%xmm6
|
||||
divpd %xmm4,%xmm6
|
||||
divpd (%ecx),%xmm6
|
||||
divps %xmm4,%xmm6
|
||||
divps (%ecx),%xmm6
|
||||
haddpd %xmm4,%xmm6
|
||||
haddpd (%ecx),%xmm6
|
||||
haddps %xmm4,%xmm6
|
||||
haddps (%ecx),%xmm6
|
||||
hsubpd %xmm4,%xmm6
|
||||
hsubpd (%ecx),%xmm6
|
||||
hsubps %xmm4,%xmm6
|
||||
hsubps (%ecx),%xmm6
|
||||
maxpd %xmm4,%xmm6
|
||||
maxpd (%ecx),%xmm6
|
||||
maxps %xmm4,%xmm6
|
||||
maxps (%ecx),%xmm6
|
||||
minpd %xmm4,%xmm6
|
||||
minpd (%ecx),%xmm6
|
||||
minps %xmm4,%xmm6
|
||||
minps (%ecx),%xmm6
|
||||
mulpd %xmm4,%xmm6
|
||||
mulpd (%ecx),%xmm6
|
||||
mulps %xmm4,%xmm6
|
||||
mulps (%ecx),%xmm6
|
||||
orpd %xmm4,%xmm6
|
||||
orpd (%ecx),%xmm6
|
||||
orps %xmm4,%xmm6
|
||||
orps (%ecx),%xmm6
|
||||
packsswb %xmm4,%xmm6
|
||||
packsswb (%ecx),%xmm6
|
||||
packssdw %xmm4,%xmm6
|
||||
packssdw (%ecx),%xmm6
|
||||
packuswb %xmm4,%xmm6
|
||||
packuswb (%ecx),%xmm6
|
||||
packusdw %xmm4,%xmm6
|
||||
packusdw (%ecx),%xmm6
|
||||
paddb %xmm4,%xmm6
|
||||
paddb (%ecx),%xmm6
|
||||
paddw %xmm4,%xmm6
|
||||
paddw (%ecx),%xmm6
|
||||
paddd %xmm4,%xmm6
|
||||
paddd (%ecx),%xmm6
|
||||
paddq %xmm4,%xmm6
|
||||
paddq (%ecx),%xmm6
|
||||
paddsb %xmm4,%xmm6
|
||||
paddsb (%ecx),%xmm6
|
||||
paddsw %xmm4,%xmm6
|
||||
paddsw (%ecx),%xmm6
|
||||
paddusb %xmm4,%xmm6
|
||||
paddusb (%ecx),%xmm6
|
||||
paddusw %xmm4,%xmm6
|
||||
paddusw (%ecx),%xmm6
|
||||
pand %xmm4,%xmm6
|
||||
pand (%ecx),%xmm6
|
||||
pandn %xmm4,%xmm6
|
||||
pandn (%ecx),%xmm6
|
||||
pavgb %xmm4,%xmm6
|
||||
pavgb (%ecx),%xmm6
|
||||
pavgw %xmm4,%xmm6
|
||||
pavgw (%ecx),%xmm6
|
||||
pcmpeqb %xmm4,%xmm6
|
||||
pcmpeqb (%ecx),%xmm6
|
||||
pcmpeqw %xmm4,%xmm6
|
||||
pcmpeqw (%ecx),%xmm6
|
||||
pcmpeqd %xmm4,%xmm6
|
||||
pcmpeqd (%ecx),%xmm6
|
||||
pcmpeqq %xmm4,%xmm6
|
||||
pcmpeqq (%ecx),%xmm6
|
||||
pcmpgtb %xmm4,%xmm6
|
||||
pcmpgtb (%ecx),%xmm6
|
||||
pcmpgtw %xmm4,%xmm6
|
||||
pcmpgtw (%ecx),%xmm6
|
||||
pcmpgtd %xmm4,%xmm6
|
||||
pcmpgtd (%ecx),%xmm6
|
||||
pcmpgtq %xmm4,%xmm6
|
||||
pcmpgtq (%ecx),%xmm6
|
||||
phaddw %xmm4,%xmm6
|
||||
phaddw (%ecx),%xmm6
|
||||
phaddd %xmm4,%xmm6
|
||||
phaddd (%ecx),%xmm6
|
||||
phaddsw %xmm4,%xmm6
|
||||
phaddsw (%ecx),%xmm6
|
||||
phsubw %xmm4,%xmm6
|
||||
phsubw (%ecx),%xmm6
|
||||
phsubd %xmm4,%xmm6
|
||||
phsubd (%ecx),%xmm6
|
||||
phsubsw %xmm4,%xmm6
|
||||
phsubsw (%ecx),%xmm6
|
||||
pmaddwd %xmm4,%xmm6
|
||||
pmaddwd (%ecx),%xmm6
|
||||
pmaddubsw %xmm4,%xmm6
|
||||
pmaddubsw (%ecx),%xmm6
|
||||
pmaxsb %xmm4,%xmm6
|
||||
pmaxsb (%ecx),%xmm6
|
||||
pmaxsw %xmm4,%xmm6
|
||||
pmaxsw (%ecx),%xmm6
|
||||
pmaxsd %xmm4,%xmm6
|
||||
pmaxsd (%ecx),%xmm6
|
||||
pmaxub %xmm4,%xmm6
|
||||
pmaxub (%ecx),%xmm6
|
||||
pmaxuw %xmm4,%xmm6
|
||||
pmaxuw (%ecx),%xmm6
|
||||
pmaxud %xmm4,%xmm6
|
||||
pmaxud (%ecx),%xmm6
|
||||
pminsb %xmm4,%xmm6
|
||||
pminsb (%ecx),%xmm6
|
||||
pminsw %xmm4,%xmm6
|
||||
pminsw (%ecx),%xmm6
|
||||
pminsd %xmm4,%xmm6
|
||||
pminsd (%ecx),%xmm6
|
||||
pminub %xmm4,%xmm6
|
||||
pminub (%ecx),%xmm6
|
||||
pminuw %xmm4,%xmm6
|
||||
pminuw (%ecx),%xmm6
|
||||
pminud %xmm4,%xmm6
|
||||
pminud (%ecx),%xmm6
|
||||
pmulhuw %xmm4,%xmm6
|
||||
pmulhuw (%ecx),%xmm6
|
||||
pmulhrsw %xmm4,%xmm6
|
||||
pmulhrsw (%ecx),%xmm6
|
||||
pmulhw %xmm4,%xmm6
|
||||
pmulhw (%ecx),%xmm6
|
||||
pmullw %xmm4,%xmm6
|
||||
pmullw (%ecx),%xmm6
|
||||
pmulld %xmm4,%xmm6
|
||||
pmulld (%ecx),%xmm6
|
||||
pmuludq %xmm4,%xmm6
|
||||
pmuludq (%ecx),%xmm6
|
||||
pmuldq %xmm4,%xmm6
|
||||
pmuldq (%ecx),%xmm6
|
||||
por %xmm4,%xmm6
|
||||
por (%ecx),%xmm6
|
||||
psadbw %xmm4,%xmm6
|
||||
psadbw (%ecx),%xmm6
|
||||
pshufb %xmm4,%xmm6
|
||||
pshufb (%ecx),%xmm6
|
||||
psignb %xmm4,%xmm6
|
||||
psignb (%ecx),%xmm6
|
||||
psignw %xmm4,%xmm6
|
||||
psignw (%ecx),%xmm6
|
||||
psignd %xmm4,%xmm6
|
||||
psignd (%ecx),%xmm6
|
||||
psllw %xmm4,%xmm6
|
||||
psllw (%ecx),%xmm6
|
||||
pslld %xmm4,%xmm6
|
||||
pslld (%ecx),%xmm6
|
||||
psllq %xmm4,%xmm6
|
||||
psllq (%ecx),%xmm6
|
||||
psraw %xmm4,%xmm6
|
||||
psraw (%ecx),%xmm6
|
||||
psrad %xmm4,%xmm6
|
||||
psrad (%ecx),%xmm6
|
||||
psrlw %xmm4,%xmm6
|
||||
psrlw (%ecx),%xmm6
|
||||
psrld %xmm4,%xmm6
|
||||
psrld (%ecx),%xmm6
|
||||
psrlq %xmm4,%xmm6
|
||||
psrlq (%ecx),%xmm6
|
||||
psubb %xmm4,%xmm6
|
||||
psubb (%ecx),%xmm6
|
||||
psubw %xmm4,%xmm6
|
||||
psubw (%ecx),%xmm6
|
||||
psubd %xmm4,%xmm6
|
||||
psubd (%ecx),%xmm6
|
||||
psubq %xmm4,%xmm6
|
||||
psubq (%ecx),%xmm6
|
||||
psubsb %xmm4,%xmm6
|
||||
psubsb (%ecx),%xmm6
|
||||
psubsw %xmm4,%xmm6
|
||||
psubsw (%ecx),%xmm6
|
||||
psubusb %xmm4,%xmm6
|
||||
psubusb (%ecx),%xmm6
|
||||
psubusw %xmm4,%xmm6
|
||||
psubusw (%ecx),%xmm6
|
||||
punpckhbw %xmm4,%xmm6
|
||||
punpckhbw (%ecx),%xmm6
|
||||
punpckhwd %xmm4,%xmm6
|
||||
punpckhwd (%ecx),%xmm6
|
||||
punpckhdq %xmm4,%xmm6
|
||||
punpckhdq (%ecx),%xmm6
|
||||
punpckhqdq %xmm4,%xmm6
|
||||
punpckhqdq (%ecx),%xmm6
|
||||
punpcklbw %xmm4,%xmm6
|
||||
punpcklbw (%ecx),%xmm6
|
||||
punpcklwd %xmm4,%xmm6
|
||||
punpcklwd (%ecx),%xmm6
|
||||
punpckldq %xmm4,%xmm6
|
||||
punpckldq (%ecx),%xmm6
|
||||
punpcklqdq %xmm4,%xmm6
|
||||
punpcklqdq (%ecx),%xmm6
|
||||
pxor %xmm4,%xmm6
|
||||
pxor (%ecx),%xmm6
|
||||
subpd %xmm4,%xmm6
|
||||
subpd (%ecx),%xmm6
|
||||
subps %xmm4,%xmm6
|
||||
subps (%ecx),%xmm6
|
||||
unpckhpd %xmm4,%xmm6
|
||||
unpckhpd (%ecx),%xmm6
|
||||
unpckhps %xmm4,%xmm6
|
||||
unpckhps (%ecx),%xmm6
|
||||
unpcklpd %xmm4,%xmm6
|
||||
unpcklpd (%ecx),%xmm6
|
||||
unpcklps %xmm4,%xmm6
|
||||
unpcklps (%ecx),%xmm6
|
||||
xorpd %xmm4,%xmm6
|
||||
xorpd (%ecx),%xmm6
|
||||
xorps %xmm4,%xmm6
|
||||
xorps (%ecx),%xmm6
|
||||
cmpeqpd %xmm4,%xmm6
|
||||
cmpeqpd (%ecx),%xmm6
|
||||
cmpeqps %xmm4,%xmm6
|
||||
cmpeqps (%ecx),%xmm6
|
||||
cmpltpd %xmm4,%xmm6
|
||||
cmpltpd (%ecx),%xmm6
|
||||
cmpltps %xmm4,%xmm6
|
||||
cmpltps (%ecx),%xmm6
|
||||
cmplepd %xmm4,%xmm6
|
||||
cmplepd (%ecx),%xmm6
|
||||
cmpleps %xmm4,%xmm6
|
||||
cmpleps (%ecx),%xmm6
|
||||
cmpunordpd %xmm4,%xmm6
|
||||
cmpunordpd (%ecx),%xmm6
|
||||
cmpunordps %xmm4,%xmm6
|
||||
cmpunordps (%ecx),%xmm6
|
||||
cmpneqpd %xmm4,%xmm6
|
||||
cmpneqpd (%ecx),%xmm6
|
||||
cmpneqps %xmm4,%xmm6
|
||||
cmpneqps (%ecx),%xmm6
|
||||
cmpnltpd %xmm4,%xmm6
|
||||
cmpnltpd (%ecx),%xmm6
|
||||
cmpnltps %xmm4,%xmm6
|
||||
cmpnltps (%ecx),%xmm6
|
||||
cmpnlepd %xmm4,%xmm6
|
||||
cmpnlepd (%ecx),%xmm6
|
||||
cmpnleps %xmm4,%xmm6
|
||||
cmpnleps (%ecx),%xmm6
|
||||
cmpordpd %xmm4,%xmm6
|
||||
cmpordpd (%ecx),%xmm6
|
||||
cmpordps %xmm4,%xmm6
|
||||
cmpordps (%ecx),%xmm6
|
||||
|
||||
# Tests for op imm8, xmm/mem128, xmm
|
||||
pcmpestri $100,%xmm4,%xmm6
|
||||
pcmpestri $100,(%ecx),%xmm6
|
||||
pcmpestrm $100,%xmm4,%xmm6
|
||||
pcmpestrm $100,(%ecx),%xmm6
|
||||
pcmpistri $100,%xmm4,%xmm6
|
||||
pcmpistri $100,(%ecx),%xmm6
|
||||
pcmpistrm $100,%xmm4,%xmm6
|
||||
pcmpistrm $100,(%ecx),%xmm6
|
||||
pshufd $100,%xmm4,%xmm6
|
||||
pshufd $100,(%ecx),%xmm6
|
||||
pshufhw $100,%xmm4,%xmm6
|
||||
pshufhw $100,(%ecx),%xmm6
|
||||
pshuflw $100,%xmm4,%xmm6
|
||||
pshuflw $100,(%ecx),%xmm6
|
||||
roundpd $100,%xmm4,%xmm6
|
||||
roundpd $100,(%ecx),%xmm6
|
||||
roundps $100,%xmm4,%xmm6
|
||||
roundps $100,(%ecx),%xmm6
|
||||
|
||||
# Tests for op imm8, xmm/mem128, xmm[, xmm]
|
||||
blendpd $100,%xmm4,%xmm6
|
||||
blendpd $100,(%ecx),%xmm6
|
||||
blendps $100,%xmm4,%xmm6
|
||||
blendps $100,(%ecx),%xmm6
|
||||
cmppd $100,%xmm4,%xmm6
|
||||
cmppd $100,(%ecx),%xmm6
|
||||
cmpps $100,%xmm4,%xmm6
|
||||
cmpps $100,(%ecx),%xmm6
|
||||
dppd $100,%xmm4,%xmm6
|
||||
dppd $100,(%ecx),%xmm6
|
||||
dpps $100,%xmm4,%xmm6
|
||||
dpps $100,(%ecx),%xmm6
|
||||
mpsadbw $100,%xmm4,%xmm6
|
||||
mpsadbw $100,(%ecx),%xmm6
|
||||
palignr $100,%xmm4,%xmm6
|
||||
palignr $100,(%ecx),%xmm6
|
||||
pblendw $100,%xmm4,%xmm6
|
||||
pblendw $100,(%ecx),%xmm6
|
||||
shufpd $100,%xmm4,%xmm6
|
||||
shufpd $100,(%ecx),%xmm6
|
||||
shufps $100,%xmm4,%xmm6
|
||||
shufps $100,(%ecx),%xmm6
|
||||
|
||||
# Tests for op xmm0, xmm/mem128, xmm[, xmm]
|
||||
blendvpd %xmm0,%xmm4,%xmm6
|
||||
blendvpd %xmm0,(%ecx),%xmm6
|
||||
blendvpd %xmm4,%xmm6
|
||||
blendvpd (%ecx),%xmm6
|
||||
blendvps %xmm0,%xmm4,%xmm6
|
||||
blendvps %xmm0,(%ecx),%xmm6
|
||||
blendvps %xmm4,%xmm6
|
||||
blendvps (%ecx),%xmm6
|
||||
pblendvb %xmm0,%xmm4,%xmm6
|
||||
pblendvb %xmm0,(%ecx),%xmm6
|
||||
pblendvb %xmm4,%xmm6
|
||||
pblendvb (%ecx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem64, xmm
|
||||
comisd %xmm4,%xmm6
|
||||
comisd (%ecx),%xmm4
|
||||
cvtdq2pd %xmm4,%xmm6
|
||||
cvtdq2pd (%ecx),%xmm4
|
||||
cvtps2pd %xmm4,%xmm6
|
||||
cvtps2pd (%ecx),%xmm4
|
||||
movddup %xmm4,%xmm6
|
||||
movddup (%ecx),%xmm4
|
||||
pmovsxbw %xmm4,%xmm6
|
||||
pmovsxbw (%ecx),%xmm4
|
||||
pmovsxwd %xmm4,%xmm6
|
||||
pmovsxwd (%ecx),%xmm4
|
||||
pmovsxdq %xmm4,%xmm6
|
||||
pmovsxdq (%ecx),%xmm4
|
||||
pmovzxbw %xmm4,%xmm6
|
||||
pmovzxbw (%ecx),%xmm4
|
||||
pmovzxwd %xmm4,%xmm6
|
||||
pmovzxwd (%ecx),%xmm4
|
||||
pmovzxdq %xmm4,%xmm6
|
||||
pmovzxdq (%ecx),%xmm4
|
||||
ucomisd %xmm4,%xmm6
|
||||
ucomisd (%ecx),%xmm4
|
||||
|
||||
# Tests for op mem64, xmm
|
||||
movsd (%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm, mem64
|
||||
movlpd %xmm4,(%ecx)
|
||||
movlps %xmm4,(%ecx)
|
||||
movhpd %xmm4,(%ecx)
|
||||
movhps %xmm4,(%ecx)
|
||||
movsd %xmm4,(%ecx)
|
||||
|
||||
# Tests for op xmm, regq/mem64
|
||||
# Tests for op regq/mem64, xmm
|
||||
movq %xmm4,(%ecx)
|
||||
movq (%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm/mem64, regl
|
||||
cvtsd2si %xmm4,%ecx
|
||||
cvtsd2si (%ecx),%ecx
|
||||
cvttsd2si %xmm4,%ecx
|
||||
cvttsd2si (%ecx),%ecx
|
||||
|
||||
# Tests for op mem64, xmm[, xmm]
|
||||
movlpd (%ecx),%xmm4
|
||||
movlps (%ecx),%xmm4
|
||||
movhpd (%ecx),%xmm4
|
||||
movhps (%ecx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm/mem64, xmm[, xmm]
|
||||
cmpsd $100,%xmm4,%xmm6
|
||||
cmpsd $100,(%ecx),%xmm6
|
||||
roundsd $100,%xmm4,%xmm6
|
||||
roundsd $100,(%ecx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem64, xmm[, xmm]
|
||||
addsd %xmm4,%xmm6
|
||||
addsd (%ecx),%xmm6
|
||||
cvtsd2ss %xmm4,%xmm6
|
||||
cvtsd2ss (%ecx),%xmm6
|
||||
divsd %xmm4,%xmm6
|
||||
divsd (%ecx),%xmm6
|
||||
maxsd %xmm4,%xmm6
|
||||
maxsd (%ecx),%xmm6
|
||||
minsd %xmm4,%xmm6
|
||||
minsd (%ecx),%xmm6
|
||||
mulsd %xmm4,%xmm6
|
||||
mulsd (%ecx),%xmm6
|
||||
sqrtsd %xmm4,%xmm6
|
||||
sqrtsd (%ecx),%xmm6
|
||||
subsd %xmm4,%xmm6
|
||||
subsd (%ecx),%xmm6
|
||||
cmpeqsd %xmm4,%xmm6
|
||||
cmpeqsd (%ecx),%xmm6
|
||||
cmpltsd %xmm4,%xmm6
|
||||
cmpltsd (%ecx),%xmm6
|
||||
cmplesd %xmm4,%xmm6
|
||||
cmplesd (%ecx),%xmm6
|
||||
cmpunordsd %xmm4,%xmm6
|
||||
cmpunordsd (%ecx),%xmm6
|
||||
cmpneqsd %xmm4,%xmm6
|
||||
cmpneqsd (%ecx),%xmm6
|
||||
cmpnltsd %xmm4,%xmm6
|
||||
cmpnltsd (%ecx),%xmm6
|
||||
cmpnlesd %xmm4,%xmm6
|
||||
cmpnlesd (%ecx),%xmm6
|
||||
cmpordsd %xmm4,%xmm6
|
||||
cmpordsd (%ecx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem32, xmm[, xmm]
|
||||
addss %xmm4,%xmm6
|
||||
addss (%ecx),%xmm6
|
||||
cvtss2sd %xmm4,%xmm6
|
||||
cvtss2sd (%ecx),%xmm6
|
||||
divss %xmm4,%xmm6
|
||||
divss (%ecx),%xmm6
|
||||
maxss %xmm4,%xmm6
|
||||
maxss (%ecx),%xmm6
|
||||
minss %xmm4,%xmm6
|
||||
minss (%ecx),%xmm6
|
||||
mulss %xmm4,%xmm6
|
||||
mulss (%ecx),%xmm6
|
||||
rcpss %xmm4,%xmm6
|
||||
rcpss (%ecx),%xmm6
|
||||
rsqrtss %xmm4,%xmm6
|
||||
rsqrtss (%ecx),%xmm6
|
||||
sqrtss %xmm4,%xmm6
|
||||
sqrtss (%ecx),%xmm6
|
||||
subss %xmm4,%xmm6
|
||||
subss (%ecx),%xmm6
|
||||
cmpeqss %xmm4,%xmm6
|
||||
cmpeqss (%ecx),%xmm6
|
||||
cmpltss %xmm4,%xmm6
|
||||
cmpltss (%ecx),%xmm6
|
||||
cmpless %xmm4,%xmm6
|
||||
cmpless (%ecx),%xmm6
|
||||
cmpunordss %xmm4,%xmm6
|
||||
cmpunordss (%ecx),%xmm6
|
||||
cmpneqss %xmm4,%xmm6
|
||||
cmpneqss (%ecx),%xmm6
|
||||
cmpnltss %xmm4,%xmm6
|
||||
cmpnltss (%ecx),%xmm6
|
||||
cmpnless %xmm4,%xmm6
|
||||
cmpnless (%ecx),%xmm6
|
||||
cmpordss %xmm4,%xmm6
|
||||
cmpordss (%ecx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem32, xmm
|
||||
comiss %xmm4,%xmm6
|
||||
comiss (%ecx),%xmm4
|
||||
pmovsxbd %xmm4,%xmm6
|
||||
pmovsxbd (%ecx),%xmm4
|
||||
pmovsxwq %xmm4,%xmm6
|
||||
pmovsxwq (%ecx),%xmm4
|
||||
pmovzxbd %xmm4,%xmm6
|
||||
pmovzxbd (%ecx),%xmm4
|
||||
pmovzxwq %xmm4,%xmm6
|
||||
pmovzxwq (%ecx),%xmm4
|
||||
ucomiss %xmm4,%xmm6
|
||||
ucomiss (%ecx),%xmm4
|
||||
|
||||
# Tests for op mem32, xmm
|
||||
movss (%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm, mem32
|
||||
movss %xmm4,(%ecx)
|
||||
|
||||
# Tests for op xmm, regl/mem32
|
||||
# Tests for op regl/mem32, xmm
|
||||
movd %xmm4,%ecx
|
||||
movd %xmm4,(%ecx)
|
||||
movd %ecx,%xmm4
|
||||
movd (%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm/mem32, regl
|
||||
cvtss2si %xmm4,%ecx
|
||||
cvtss2si (%ecx),%ecx
|
||||
cvttss2si %xmm4,%ecx
|
||||
cvttss2si (%ecx),%ecx
|
||||
|
||||
# Tests for op imm8, xmm, regq/mem32
|
||||
extractps $100,%xmm4,(%ecx)
|
||||
# Tests for op imm8, xmm, regl/mem32
|
||||
pextrd $100,%xmm4,%ecx
|
||||
pextrd $100,%xmm4,(%ecx)
|
||||
extractps $100,%xmm4,%ecx
|
||||
extractps $100,%xmm4,(%ecx)
|
||||
|
||||
# Tests for op regl/mem32, xmm[, xmm]
|
||||
cvtsi2sd %ecx,%xmm4
|
||||
cvtsi2sd (%ecx),%xmm4
|
||||
cvtsi2ss %ecx,%xmm4
|
||||
cvtsi2ss (%ecx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm/mem32, xmm[, xmm]
|
||||
cmpss $100,%xmm4,%xmm6
|
||||
cmpss $100,(%ecx),%xmm6
|
||||
insertps $100,%xmm4,%xmm6
|
||||
insertps $100,(%ecx),%xmm6
|
||||
roundss $100,%xmm4,%xmm6
|
||||
roundss $100,(%ecx),%xmm6
|
||||
|
||||
# Tests for op xmm/m16, xmm
|
||||
pmovsxbq %xmm4,%xmm6
|
||||
pmovsxbq (%ecx),%xmm4
|
||||
pmovzxbq %xmm4,%xmm6
|
||||
pmovzxbq (%ecx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regl/mem16
|
||||
pextrw $100,%xmm4,%ecx
|
||||
pextrw $100,%xmm4,(%ecx)
|
||||
|
||||
# Tests for op imm8, xmm, regq/mem16
|
||||
pextrw $100,%xmm4,(%ecx)
|
||||
|
||||
# Tests for op imm8, regl/mem16, xmm[, xmm]
|
||||
pinsrw $100,%ecx,%xmm4
|
||||
pinsrw $100,(%ecx),%xmm4
|
||||
|
||||
|
||||
# Tests for op imm8, xmm, regl/mem8
|
||||
pextrb $100,%xmm4,%ecx
|
||||
pextrb $100,%xmm4,(%ecx)
|
||||
|
||||
# Tests for op imm8, regl/mem8, xmm[, xmm]
|
||||
pinsrb $100,%ecx,%xmm4
|
||||
pinsrb $100,(%ecx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regq/mem8
|
||||
pextrb $100,%xmm4,(%ecx)
|
||||
|
||||
# Tests for op imm8, regl/mem8, xmm[, xmm]
|
||||
pinsrb $100,%ecx,%xmm4
|
||||
pinsrb $100,(%ecx),%xmm4
|
||||
|
||||
# Tests for op xmm, xmm
|
||||
maskmovdqu %xmm4,%xmm6
|
||||
movq %xmm4,%xmm6
|
||||
|
||||
# Tests for op xmm, regl
|
||||
movmskpd %xmm4,%ecx
|
||||
movmskps %xmm4,%ecx
|
||||
pmovmskb %xmm4,%ecx
|
||||
# Tests for op xmm, xmm[, xmm]
|
||||
movhlps %xmm4,%xmm6
|
||||
movlhps %xmm4,%xmm6
|
||||
movsd %xmm4,%xmm6
|
||||
movss %xmm4,%xmm6
|
||||
|
||||
# Tests for op imm8, xmm[, xmm]
|
||||
pslld $100,%xmm4
|
||||
pslldq $100,%xmm4
|
||||
psllq $100,%xmm4
|
||||
psllw $100,%xmm4
|
||||
psrad $100,%xmm4
|
||||
psraw $100,%xmm4
|
||||
psrld $100,%xmm4
|
||||
psrldq $100,%xmm4
|
||||
psrlq $100,%xmm4
|
||||
psrlw $100,%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regl
|
||||
pextrw $100,%xmm4,%ecx
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
#source: x86-64-aes.s
|
||||
#as: -J
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86-64 AES (Intel mode)
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[rcx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist xmm0,XMMWORD PTR \[rcx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist xmm0,xmm1,0x8
|
||||
#pass
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
#as: -J
|
||||
#objdump: -dw
|
||||
#name: x86-64 AES
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc c1 aesenc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd 01 aesenclast \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dd c1 aesenclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de 01 aesdec \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 de c1 aesdec %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df 01 aesdeclast \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 df c1 aesdeclast %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db 01 aesimc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 38 db c1 aesimc %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df 01 08 aeskeygenassist \$0x8,\(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a df c1 08 aeskeygenassist \$0x8,%xmm1,%xmm0
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Check 64bit AES new instructions.
|
||||
|
||||
.text
|
||||
foo:
|
||||
aesenc (%rcx),%xmm0
|
||||
aesenc %xmm1,%xmm0
|
||||
aesenclast (%rcx),%xmm0
|
||||
aesenclast %xmm1,%xmm0
|
||||
aesdec (%rcx),%xmm0
|
||||
aesdec %xmm1,%xmm0
|
||||
aesdeclast (%rcx),%xmm0
|
||||
aesdeclast %xmm1,%xmm0
|
||||
aesimc (%rcx),%xmm0
|
||||
aesimc %xmm1,%xmm0
|
||||
aeskeygenassist $8,(%rcx),%xmm0
|
||||
aeskeygenassist $8,%xmm1,%xmm0
|
||||
|
||||
.intel_syntax noprefix
|
||||
aesenc xmm0,XMMWORD PTR [rcx]
|
||||
aesenc xmm0,xmm1
|
||||
aesenclast xmm0,XMMWORD PTR [rcx]
|
||||
aesenclast xmm0,xmm1
|
||||
aesdec xmm0,XMMWORD PTR [rcx]
|
||||
aesdec xmm0,xmm1
|
||||
aesdeclast xmm0,XMMWORD PTR [rcx]
|
||||
aesdeclast xmm0,xmm1
|
||||
aesimc xmm0,XMMWORD PTR [rcx]
|
||||
aesimc xmm0,xmm1
|
||||
aeskeygenassist xmm0,XMMWORD PTR [rcx],8
|
||||
aeskeygenassist xmm0,xmm1,8
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
#as: -march=generic64+sse4+vmx+smx+xsave+sse5+3dnowa+svme+padlock
|
||||
#as: -march=generic64+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
|
||||
#objdump: -dw
|
||||
#name: x86-64 arch 2
|
||||
|
||||
|
|
@ -15,9 +15,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3
|
||||
[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3
|
||||
[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
|
||||
[ ]*[a-f0-9]+: c5 fc 77 vzeroall
|
||||
[ ]*[a-f0-9]+: 0f 01 c4 vmxoff
|
||||
[ ]*[a-f0-9]+: 0f 37 getsec
|
||||
[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
|
||||
[ ]*[a-f0-9]+: 66 0f 38 dc 01 aesenc \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: c4 e3 ed 69 fc 60 vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3
|
||||
[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1
|
||||
|
|
|
|||
|
|
@ -16,12 +16,20 @@ phaddw %xmm4,%xmm3
|
|||
phminposuw %xmm1,%xmm3
|
||||
# SSE4.2
|
||||
crc32 %ecx,%ebx
|
||||
# AVX
|
||||
vzeroall
|
||||
# VMX
|
||||
vmxoff
|
||||
# SMX
|
||||
getsec
|
||||
# Xsave
|
||||
xgetbv
|
||||
# AES
|
||||
aesenc (%rcx),%xmm0
|
||||
# CLMUL
|
||||
pclmulqdq $8,%xmm1,%xmm0
|
||||
# FMA
|
||||
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
# 3DNow
|
||||
pmulhrw %mm4,%mm3
|
||||
# 3DNow Extensions
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,31 @@
|
|||
#source: x86-64-clmul.s
|
||||
#as: -J
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86-64 CLMUL (Intel mode)
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[rcx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq xmm0,XMMWORD PTR \[rcx\],0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq xmm0,xmm1,0x8
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq xmm0,xmm1
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq xmm0,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq xmm0,xmm1
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#as: -J
|
||||
#objdump: -dw
|
||||
#name: x86-64 CLMUL
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 08 pclmulqdq \$0x8,\(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 08 pclmulqdq \$0x8,%xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 00 pclmullqlqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 00 pclmullqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 01 pclmulhqlqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 01 pclmulhqlqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 10 pclmullqhqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 10 pclmullqhqdq %xmm1,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 01 11 pclmulhqhqdq \(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 3a 44 c1 11 pclmulhqhqdq %xmm1,%xmm0
|
||||
#pass
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
# Check 64bit CLMUL new instructions.
|
||||
|
||||
.text
|
||||
foo:
|
||||
pclmulqdq $8,(%rcx),%xmm0
|
||||
pclmulqdq $8,%xmm1,%xmm0
|
||||
pclmullqlqdq (%rcx),%xmm0
|
||||
pclmullqlqdq %xmm1,%xmm0
|
||||
pclmulhqlqdq (%rcx),%xmm0
|
||||
pclmulhqlqdq %xmm1,%xmm0
|
||||
pclmullqhqdq (%rcx),%xmm0
|
||||
pclmullqhqdq %xmm1,%xmm0
|
||||
pclmulhqhqdq (%rcx),%xmm0
|
||||
pclmulhqhqdq %xmm1,%xmm0
|
||||
|
||||
.intel_syntax noprefix
|
||||
pclmulqdq xmm0,XMMWORD PTR [rcx],8
|
||||
pclmulqdq xmm0,xmm1,8
|
||||
pclmullqlqdq xmm0,XMMWORD PTR [rcx]
|
||||
pclmullqlqdq xmm0,xmm1
|
||||
pclmulhqlqdq xmm0,XMMWORD PTR [rcx]
|
||||
pclmulhqlqdq xmm0,xmm1
|
||||
pclmullqhqdq xmm0,XMMWORD PTR [rcx]
|
||||
pclmullqhqdq xmm0,xmm1
|
||||
pclmulhqhqdq xmm0,XMMWORD PTR [rcx]
|
||||
pclmulhqhqdq xmm0,xmm1
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:25: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:27: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:35: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:39: Error: .*
|
||||
.*:40: Error: .*
|
||||
.*:41: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:43: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:45: Error: .*
|
||||
.*:46: Error: .*
|
||||
.*:47: Error: .*
|
||||
.*:48: Error: .*
|
||||
.*:49: Error: .*
|
||||
.*:50: Error: .*
|
||||
.*:51: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:53: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:55: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check illegal 64bit AVX instructions
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+_start:
|
||||
[ ]*4[ ]+vcvtpd2dq \(%rcx\),%xmm2
|
||||
[ ]*5[ ]+vcvtpd2ps \(%rcx\),%xmm2
|
||||
[ ]*6[ ]+vcvttpd2dq \(%rcx\),%xmm2
|
||||
[ ]*7[ ]+vfmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*8[ ]+vfmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*9[ ]+vfmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*10[ ]+vfmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*11[ ]+vfmaddsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*12[ ]+vfmaddsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*13[ ]+vfmsubaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*14[ ]+vfmsubaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*15[ ]+vfmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*16[ ]+vfmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*17[ ]+vfmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*18[ ]+vfmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*19[ ]+vfnmaddpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*20[ ]+vfnmaddps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*21[ ]+vfnmaddsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*22[ ]+vfnmaddss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*23[ ]+vfnmsubpd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*24[ ]+vfnmsubps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*25[ ]+vfnmsubsd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*26[ ]+vfnmsubss \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*27[ ]+vpermil2pd \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*28[ ]+vpermil2ps \$17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
[ ]*29[ ]+
|
||||
[ ]*30[ ]+\.intel_syntax noprefix
|
||||
[ ]*31[ ]+vcvtpd2dq xmm2,\[rcx\]
|
||||
[ ]*32[ ]+vcvtpd2ps xmm2,\[rcx\]
|
||||
[ ]*33[ ]+vcvttpd2dq xmm2,\[rcx\]
|
||||
[ ]*34[ ]+vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*35[ ]+vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*36[ ]+vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*37[ ]+vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*38[ ]+vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*39[ ]+vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*40[ ]+vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*41[ ]+vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*42[ ]+vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*43[ ]+vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*44[ ]+vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*45[ ]+vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*46[ ]+vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*47[ ]+vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*48[ ]+vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*49[ ]+vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*50[ ]+vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*51[ ]+vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*52[ ]+vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*53[ ]+vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*54[ ]+vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
[ ]*55[ ]+vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
# Check illegal 64bit AVX instructions
|
||||
.text
|
||||
_start:
|
||||
vcvtpd2dq (%rcx),%xmm2
|
||||
vcvtpd2ps (%rcx),%xmm2
|
||||
vcvttpd2dq (%rcx),%xmm2
|
||||
vfmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmaddsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmaddss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubpd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubsd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vfnmsubss $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2pd $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
vpermil2ps $17,%xmm4,%xmm2,%xmm1,%xmm3
|
||||
|
||||
.intel_syntax noprefix
|
||||
vcvtpd2dq xmm2,[rcx]
|
||||
vcvtpd2ps xmm2,[rcx]
|
||||
vcvttpd2dq xmm2,[rcx]
|
||||
vfmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmaddsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmaddss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubpd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubsd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vfnmsubss xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2pd xmm3,xmm1,xmm2,xmm4,0x10
|
||||
vpermil2ps xmm3,xmm1,xmm2,xmm4,0x10
|
||||
|
|
@ -42,17 +42,9 @@ Disassembly of section .text:
|
|||
0+e <into>:
|
||||
[ ]*[a-f0-9]+: ce \(bad\)
|
||||
|
||||
0+f <lds>:
|
||||
[ ]*[a-f0-9]+: c5 \(bad\)
|
||||
[ ]*[a-f0-9]+: 10 c4 adc ah,al
|
||||
|
||||
0+11 <les>:
|
||||
[ ]*[a-f0-9]+: c4 \(bad\)
|
||||
[ ]*[a-f0-9]+: 10 60 61 adc BYTE PTR \[rax\+0x61\],ah
|
||||
|
||||
0+13 <pusha>:
|
||||
0+f <pusha>:
|
||||
[ ]*[a-f0-9]+: 60 \(bad\)
|
||||
|
||||
0+14 <popa>:
|
||||
0+10 <popa>:
|
||||
[ ]*[a-f0-9]+: 61 \(bad\)
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -41,17 +41,9 @@ Disassembly of section .text:
|
|||
0+e <into>:
|
||||
[ ]*[a-f0-9]+: ce \(bad\)
|
||||
|
||||
0+f <lds>:
|
||||
[ ]*[a-f0-9]+: c5 \(bad\)
|
||||
[ ]*[a-f0-9]+: 10 c4 adc %al,%ah
|
||||
|
||||
0+11 <les>:
|
||||
[ ]*[a-f0-9]+: c4 \(bad\)
|
||||
[ ]*[a-f0-9]+: 10 60 61 adc %ah,0x61\(%rax\)
|
||||
|
||||
0+13 <pusha>:
|
||||
0+f <pusha>:
|
||||
[ ]*[a-f0-9]+: 60 \(bad\)
|
||||
|
||||
0+14 <popa>:
|
||||
0+10 <popa>:
|
||||
[ ]*[a-f0-9]+: 61 \(bad\)
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -20,10 +20,6 @@ das:
|
|||
das
|
||||
into:
|
||||
into
|
||||
lds:
|
||||
lds (%eax),%edx
|
||||
les:
|
||||
les (%eax),%edx
|
||||
pusha:
|
||||
pusha
|
||||
popa:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,593 @@
|
|||
#as: -msse2avx
|
||||
#objdump: -dw
|
||||
#name: x86-64 SSE with AVX encoding
|
||||
|
||||
.*: file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: c5 f8 ae 11 vldmxcsr \(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 ae 19 vstmxcsr \(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 5b f4 vcvtdq2ps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 5b 21 vcvtdq2ps \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb e6 f4 vcvtpd2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb e6 21 vcvtpd2dqx \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 5a f4 vcvtpd2ps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 5a 21 vcvtpd2psx \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 5b f4 vcvtps2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 5b 21 vcvtps2dq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 e6 f4 vcvttpd2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 e6 21 vcvttpd2dqx \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 5b f4 vcvttps2dq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 5b 21 vcvttps2dq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 21 vmovapd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 21 vmovaps \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f 21 vmovdqa \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f 21 vmovdqu \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 16 f4 vmovshdup %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 16 21 vmovshdup \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 12 f4 vmovsldup %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 12 21 vmovsldup \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 21 vmovupd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 21 vmovups \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1c f4 vpabsb %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1c 21 vpabsb \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1d f4 vpabsw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1d 21 vpabsw \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1e f4 vpabsd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 1e 21 vpabsd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 41 f4 vphminposuw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 41 21 vphminposuw \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 17 f4 vptest %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 17 21 vptest \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 53 f4 vrcpps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 53 21 vrcpps \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 52 f4 vrsqrtps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 52 21 vrsqrtps \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 51 f4 vsqrtpd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 51 21 vsqrtpd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 51 f4 vsqrtps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 51 21 vsqrtps \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 21 vmovapd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 21 vmovaps %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f 21 vmovdqa %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f 21 vmovdqu %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 21 vmovupd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 21 vmovups %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 fb f0 21 vlddqu \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 2a 21 vmovntdqa \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 e7 21 vmovntdq %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 2b 21 vmovntpd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 2b 21 vmovntps %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 c9 58 f4 vaddpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 58 31 vaddpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 58 f4 vaddps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 58 31 vaddps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d0 f4 vaddsubpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d0 31 vaddsubpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb d0 f4 vaddsubps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb d0 31 vaddsubps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 55 f4 vandnpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 55 31 vandnpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 55 f4 vandnps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 55 31 vandnps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 54 f4 vandpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 54 31 vandpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 54 f4 vandps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 54 31 vandps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5e f4 vdivpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5e 31 vdivpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5e f4 vdivps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5e 31 vdivps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7c f4 vhaddpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7c 31 vhaddpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7c f4 vhaddps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7c 31 vhaddps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7d f4 vhsubpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 7d 31 vhsubpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7d f4 vhsubps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 7d 31 vhsubps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5f f4 vmaxpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5f 31 vmaxpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5f f4 vmaxps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5f 31 vmaxps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5d f4 vminpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5d 31 vminpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5d f4 vminps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5d 31 vminps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 59 f4 vmulpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 59 31 vmulpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 59 f4 vmulps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 59 31 vmulps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 56 f4 vorpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 56 31 vorpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 56 f4 vorps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 56 31 vorps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 63 f4 vpacksswb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 63 31 vpacksswb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6b f4 vpackssdw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6b 31 vpackssdw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 67 f4 vpackuswb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 67 31 vpackuswb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 2b f4 vpackusdw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 2b 31 vpackusdw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fc f4 vpaddb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fc 31 vpaddb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fd f4 vpaddw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fd 31 vpaddw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fe f4 vpaddd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fe 31 vpaddd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d4 f4 vpaddq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d4 31 vpaddq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ec f4 vpaddsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ec 31 vpaddsb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ed f4 vpaddsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ed 31 vpaddsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dc f4 vpaddusb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dc 31 vpaddusb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dd f4 vpaddusw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 dd 31 vpaddusw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 db f4 vpand %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 db 31 vpand \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 df f4 vpandn %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 df 31 vpandn \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e0 f4 vpavgb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e0 31 vpavgb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e3 f4 vpavgw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e3 31 vpavgw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 74 f4 vpcmpeqb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 74 31 vpcmpeqb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 75 f4 vpcmpeqw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 75 31 vpcmpeqw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 76 f4 vpcmpeqd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 76 31 vpcmpeqd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 29 f4 vpcmpeqq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 29 31 vpcmpeqq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 64 f4 vpcmpgtb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 64 31 vpcmpgtb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 65 f4 vpcmpgtw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 65 31 vpcmpgtw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 66 f4 vpcmpgtd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 66 31 vpcmpgtd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 37 f4 vpcmpgtq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 37 31 vpcmpgtq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 01 f4 vphaddw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 01 31 vphaddw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 02 f4 vphaddd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 02 31 vphaddd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 03 f4 vphaddsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 03 31 vphaddsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 05 f4 vphsubw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 05 31 vphsubw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 06 f4 vphsubd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 06 31 vphsubd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 07 f4 vphsubsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 07 31 vphsubsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f5 f4 vpmaddwd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f5 31 vpmaddwd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 04 f4 vpmaddubsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 04 31 vpmaddubsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3c f4 vpmaxsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3c 31 vpmaxsb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ee f4 vpmaxsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ee 31 vpmaxsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3d f4 vpmaxsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3d 31 vpmaxsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 de f4 vpmaxub %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 de 31 vpmaxub \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3e f4 vpmaxuw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3e 31 vpmaxuw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3f f4 vpmaxud %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3f 31 vpmaxud \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 38 f4 vpminsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 38 31 vpminsb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ea f4 vpminsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ea 31 vpminsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 39 f4 vpminsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 39 31 vpminsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 da f4 vpminub %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 da 31 vpminub \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3a f4 vpminuw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3a 31 vpminuw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3b f4 vpminud %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 3b 31 vpminud \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e4 f4 vpmulhuw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e4 31 vpmulhuw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0b f4 vpmulhrsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0b 31 vpmulhrsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e5 f4 vpmulhw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e5 31 vpmulhw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d5 f4 vpmullw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d5 31 vpmullw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 40 f4 vpmulld %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 40 31 vpmulld \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f4 f4 vpmuludq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f4 31 vpmuludq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 28 f4 vpmuldq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 28 31 vpmuldq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 eb f4 vpor %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 eb 31 vpor \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f6 f4 vpsadbw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f6 31 vpsadbw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 00 f4 vpshufb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 00 31 vpshufb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 08 f4 vpsignb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 08 31 vpsignb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 09 f4 vpsignw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 09 31 vpsignw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0a f4 vpsignd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 49 0a 31 vpsignd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f1 f4 vpsllw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f1 31 vpsllw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f2 f4 vpslld %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f2 31 vpslld \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f3 f4 vpsllq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f3 31 vpsllq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e1 f4 vpsraw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e1 31 vpsraw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e2 f4 vpsrad %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e2 31 vpsrad \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d1 f4 vpsrlw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d1 31 vpsrlw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d2 f4 vpsrld %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d2 31 vpsrld \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d3 f4 vpsrlq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d3 31 vpsrlq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f8 f4 vpsubb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f8 31 vpsubb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f9 f4 vpsubw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 f9 31 vpsubw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fa f4 vpsubd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fa 31 vpsubd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fb f4 vpsubq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 fb 31 vpsubq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e8 f4 vpsubsb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e8 31 vpsubsb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e9 f4 vpsubsw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 e9 31 vpsubsw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d8 f4 vpsubusb %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d8 31 vpsubusb \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d9 f4 vpsubusw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 d9 31 vpsubusw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 68 f4 vpunpckhbw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 68 31 vpunpckhbw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 69 f4 vpunpckhwd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 69 31 vpunpckhwd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6a f4 vpunpckhdq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6a 31 vpunpckhdq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6d f4 vpunpckhqdq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6d 31 vpunpckhqdq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 60 f4 vpunpcklbw %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 60 31 vpunpcklbw \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 61 f4 vpunpcklwd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 61 31 vpunpcklwd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 62 f4 vpunpckldq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 62 31 vpunpckldq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6c f4 vpunpcklqdq %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 6c 31 vpunpcklqdq \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ef f4 vpxor %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 ef 31 vpxor \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5c f4 vsubpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 5c 31 vsubpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5c f4 vsubps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 5c 31 vsubps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 15 f4 vunpckhpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 15 31 vunpckhpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 15 f4 vunpckhps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 15 31 vunpckhps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 14 f4 vunpcklpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 14 31 vunpcklpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 14 f4 vunpcklps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 14 31 vunpcklps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 57 f4 vxorpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 57 31 vxorpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 57 f4 vxorps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 57 31 vxorps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 00 vcmpeqpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 00 vcmpeqpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 00 vcmpeqps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 00 vcmpeqps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 01 vcmpltpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 01 vcmpltpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 01 vcmpltps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 01 vcmpltps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 02 vcmplepd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 02 vcmplepd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 02 vcmpleps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 02 vcmpleps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 03 vcmpunordpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 03 vcmpunordpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 03 vcmpunordps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 03 vcmpunordps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 04 vcmpneqpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 04 vcmpneqpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 04 vcmpneqps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 04 vcmpneqps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 05 vcmpnltpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 05 vcmpnltpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 05 vcmpnltps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 05 vcmpnltps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 06 vcmpnlepd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 06 vcmpnlepd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 06 vcmpnleps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 06 vcmpnleps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 07 vcmpordpd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 07 vcmpordpd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 07 vcmpordps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 07 vcmpordps \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 61 f4 64 vpcmpestri \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 61 31 64 vpcmpestri \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 60 f4 64 vpcmpestrm \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 60 31 64 vpcmpestrm \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 63 f4 64 vpcmpistri \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 63 31 64 vpcmpistri \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 62 f4 64 vpcmpistrm \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 62 31 64 vpcmpistrm \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 70 f4 64 vpshufd \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 70 31 64 vpshufd \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 70 f4 64 vpshufhw \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 70 31 64 vpshufhw \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb 70 f4 64 vpshuflw \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb 70 31 64 vpshuflw \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 09 f4 64 vroundpd \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 09 31 64 vroundpd \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 08 f4 64 vroundps \$0x64,%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 08 31 64 vroundps \$0x64,\(%rcx\),%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0d f4 64 vblendpd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0d 31 64 vblendpd \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0c f4 64 vblendps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0c 31 64 vblendps \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 f4 64 vcmppd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c2 31 64 vcmppd \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 f4 64 vcmpps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 31 64 vcmpps \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 41 f4 64 vdppd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 41 31 64 vdppd \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 40 f4 64 vdpps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 40 31 64 vdpps \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 42 f4 64 vmpsadbw \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 42 31 64 vmpsadbw \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0f f4 64 vpalignr \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0f 31 64 vpalignr \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0e f4 64 vpblendw \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0e 31 64 vpblendw \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c6 f4 64 vshufpd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c9 c6 31 64 vshufpd \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 f4 64 vshufps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 31 64 vshufps \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b f4 00 vblendvpd %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4b 31 00 vblendvpd %xmm0,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a f4 00 vblendvps %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4a 31 00 vblendvps %xmm0,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c f4 00 vpblendvb %xmm0,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 4c 31 00 vpblendvb %xmm0,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 2f f4 vcomisd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 2f 21 vcomisd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa e6 f4 vcvtdq2pd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa e6 21 vcvtdq2pd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 5a f4 vcvtps2pd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 5a 21 vcvtps2pd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb 12 f4 vmovddup %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fb 12 21 vmovddup \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 20 f4 vpmovsxbw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 20 21 vpmovsxbw \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 23 f4 vpmovsxwd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 23 21 vpmovsxwd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 25 f4 vpmovsxdq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 25 21 vpmovsxdq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 30 f4 vpmovzxbw %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 30 21 vpmovzxbw \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 33 f4 vpmovzxwd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 33 21 vpmovzxwd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 35 f4 vpmovzxdq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 35 21 vpmovzxdq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 2e f4 vucomisd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 2e 21 vucomisd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb 10 21 vmovsd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 13 21 vmovlpd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 13 21 vmovlps %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 17 21 vmovhpd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f8 17 21 vmovhps %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 fb 11 21 vmovsd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c4 e1 f9 7e e1 vmovq %xmm4,%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 f9 6e e1 vmovq %rcx,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 21 vmovq %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 fa 7e 21 vmovq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fb 2d cc vcvtsd2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fb 2d 09 vcvtsd2si \(%rcx\),%ecx
|
||||
[ ]*[a-f0-9]+: c5 fb 2c cc vcvttsd2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fb 2c 09 vcvttsd2si \(%rcx\),%ecx
|
||||
[ ]*[a-f0-9]+: c4 e1 fb 2d cc vcvtsd2si %xmm4,%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 fb 2d 09 vcvtsd2si \(%rcx\),%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 fb 2c cc vcvttsd2si %xmm4,%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si \(%rcx\),%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 db 2a e1 vcvtsi2sd %rcx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e1 db 2a 21 vcvtsi2sdq \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e1 da 2a e1 vcvtsi2ss %rcx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e1 da 2a 21 vcvtsi2ssq \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 d9 22 e1 64 vpinsrq \$0x64,%rcx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 d9 22 21 64 vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 f9 16 e1 64 vpextrq \$0x64,%xmm4,%rcx
|
||||
[ ]*[a-f0-9]+: c4 e3 f9 16 21 64 vpextrq \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 d9 12 21 vmovlpd \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d8 12 21 vmovlps \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 16 21 vmovhpd \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d8 16 21 vmovhps \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 64 vcmpsd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 64 vcmpsd \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0b f4 64 vroundsd \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0b 31 64 vroundsd \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 58 f4 vaddsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 58 31 vaddsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5a f4 vcvtsd2ss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5a 31 vcvtsd2ss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5e f4 vdivsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5e 31 vdivsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5f f4 vmaxsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5f 31 vmaxsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5d f4 vminsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5d 31 vminsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 59 f4 vmulsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 59 31 vmulsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 51 f4 vsqrtsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 51 31 vsqrtsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5c f4 vsubsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 5c 31 vsubsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 00 vcmpeqsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 00 vcmpeqsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 01 vcmpltsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 01 vcmpltsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 02 vcmplesd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 02 vcmplesd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 03 vcmpunordsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 03 vcmpunordsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 04 vcmpneqsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 04 vcmpneqsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 05 vcmpnltsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 05 vcmpnltsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 06 vcmpnlesd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 06 vcmpnlesd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 f4 07 vcmpordsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb c2 31 07 vcmpordsd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 58 f4 vaddss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 58 31 vaddss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5a f4 vcvtss2sd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5a 31 vcvtss2sd \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5e f4 vdivss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5e 31 vdivss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5f f4 vmaxss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5f 31 vmaxss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5d f4 vminss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5d 31 vminss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 59 f4 vmulss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 59 31 vmulss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 53 f4 vrcpss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 53 31 vrcpss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 52 f4 vrsqrtss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 52 31 vrsqrtss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 51 f4 vsqrtss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 51 31 vsqrtss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5c f4 vsubss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 5c 31 vsubss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 00 vcmpeqss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 00 vcmpeqss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 01 vcmpltss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 01 vcmpltss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 02 vcmpless %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 02 vcmpless \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 03 vcmpunordss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 03 vcmpunordss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 04 vcmpneqss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 04 vcmpneqss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 05 vcmpnltss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 05 vcmpnltss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 06 vcmpnless %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 06 vcmpnless \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 07 vcmpordss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 07 vcmpordss \(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 2f f4 vcomiss %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 2f 21 vcomiss \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 21 f4 vpmovsxbd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 21 21 vpmovsxbd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 24 f4 vpmovsxwq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 24 21 vpmovsxwq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 31 f4 vpmovzxbd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 31 21 vpmovzxbd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 34 f4 vpmovzxwq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 34 21 vpmovzxwq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 2e f4 vucomiss %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 2e 21 vucomiss \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 10 21 vmovss \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 11 21 vmovss %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 7e e1 vmovd %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 7e 21 vmovd %xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 6e e1 vmovd %ecx,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6e 21 vmovd \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 2d cc vcvtss2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fa 2d 09 vcvtss2si \(%rcx\),%ecx
|
||||
[ ]*[a-f0-9]+: c5 fa 2c cc vcvttss2si %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fa 2c 09 vcvttss2si \(%rcx\),%ecx
|
||||
[ ]*[a-f0-9]+: c4 e1 fa 2d cc vcvtss2si %xmm4,%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 fa 2d 09 vcvtss2si \(%rcx\),%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 fa 2c cc vcvttss2si %xmm4,%rcx
|
||||
[ ]*[a-f0-9]+: c4 e1 fa 2c 09 vcvttss2si \(%rcx\),%rcx
|
||||
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 79 16 e1 64 vpextrd \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 16 21 64 vpextrd \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 e1 64 vextractps \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 17 21 64 vextractps \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 db 2a e1 vcvtsi2sd %ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 db 2a 21 vcvtsi2sdl \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 da 2a e1 vcvtsi2ss %ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 da 2a 21 vcvtsi2ssl \(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ca c2 f4 64 vcmpss \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca c2 31 64 vcmpss \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 21 f4 64 vinsertps \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 21 31 64 vinsertps \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0a f4 64 vroundss \$0x64,%xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 49 0a 31 64 vroundss \$0x64,\(%rcx\),%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 22 f4 vpmovsxbq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 22 21 vpmovsxbq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 79 32 f4 vpmovzxbq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 79 32 21 vpmovzxbq \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 15 21 64 vpextrw \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c5 d9 c4 e1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 c4 21 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 c4 e1 64 vpinsrw \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 c4 21 64 vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 e1 64 vpextrb \$0x64,%xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c4 e3 79 14 21 64 vpextrb \$0x64,%xmm4,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 e1 64 vpinsrb \$0x64,%ecx,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 59 20 21 64 vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 f7 f4 vmaskmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 50 cc vmovmskpd %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f8 50 cc vmovmskps %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 f9 d7 cc vpmovmskb %xmm4,%ecx
|
||||
[ ]*[a-f0-9]+: c5 c8 12 f4 vmovhlps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 c8 16 f4 vmovlhps %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 cb 10 f4 vmovsd %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 ca 10 f4 vmovss %xmm4,%xmm6,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 d9 72 f4 64 vpslld \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 fc 64 vpslldq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 f4 64 vpsllq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 71 f4 64 vpsllw \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 72 e4 64 vpsrad \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 71 e4 64 vpsraw \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 72 d4 64 vpsrld \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 dc 64 vpsrldq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 73 d4 64 vpsrlq \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 d9 71 d4 64 vpsrlw \$0x64,%xmm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 c5 cc 64 vpextrw \$0x64,%xmm4,%ecx
|
||||
#pass
|
||||
|
|
@ -0,0 +1,683 @@
|
|||
# Check 64bit SSE to AVX instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
# Tests for op mem64
|
||||
ldmxcsr (%rcx)
|
||||
stmxcsr (%rcx)
|
||||
|
||||
# Tests for op xmm/mem128, xmm
|
||||
cvtdq2ps %xmm4,%xmm6
|
||||
cvtdq2ps (%rcx),%xmm4
|
||||
cvtpd2dq %xmm4,%xmm6
|
||||
cvtpd2dq (%rcx),%xmm4
|
||||
cvtpd2ps %xmm4,%xmm6
|
||||
cvtpd2ps (%rcx),%xmm4
|
||||
cvtps2dq %xmm4,%xmm6
|
||||
cvtps2dq (%rcx),%xmm4
|
||||
cvttpd2dq %xmm4,%xmm6
|
||||
cvttpd2dq (%rcx),%xmm4
|
||||
cvttps2dq %xmm4,%xmm6
|
||||
cvttps2dq (%rcx),%xmm4
|
||||
movapd %xmm4,%xmm6
|
||||
movapd (%rcx),%xmm4
|
||||
movaps %xmm4,%xmm6
|
||||
movaps (%rcx),%xmm4
|
||||
movdqa %xmm4,%xmm6
|
||||
movdqa (%rcx),%xmm4
|
||||
movdqu %xmm4,%xmm6
|
||||
movdqu (%rcx),%xmm4
|
||||
movshdup %xmm4,%xmm6
|
||||
movshdup (%rcx),%xmm4
|
||||
movsldup %xmm4,%xmm6
|
||||
movsldup (%rcx),%xmm4
|
||||
movupd %xmm4,%xmm6
|
||||
movupd (%rcx),%xmm4
|
||||
movups %xmm4,%xmm6
|
||||
movups (%rcx),%xmm4
|
||||
pabsb %xmm4,%xmm6
|
||||
pabsb (%rcx),%xmm4
|
||||
pabsw %xmm4,%xmm6
|
||||
pabsw (%rcx),%xmm4
|
||||
pabsd %xmm4,%xmm6
|
||||
pabsd (%rcx),%xmm4
|
||||
phminposuw %xmm4,%xmm6
|
||||
phminposuw (%rcx),%xmm4
|
||||
ptest %xmm4,%xmm6
|
||||
ptest (%rcx),%xmm4
|
||||
rcpps %xmm4,%xmm6
|
||||
rcpps (%rcx),%xmm4
|
||||
rsqrtps %xmm4,%xmm6
|
||||
rsqrtps (%rcx),%xmm4
|
||||
sqrtpd %xmm4,%xmm6
|
||||
sqrtpd (%rcx),%xmm4
|
||||
sqrtps %xmm4,%xmm6
|
||||
sqrtps (%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm, xmm/mem128
|
||||
movapd %xmm4,%xmm6
|
||||
movapd %xmm4,(%rcx)
|
||||
movaps %xmm4,%xmm6
|
||||
movaps %xmm4,(%rcx)
|
||||
movdqa %xmm4,%xmm6
|
||||
movdqa %xmm4,(%rcx)
|
||||
movdqu %xmm4,%xmm6
|
||||
movdqu %xmm4,(%rcx)
|
||||
movupd %xmm4,%xmm6
|
||||
movupd %xmm4,(%rcx)
|
||||
movups %xmm4,%xmm6
|
||||
movups %xmm4,(%rcx)
|
||||
|
||||
# Tests for op mem128, xmm
|
||||
lddqu (%rcx),%xmm4
|
||||
movntdqa (%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm, mem128
|
||||
movntdq %xmm4,(%rcx)
|
||||
movntpd %xmm4,(%rcx)
|
||||
movntps %xmm4,(%rcx)
|
||||
|
||||
# Tests for op xmm/mem128, xmm[, xmm]
|
||||
addpd %xmm4,%xmm6
|
||||
addpd (%rcx),%xmm6
|
||||
addps %xmm4,%xmm6
|
||||
addps (%rcx),%xmm6
|
||||
addsubpd %xmm4,%xmm6
|
||||
addsubpd (%rcx),%xmm6
|
||||
addsubps %xmm4,%xmm6
|
||||
addsubps (%rcx),%xmm6
|
||||
andnpd %xmm4,%xmm6
|
||||
andnpd (%rcx),%xmm6
|
||||
andnps %xmm4,%xmm6
|
||||
andnps (%rcx),%xmm6
|
||||
andpd %xmm4,%xmm6
|
||||
andpd (%rcx),%xmm6
|
||||
andps %xmm4,%xmm6
|
||||
andps (%rcx),%xmm6
|
||||
divpd %xmm4,%xmm6
|
||||
divpd (%rcx),%xmm6
|
||||
divps %xmm4,%xmm6
|
||||
divps (%rcx),%xmm6
|
||||
haddpd %xmm4,%xmm6
|
||||
haddpd (%rcx),%xmm6
|
||||
haddps %xmm4,%xmm6
|
||||
haddps (%rcx),%xmm6
|
||||
hsubpd %xmm4,%xmm6
|
||||
hsubpd (%rcx),%xmm6
|
||||
hsubps %xmm4,%xmm6
|
||||
hsubps (%rcx),%xmm6
|
||||
maxpd %xmm4,%xmm6
|
||||
maxpd (%rcx),%xmm6
|
||||
maxps %xmm4,%xmm6
|
||||
maxps (%rcx),%xmm6
|
||||
minpd %xmm4,%xmm6
|
||||
minpd (%rcx),%xmm6
|
||||
minps %xmm4,%xmm6
|
||||
minps (%rcx),%xmm6
|
||||
mulpd %xmm4,%xmm6
|
||||
mulpd (%rcx),%xmm6
|
||||
mulps %xmm4,%xmm6
|
||||
mulps (%rcx),%xmm6
|
||||
orpd %xmm4,%xmm6
|
||||
orpd (%rcx),%xmm6
|
||||
orps %xmm4,%xmm6
|
||||
orps (%rcx),%xmm6
|
||||
packsswb %xmm4,%xmm6
|
||||
packsswb (%rcx),%xmm6
|
||||
packssdw %xmm4,%xmm6
|
||||
packssdw (%rcx),%xmm6
|
||||
packuswb %xmm4,%xmm6
|
||||
packuswb (%rcx),%xmm6
|
||||
packusdw %xmm4,%xmm6
|
||||
packusdw (%rcx),%xmm6
|
||||
paddb %xmm4,%xmm6
|
||||
paddb (%rcx),%xmm6
|
||||
paddw %xmm4,%xmm6
|
||||
paddw (%rcx),%xmm6
|
||||
paddd %xmm4,%xmm6
|
||||
paddd (%rcx),%xmm6
|
||||
paddq %xmm4,%xmm6
|
||||
paddq (%rcx),%xmm6
|
||||
paddsb %xmm4,%xmm6
|
||||
paddsb (%rcx),%xmm6
|
||||
paddsw %xmm4,%xmm6
|
||||
paddsw (%rcx),%xmm6
|
||||
paddusb %xmm4,%xmm6
|
||||
paddusb (%rcx),%xmm6
|
||||
paddusw %xmm4,%xmm6
|
||||
paddusw (%rcx),%xmm6
|
||||
pand %xmm4,%xmm6
|
||||
pand (%rcx),%xmm6
|
||||
pandn %xmm4,%xmm6
|
||||
pandn (%rcx),%xmm6
|
||||
pavgb %xmm4,%xmm6
|
||||
pavgb (%rcx),%xmm6
|
||||
pavgw %xmm4,%xmm6
|
||||
pavgw (%rcx),%xmm6
|
||||
pcmpeqb %xmm4,%xmm6
|
||||
pcmpeqb (%rcx),%xmm6
|
||||
pcmpeqw %xmm4,%xmm6
|
||||
pcmpeqw (%rcx),%xmm6
|
||||
pcmpeqd %xmm4,%xmm6
|
||||
pcmpeqd (%rcx),%xmm6
|
||||
pcmpeqq %xmm4,%xmm6
|
||||
pcmpeqq (%rcx),%xmm6
|
||||
pcmpgtb %xmm4,%xmm6
|
||||
pcmpgtb (%rcx),%xmm6
|
||||
pcmpgtw %xmm4,%xmm6
|
||||
pcmpgtw (%rcx),%xmm6
|
||||
pcmpgtd %xmm4,%xmm6
|
||||
pcmpgtd (%rcx),%xmm6
|
||||
pcmpgtq %xmm4,%xmm6
|
||||
pcmpgtq (%rcx),%xmm6
|
||||
phaddw %xmm4,%xmm6
|
||||
phaddw (%rcx),%xmm6
|
||||
phaddd %xmm4,%xmm6
|
||||
phaddd (%rcx),%xmm6
|
||||
phaddsw %xmm4,%xmm6
|
||||
phaddsw (%rcx),%xmm6
|
||||
phsubw %xmm4,%xmm6
|
||||
phsubw (%rcx),%xmm6
|
||||
phsubd %xmm4,%xmm6
|
||||
phsubd (%rcx),%xmm6
|
||||
phsubsw %xmm4,%xmm6
|
||||
phsubsw (%rcx),%xmm6
|
||||
pmaddwd %xmm4,%xmm6
|
||||
pmaddwd (%rcx),%xmm6
|
||||
pmaddubsw %xmm4,%xmm6
|
||||
pmaddubsw (%rcx),%xmm6
|
||||
pmaxsb %xmm4,%xmm6
|
||||
pmaxsb (%rcx),%xmm6
|
||||
pmaxsw %xmm4,%xmm6
|
||||
pmaxsw (%rcx),%xmm6
|
||||
pmaxsd %xmm4,%xmm6
|
||||
pmaxsd (%rcx),%xmm6
|
||||
pmaxub %xmm4,%xmm6
|
||||
pmaxub (%rcx),%xmm6
|
||||
pmaxuw %xmm4,%xmm6
|
||||
pmaxuw (%rcx),%xmm6
|
||||
pmaxud %xmm4,%xmm6
|
||||
pmaxud (%rcx),%xmm6
|
||||
pminsb %xmm4,%xmm6
|
||||
pminsb (%rcx),%xmm6
|
||||
pminsw %xmm4,%xmm6
|
||||
pminsw (%rcx),%xmm6
|
||||
pminsd %xmm4,%xmm6
|
||||
pminsd (%rcx),%xmm6
|
||||
pminub %xmm4,%xmm6
|
||||
pminub (%rcx),%xmm6
|
||||
pminuw %xmm4,%xmm6
|
||||
pminuw (%rcx),%xmm6
|
||||
pminud %xmm4,%xmm6
|
||||
pminud (%rcx),%xmm6
|
||||
pmulhuw %xmm4,%xmm6
|
||||
pmulhuw (%rcx),%xmm6
|
||||
pmulhrsw %xmm4,%xmm6
|
||||
pmulhrsw (%rcx),%xmm6
|
||||
pmulhw %xmm4,%xmm6
|
||||
pmulhw (%rcx),%xmm6
|
||||
pmullw %xmm4,%xmm6
|
||||
pmullw (%rcx),%xmm6
|
||||
pmulld %xmm4,%xmm6
|
||||
pmulld (%rcx),%xmm6
|
||||
pmuludq %xmm4,%xmm6
|
||||
pmuludq (%rcx),%xmm6
|
||||
pmuldq %xmm4,%xmm6
|
||||
pmuldq (%rcx),%xmm6
|
||||
por %xmm4,%xmm6
|
||||
por (%rcx),%xmm6
|
||||
psadbw %xmm4,%xmm6
|
||||
psadbw (%rcx),%xmm6
|
||||
pshufb %xmm4,%xmm6
|
||||
pshufb (%rcx),%xmm6
|
||||
psignb %xmm4,%xmm6
|
||||
psignb (%rcx),%xmm6
|
||||
psignw %xmm4,%xmm6
|
||||
psignw (%rcx),%xmm6
|
||||
psignd %xmm4,%xmm6
|
||||
psignd (%rcx),%xmm6
|
||||
psllw %xmm4,%xmm6
|
||||
psllw (%rcx),%xmm6
|
||||
pslld %xmm4,%xmm6
|
||||
pslld (%rcx),%xmm6
|
||||
psllq %xmm4,%xmm6
|
||||
psllq (%rcx),%xmm6
|
||||
psraw %xmm4,%xmm6
|
||||
psraw (%rcx),%xmm6
|
||||
psrad %xmm4,%xmm6
|
||||
psrad (%rcx),%xmm6
|
||||
psrlw %xmm4,%xmm6
|
||||
psrlw (%rcx),%xmm6
|
||||
psrld %xmm4,%xmm6
|
||||
psrld (%rcx),%xmm6
|
||||
psrlq %xmm4,%xmm6
|
||||
psrlq (%rcx),%xmm6
|
||||
psubb %xmm4,%xmm6
|
||||
psubb (%rcx),%xmm6
|
||||
psubw %xmm4,%xmm6
|
||||
psubw (%rcx),%xmm6
|
||||
psubd %xmm4,%xmm6
|
||||
psubd (%rcx),%xmm6
|
||||
psubq %xmm4,%xmm6
|
||||
psubq (%rcx),%xmm6
|
||||
psubsb %xmm4,%xmm6
|
||||
psubsb (%rcx),%xmm6
|
||||
psubsw %xmm4,%xmm6
|
||||
psubsw (%rcx),%xmm6
|
||||
psubusb %xmm4,%xmm6
|
||||
psubusb (%rcx),%xmm6
|
||||
psubusw %xmm4,%xmm6
|
||||
psubusw (%rcx),%xmm6
|
||||
punpckhbw %xmm4,%xmm6
|
||||
punpckhbw (%rcx),%xmm6
|
||||
punpckhwd %xmm4,%xmm6
|
||||
punpckhwd (%rcx),%xmm6
|
||||
punpckhdq %xmm4,%xmm6
|
||||
punpckhdq (%rcx),%xmm6
|
||||
punpckhqdq %xmm4,%xmm6
|
||||
punpckhqdq (%rcx),%xmm6
|
||||
punpcklbw %xmm4,%xmm6
|
||||
punpcklbw (%rcx),%xmm6
|
||||
punpcklwd %xmm4,%xmm6
|
||||
punpcklwd (%rcx),%xmm6
|
||||
punpckldq %xmm4,%xmm6
|
||||
punpckldq (%rcx),%xmm6
|
||||
punpcklqdq %xmm4,%xmm6
|
||||
punpcklqdq (%rcx),%xmm6
|
||||
pxor %xmm4,%xmm6
|
||||
pxor (%rcx),%xmm6
|
||||
subpd %xmm4,%xmm6
|
||||
subpd (%rcx),%xmm6
|
||||
subps %xmm4,%xmm6
|
||||
subps (%rcx),%xmm6
|
||||
unpckhpd %xmm4,%xmm6
|
||||
unpckhpd (%rcx),%xmm6
|
||||
unpckhps %xmm4,%xmm6
|
||||
unpckhps (%rcx),%xmm6
|
||||
unpcklpd %xmm4,%xmm6
|
||||
unpcklpd (%rcx),%xmm6
|
||||
unpcklps %xmm4,%xmm6
|
||||
unpcklps (%rcx),%xmm6
|
||||
xorpd %xmm4,%xmm6
|
||||
xorpd (%rcx),%xmm6
|
||||
xorps %xmm4,%xmm6
|
||||
xorps (%rcx),%xmm6
|
||||
cmpeqpd %xmm4,%xmm6
|
||||
cmpeqpd (%rcx),%xmm6
|
||||
cmpeqps %xmm4,%xmm6
|
||||
cmpeqps (%rcx),%xmm6
|
||||
cmpltpd %xmm4,%xmm6
|
||||
cmpltpd (%rcx),%xmm6
|
||||
cmpltps %xmm4,%xmm6
|
||||
cmpltps (%rcx),%xmm6
|
||||
cmplepd %xmm4,%xmm6
|
||||
cmplepd (%rcx),%xmm6
|
||||
cmpleps %xmm4,%xmm6
|
||||
cmpleps (%rcx),%xmm6
|
||||
cmpunordpd %xmm4,%xmm6
|
||||
cmpunordpd (%rcx),%xmm6
|
||||
cmpunordps %xmm4,%xmm6
|
||||
cmpunordps (%rcx),%xmm6
|
||||
cmpneqpd %xmm4,%xmm6
|
||||
cmpneqpd (%rcx),%xmm6
|
||||
cmpneqps %xmm4,%xmm6
|
||||
cmpneqps (%rcx),%xmm6
|
||||
cmpnltpd %xmm4,%xmm6
|
||||
cmpnltpd (%rcx),%xmm6
|
||||
cmpnltps %xmm4,%xmm6
|
||||
cmpnltps (%rcx),%xmm6
|
||||
cmpnlepd %xmm4,%xmm6
|
||||
cmpnlepd (%rcx),%xmm6
|
||||
cmpnleps %xmm4,%xmm6
|
||||
cmpnleps (%rcx),%xmm6
|
||||
cmpordpd %xmm4,%xmm6
|
||||
cmpordpd (%rcx),%xmm6
|
||||
cmpordps %xmm4,%xmm6
|
||||
cmpordps (%rcx),%xmm6
|
||||
|
||||
# Tests for op imm8, xmm/mem128, xmm
|
||||
pcmpestri $100,%xmm4,%xmm6
|
||||
pcmpestri $100,(%rcx),%xmm6
|
||||
pcmpestrm $100,%xmm4,%xmm6
|
||||
pcmpestrm $100,(%rcx),%xmm6
|
||||
pcmpistri $100,%xmm4,%xmm6
|
||||
pcmpistri $100,(%rcx),%xmm6
|
||||
pcmpistrm $100,%xmm4,%xmm6
|
||||
pcmpistrm $100,(%rcx),%xmm6
|
||||
pshufd $100,%xmm4,%xmm6
|
||||
pshufd $100,(%rcx),%xmm6
|
||||
pshufhw $100,%xmm4,%xmm6
|
||||
pshufhw $100,(%rcx),%xmm6
|
||||
pshuflw $100,%xmm4,%xmm6
|
||||
pshuflw $100,(%rcx),%xmm6
|
||||
roundpd $100,%xmm4,%xmm6
|
||||
roundpd $100,(%rcx),%xmm6
|
||||
roundps $100,%xmm4,%xmm6
|
||||
roundps $100,(%rcx),%xmm6
|
||||
|
||||
# Tests for op imm8, xmm/mem128, xmm[, xmm]
|
||||
blendpd $100,%xmm4,%xmm6
|
||||
blendpd $100,(%rcx),%xmm6
|
||||
blendps $100,%xmm4,%xmm6
|
||||
blendps $100,(%rcx),%xmm6
|
||||
cmppd $100,%xmm4,%xmm6
|
||||
cmppd $100,(%rcx),%xmm6
|
||||
cmpps $100,%xmm4,%xmm6
|
||||
cmpps $100,(%rcx),%xmm6
|
||||
dppd $100,%xmm4,%xmm6
|
||||
dppd $100,(%rcx),%xmm6
|
||||
dpps $100,%xmm4,%xmm6
|
||||
dpps $100,(%rcx),%xmm6
|
||||
mpsadbw $100,%xmm4,%xmm6
|
||||
mpsadbw $100,(%rcx),%xmm6
|
||||
palignr $100,%xmm4,%xmm6
|
||||
palignr $100,(%rcx),%xmm6
|
||||
pblendw $100,%xmm4,%xmm6
|
||||
pblendw $100,(%rcx),%xmm6
|
||||
shufpd $100,%xmm4,%xmm6
|
||||
shufpd $100,(%rcx),%xmm6
|
||||
shufps $100,%xmm4,%xmm6
|
||||
shufps $100,(%rcx),%xmm6
|
||||
|
||||
# Tests for op xmm0, xmm/mem128, xmm[, xmm]
|
||||
blendvpd %xmm0,%xmm4,%xmm6
|
||||
blendvpd %xmm0,(%rcx),%xmm6
|
||||
blendvpd %xmm4,%xmm6
|
||||
blendvpd (%rcx),%xmm6
|
||||
blendvps %xmm0,%xmm4,%xmm6
|
||||
blendvps %xmm0,(%rcx),%xmm6
|
||||
blendvps %xmm4,%xmm6
|
||||
blendvps (%rcx),%xmm6
|
||||
pblendvb %xmm0,%xmm4,%xmm6
|
||||
pblendvb %xmm0,(%rcx),%xmm6
|
||||
pblendvb %xmm4,%xmm6
|
||||
pblendvb (%rcx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem64, xmm
|
||||
comisd %xmm4,%xmm6
|
||||
comisd (%rcx),%xmm4
|
||||
cvtdq2pd %xmm4,%xmm6
|
||||
cvtdq2pd (%rcx),%xmm4
|
||||
cvtps2pd %xmm4,%xmm6
|
||||
cvtps2pd (%rcx),%xmm4
|
||||
movddup %xmm4,%xmm6
|
||||
movddup (%rcx),%xmm4
|
||||
pmovsxbw %xmm4,%xmm6
|
||||
pmovsxbw (%rcx),%xmm4
|
||||
pmovsxwd %xmm4,%xmm6
|
||||
pmovsxwd (%rcx),%xmm4
|
||||
pmovsxdq %xmm4,%xmm6
|
||||
pmovsxdq (%rcx),%xmm4
|
||||
pmovzxbw %xmm4,%xmm6
|
||||
pmovzxbw (%rcx),%xmm4
|
||||
pmovzxwd %xmm4,%xmm6
|
||||
pmovzxwd (%rcx),%xmm4
|
||||
pmovzxdq %xmm4,%xmm6
|
||||
pmovzxdq (%rcx),%xmm4
|
||||
ucomisd %xmm4,%xmm6
|
||||
ucomisd (%rcx),%xmm4
|
||||
|
||||
# Tests for op mem64, xmm
|
||||
movsd (%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm, mem64
|
||||
movlpd %xmm4,(%rcx)
|
||||
movlps %xmm4,(%rcx)
|
||||
movhpd %xmm4,(%rcx)
|
||||
movhps %xmm4,(%rcx)
|
||||
movsd %xmm4,(%rcx)
|
||||
|
||||
# Tests for op xmm, regq/mem64
|
||||
# Tests for op regq/mem64, xmm
|
||||
movq %xmm4,%rcx
|
||||
movq %rcx,%xmm4
|
||||
movq %xmm4,(%rcx)
|
||||
movq (%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm/mem64, regl
|
||||
cvtsd2si %xmm4,%ecx
|
||||
cvtsd2si (%rcx),%ecx
|
||||
cvttsd2si %xmm4,%ecx
|
||||
cvttsd2si (%rcx),%ecx
|
||||
|
||||
# Tests for op xmm/mem64, regq
|
||||
cvtsd2si %xmm4,%rcx
|
||||
cvtsd2si (%rcx),%rcx
|
||||
cvttsd2si %xmm4,%rcx
|
||||
cvttsd2si (%rcx),%rcx
|
||||
|
||||
# Tests for op regq/mem64, xmm[, xmm]
|
||||
cvtsi2sdq %rcx,%xmm4
|
||||
cvtsi2sdq (%rcx),%xmm4
|
||||
cvtsi2ssq %rcx,%xmm4
|
||||
cvtsi2ssq (%rcx),%xmm4
|
||||
|
||||
# Tests for op imm8, regq/mem64, xmm[, xmm]
|
||||
pinsrq $100,%rcx,%xmm4
|
||||
pinsrq $100,(%rcx),%xmm4
|
||||
|
||||
# Testsf for op imm8, xmm, regq/mem64
|
||||
pextrq $100,%xmm4,%rcx
|
||||
pextrq $100,%xmm4,(%rcx)
|
||||
|
||||
# Tests for op mem64, xmm[, xmm]
|
||||
movlpd (%rcx),%xmm4
|
||||
movlps (%rcx),%xmm4
|
||||
movhpd (%rcx),%xmm4
|
||||
movhps (%rcx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm/mem64, xmm[, xmm]
|
||||
cmpsd $100,%xmm4,%xmm6
|
||||
cmpsd $100,(%rcx),%xmm6
|
||||
roundsd $100,%xmm4,%xmm6
|
||||
roundsd $100,(%rcx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem64, xmm[, xmm]
|
||||
addsd %xmm4,%xmm6
|
||||
addsd (%rcx),%xmm6
|
||||
cvtsd2ss %xmm4,%xmm6
|
||||
cvtsd2ss (%rcx),%xmm6
|
||||
divsd %xmm4,%xmm6
|
||||
divsd (%rcx),%xmm6
|
||||
maxsd %xmm4,%xmm6
|
||||
maxsd (%rcx),%xmm6
|
||||
minsd %xmm4,%xmm6
|
||||
minsd (%rcx),%xmm6
|
||||
mulsd %xmm4,%xmm6
|
||||
mulsd (%rcx),%xmm6
|
||||
sqrtsd %xmm4,%xmm6
|
||||
sqrtsd (%rcx),%xmm6
|
||||
subsd %xmm4,%xmm6
|
||||
subsd (%rcx),%xmm6
|
||||
cmpeqsd %xmm4,%xmm6
|
||||
cmpeqsd (%rcx),%xmm6
|
||||
cmpltsd %xmm4,%xmm6
|
||||
cmpltsd (%rcx),%xmm6
|
||||
cmplesd %xmm4,%xmm6
|
||||
cmplesd (%rcx),%xmm6
|
||||
cmpunordsd %xmm4,%xmm6
|
||||
cmpunordsd (%rcx),%xmm6
|
||||
cmpneqsd %xmm4,%xmm6
|
||||
cmpneqsd (%rcx),%xmm6
|
||||
cmpnltsd %xmm4,%xmm6
|
||||
cmpnltsd (%rcx),%xmm6
|
||||
cmpnlesd %xmm4,%xmm6
|
||||
cmpnlesd (%rcx),%xmm6
|
||||
cmpordsd %xmm4,%xmm6
|
||||
cmpordsd (%rcx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem32, xmm[, xmm]
|
||||
addss %xmm4,%xmm6
|
||||
addss (%rcx),%xmm6
|
||||
cvtss2sd %xmm4,%xmm6
|
||||
cvtss2sd (%rcx),%xmm6
|
||||
divss %xmm4,%xmm6
|
||||
divss (%rcx),%xmm6
|
||||
maxss %xmm4,%xmm6
|
||||
maxss (%rcx),%xmm6
|
||||
minss %xmm4,%xmm6
|
||||
minss (%rcx),%xmm6
|
||||
mulss %xmm4,%xmm6
|
||||
mulss (%rcx),%xmm6
|
||||
rcpss %xmm4,%xmm6
|
||||
rcpss (%rcx),%xmm6
|
||||
rsqrtss %xmm4,%xmm6
|
||||
rsqrtss (%rcx),%xmm6
|
||||
sqrtss %xmm4,%xmm6
|
||||
sqrtss (%rcx),%xmm6
|
||||
subss %xmm4,%xmm6
|
||||
subss (%rcx),%xmm6
|
||||
cmpeqss %xmm4,%xmm6
|
||||
cmpeqss (%rcx),%xmm6
|
||||
cmpltss %xmm4,%xmm6
|
||||
cmpltss (%rcx),%xmm6
|
||||
cmpless %xmm4,%xmm6
|
||||
cmpless (%rcx),%xmm6
|
||||
cmpunordss %xmm4,%xmm6
|
||||
cmpunordss (%rcx),%xmm6
|
||||
cmpneqss %xmm4,%xmm6
|
||||
cmpneqss (%rcx),%xmm6
|
||||
cmpnltss %xmm4,%xmm6
|
||||
cmpnltss (%rcx),%xmm6
|
||||
cmpnless %xmm4,%xmm6
|
||||
cmpnless (%rcx),%xmm6
|
||||
cmpordss %xmm4,%xmm6
|
||||
cmpordss (%rcx),%xmm6
|
||||
|
||||
# Tests for op xmm/mem32, xmm
|
||||
comiss %xmm4,%xmm6
|
||||
comiss (%rcx),%xmm4
|
||||
pmovsxbd %xmm4,%xmm6
|
||||
pmovsxbd (%rcx),%xmm4
|
||||
pmovsxwq %xmm4,%xmm6
|
||||
pmovsxwq (%rcx),%xmm4
|
||||
pmovzxbd %xmm4,%xmm6
|
||||
pmovzxbd (%rcx),%xmm4
|
||||
pmovzxwq %xmm4,%xmm6
|
||||
pmovzxwq (%rcx),%xmm4
|
||||
ucomiss %xmm4,%xmm6
|
||||
ucomiss (%rcx),%xmm4
|
||||
|
||||
# Tests for op mem32, xmm
|
||||
movss (%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm, mem32
|
||||
movss %xmm4,(%rcx)
|
||||
|
||||
# Tests for op xmm, regl/mem32
|
||||
# Tests for op regl/mem32, xmm
|
||||
movd %xmm4,%ecx
|
||||
movd %xmm4,(%rcx)
|
||||
movd %ecx,%xmm4
|
||||
movd (%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm/mem32, regl
|
||||
cvtss2si %xmm4,%ecx
|
||||
cvtss2si (%rcx),%ecx
|
||||
cvttss2si %xmm4,%ecx
|
||||
cvttss2si (%rcx),%ecx
|
||||
|
||||
# Tests for op xmm/mem32, regq
|
||||
cvtss2si %xmm4,%rcx
|
||||
cvtss2si (%rcx),%rcx
|
||||
cvttss2si %xmm4,%rcx
|
||||
cvttss2si (%rcx),%rcx
|
||||
|
||||
# Tests for op xmm, regq
|
||||
movmskpd %xmm4,%rcx
|
||||
movmskps %xmm4,%rcx
|
||||
pmovmskb %xmm4,%rcx
|
||||
|
||||
# Tests for op imm8, xmm, regq/mem32
|
||||
extractps $100,%xmm4,%rcx
|
||||
extractps $100,%xmm4,(%rcx)
|
||||
# Tests for op imm8, xmm, regl/mem32
|
||||
pextrd $100,%xmm4,%ecx
|
||||
pextrd $100,%xmm4,(%rcx)
|
||||
extractps $100,%xmm4,%ecx
|
||||
extractps $100,%xmm4,(%rcx)
|
||||
|
||||
# Tests for op regl/mem32, xmm[, xmm]
|
||||
cvtsi2sd %ecx,%xmm4
|
||||
cvtsi2sd (%rcx),%xmm4
|
||||
cvtsi2ss %ecx,%xmm4
|
||||
cvtsi2ss (%rcx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm/mem32, xmm[, xmm]
|
||||
cmpss $100,%xmm4,%xmm6
|
||||
cmpss $100,(%rcx),%xmm6
|
||||
insertps $100,%xmm4,%xmm6
|
||||
insertps $100,(%rcx),%xmm6
|
||||
roundss $100,%xmm4,%xmm6
|
||||
roundss $100,(%rcx),%xmm6
|
||||
|
||||
# Tests for op xmm/m16, xmm
|
||||
pmovsxbq %xmm4,%xmm6
|
||||
pmovsxbq (%rcx),%xmm4
|
||||
pmovzxbq %xmm4,%xmm6
|
||||
pmovzxbq (%rcx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regl/mem16
|
||||
pextrw $100,%xmm4,%ecx
|
||||
pextrw $100,%xmm4,(%rcx)
|
||||
|
||||
# Tests for op imm8, xmm, regq/mem16
|
||||
pextrw $100,%xmm4,%rcx
|
||||
pextrw $100,%xmm4,(%rcx)
|
||||
|
||||
# Tests for op imm8, regl/mem16, xmm[, xmm]
|
||||
pinsrw $100,%ecx,%xmm4
|
||||
pinsrw $100,(%rcx),%xmm4
|
||||
|
||||
|
||||
pinsrw $100,%rcx,%xmm4
|
||||
pinsrw $100,(%rcx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regl/mem8
|
||||
pextrb $100,%xmm4,%ecx
|
||||
pextrb $100,%xmm4,(%rcx)
|
||||
|
||||
# Tests for op imm8, regl/mem8, xmm[, xmm]
|
||||
pinsrb $100,%ecx,%xmm4
|
||||
pinsrb $100,(%rcx),%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regq
|
||||
pextrw $100,%xmm4,%rcx
|
||||
# Tests for op imm8, xmm, regq/mem8
|
||||
pextrb $100,%xmm4,%rcx
|
||||
pextrb $100,%xmm4,(%rcx)
|
||||
|
||||
# Tests for op imm8, regl/mem8, xmm[, xmm]
|
||||
pinsrb $100,%ecx,%xmm4
|
||||
pinsrb $100,(%rcx),%xmm4
|
||||
|
||||
# Tests for op xmm, xmm
|
||||
maskmovdqu %xmm4,%xmm6
|
||||
movq %xmm4,%xmm6
|
||||
|
||||
# Tests for op xmm, regl
|
||||
movmskpd %xmm4,%ecx
|
||||
movmskps %xmm4,%ecx
|
||||
pmovmskb %xmm4,%ecx
|
||||
# Tests for op xmm, xmm[, xmm]
|
||||
movhlps %xmm4,%xmm6
|
||||
movlhps %xmm4,%xmm6
|
||||
movsd %xmm4,%xmm6
|
||||
movss %xmm4,%xmm6
|
||||
|
||||
# Tests for op imm8, xmm[, xmm]
|
||||
pslld $100,%xmm4
|
||||
pslldq $100,%xmm4
|
||||
psllq $100,%xmm4
|
||||
psllw $100,%xmm4
|
||||
psrad $100,%xmm4
|
||||
psraw $100,%xmm4
|
||||
psrld $100,%xmm4
|
||||
psrldq $100,%xmm4
|
||||
psrlq $100,%xmm4
|
||||
psrlw $100,%xmm4
|
||||
|
||||
# Tests for op imm8, xmm, regl
|
||||
pextrw $100,%xmm4,%ecx
|
||||
|
||||
|
|
@ -1,3 +1,8 @@
|
|||
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386.h (MAX_OPERANDS): Set to 5.
|
||||
(MAX_MNEM_SIZE): Changed to 20.
|
||||
|
||||
2008-03-09 Paul Brook <paul@codesourcery.com>
|
||||
|
||||
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@
|
|||
#define REX_B 1
|
||||
|
||||
/* max operands per insn */
|
||||
#define MAX_OPERANDS 4
|
||||
#define MAX_OPERANDS 5
|
||||
|
||||
/* max immediates per insn (lcall, ljmp, insertq, extrq) */
|
||||
#define MAX_IMMEDIATE_OPERANDS 2
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
#define MAX_MEMORY_OPERANDS 2
|
||||
|
||||
/* max size of insn mnemonics. */
|
||||
#define MAX_MNEM_SIZE 16
|
||||
#define MAX_MNEM_SIZE 20
|
||||
|
||||
/* max size of register name in insn mnemonics. */
|
||||
#define MAX_REG_NAME_SIZE 8
|
||||
|
|
|
|||
|
|
@ -1,3 +1,152 @@
|
|||
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (OP_E_register): New.
|
||||
(OP_E_memory): Likewise.
|
||||
(OP_VEX): Likewise.
|
||||
(OP_EX_Vex): Likewise.
|
||||
(OP_EX_VexW): Likewise.
|
||||
(OP_XMM_Vex): Likewise.
|
||||
(OP_XMM_VexW): Likewise.
|
||||
(OP_REG_VexI4): Likewise.
|
||||
(PCLMUL_Fixup): Likewise.
|
||||
(VEXI4_Fixup): Likewise.
|
||||
(VZERO_Fixup): Likewise.
|
||||
(VCMP_Fixup): Likewise.
|
||||
(VPERMIL2_Fixup): Likewise.
|
||||
(rex_original): Likewise.
|
||||
(rex_ignored): Likewise.
|
||||
(Mxmm): Likewise.
|
||||
(XMM): Likewise.
|
||||
(EXxmm): Likewise.
|
||||
(EXxmmq): Likewise.
|
||||
(EXymmq): Likewise.
|
||||
(Vex): Likewise.
|
||||
(Vex128): Likewise.
|
||||
(Vex256): Likewise.
|
||||
(VexI4): Likewise.
|
||||
(EXdVex): Likewise.
|
||||
(EXqVex): Likewise.
|
||||
(EXVexW): Likewise.
|
||||
(EXdVexW): Likewise.
|
||||
(EXqVexW): Likewise.
|
||||
(XMVex): Likewise.
|
||||
(XMVexW): Likewise.
|
||||
(XMVexI4): Likewise.
|
||||
(PCLMUL): Likewise.
|
||||
(VZERO): Likewise.
|
||||
(VCMP): Likewise.
|
||||
(VPERMIL2): Likewise.
|
||||
(xmm_mode): Likewise.
|
||||
(xmmq_mode): Likewise.
|
||||
(ymmq_mode): Likewise.
|
||||
(vex_mode): Likewise.
|
||||
(vex128_mode): Likewise.
|
||||
(vex256_mode): Likewise.
|
||||
(USE_VEX_C4_TABLE): Likewise.
|
||||
(USE_VEX_C5_TABLE): Likewise.
|
||||
(USE_VEX_LEN_TABLE): Likewise.
|
||||
(VEX_C4_TABLE): Likewise.
|
||||
(VEX_C5_TABLE): Likewise.
|
||||
(VEX_LEN_TABLE): Likewise.
|
||||
(REG_VEX_XX): Likewise.
|
||||
(MOD_VEX_XXX): Likewise.
|
||||
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
|
||||
(PREFIX_0F3A44): Likewise.
|
||||
(PREFIX_0F3ADF): Likewise.
|
||||
(PREFIX_VEX_XXX): Likewise.
|
||||
(VEX_OF): Likewise.
|
||||
(VEX_OF38): Likewise.
|
||||
(VEX_OF3A): Likewise.
|
||||
(VEX_LEN_XXX): Likewise.
|
||||
(vex): Likewise.
|
||||
(need_vex): Likewise.
|
||||
(need_vex_reg): Likewise.
|
||||
(vex_i4_done): Likewise.
|
||||
(vex_table): Likewise.
|
||||
(vex_len_table): Likewise.
|
||||
(OP_REG_VexI4): Likewise.
|
||||
(vex_cmp_op): Likewise.
|
||||
(pclmul_op): Likewise.
|
||||
(vpermil2_op): Likewise.
|
||||
(m_mode): Updated.
|
||||
(es_reg): Likewise.
|
||||
(PREFIX_0F38F0): Likewise.
|
||||
(PREFIX_0F3A60): Likewise.
|
||||
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
|
||||
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
|
||||
and PREFIX_VEX_XXX entries.
|
||||
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
|
||||
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
|
||||
PREFIX_0F3ADF.
|
||||
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
|
||||
Add MOD_VEX_XXX entries.
|
||||
(ckprefix): Initialize rex_original and rex_ignored. Store the
|
||||
REX byte in rex_original.
|
||||
(get_valid_dis386): Handle the implicit prefix in VEX prefix
|
||||
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
|
||||
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
|
||||
calling get_valid_dis386. Use rex_original and rex_ignored when
|
||||
printing out REX.
|
||||
(putop): Handle "XY".
|
||||
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
|
||||
ymmq_mode.
|
||||
(OP_E_extended): Updated to use OP_E_register and
|
||||
OP_E_memory.
|
||||
(OP_XMM): Handle VEX.
|
||||
(OP_EX): Likewise.
|
||||
(XMM_Fixup): Likewise.
|
||||
(CMP_Fixup): Use ARRAY_SIZE.
|
||||
|
||||
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
|
||||
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
|
||||
(operand_type_init): Add OPERAND_TYPE_REGYMM and
|
||||
OPERAND_TYPE_VEX_IMM4.
|
||||
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
|
||||
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
|
||||
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
|
||||
VexImmExt and SSE2AVX.
|
||||
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
|
||||
|
||||
* i386-opc.h (CpuAVX): New.
|
||||
(CpuAES): Likewise.
|
||||
(CpuCLMUL): Likewise.
|
||||
(CpuFMA): Likewise.
|
||||
(Vex): Likewise.
|
||||
(Vex256): Likewise.
|
||||
(VexNDS): Likewise.
|
||||
(VexNDD): Likewise.
|
||||
(VexW0): Likewise.
|
||||
(VexW1): Likewise.
|
||||
(Vex0F): Likewise.
|
||||
(Vex0F38): Likewise.
|
||||
(Vex0F3A): Likewise.
|
||||
(Vex3Sources): Likewise.
|
||||
(VexImmExt): Likewise.
|
||||
(SSE2AVX): Likewise.
|
||||
(RegYMM): Likewise.
|
||||
(Ymmword): Likewise.
|
||||
(Vex_Imm4): Likewise.
|
||||
(Implicit1stXmm0): Likewise.
|
||||
(CpuXsave): Updated.
|
||||
(CpuLM): Likewise.
|
||||
(ByteOkIntel): Likewise.
|
||||
(OldGcc): Likewise.
|
||||
(Control): Likewise.
|
||||
(Unspecified): Likewise.
|
||||
(OTMax): Likewise.
|
||||
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
|
||||
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
|
||||
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
|
||||
vex3sources, veximmext and sse2avx.
|
||||
(i386_operand_type): Add regymm, ymmword and vex_imm4.
|
||||
|
||||
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
|
||||
|
||||
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
|
||||
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
|
||||
|
||||
From Robin Getz <robin.getz@analog.com>
|
||||
|
|
|
|||
5426
opcodes/i386-dis.c
5426
opcodes/i386-dis.c
File diff suppressed because it is too large
Load Diff
|
|
@ -102,6 +102,12 @@ static initializer cpu_flag_init [] =
|
|||
"CpuSMX" },
|
||||
{ "CPU_XSAVE_FLAGS",
|
||||
"CpuXsave" },
|
||||
{ "CPU_AES_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
|
||||
{ "CPU_CLMUL_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuCLMUL" },
|
||||
{ "CPU_FMA_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
|
||||
{ "CPU_3DNOW_FLAGS",
|
||||
"CpuMMX|Cpu3dnow" },
|
||||
{ "CPU_3DNOWA_FLAGS",
|
||||
|
|
@ -116,6 +122,8 @@ static initializer cpu_flag_init [] =
|
|||
"CpuABM" },
|
||||
{ "CPU_SSE5_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5"},
|
||||
{ "CPU_AVX_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init [] =
|
||||
|
|
@ -182,6 +190,8 @@ static initializer operand_type_init [] =
|
|||
"RegMMX" },
|
||||
{ "OPERAND_TYPE_REGXMM",
|
||||
"RegXMM" },
|
||||
{ "OPERAND_TYPE_REGYMM",
|
||||
"RegYMM" },
|
||||
{ "OPERAND_TYPE_ESSEG",
|
||||
"EsSeg" },
|
||||
{ "OPERAND_TYPE_ACC32",
|
||||
|
|
@ -210,6 +220,8 @@ static initializer operand_type_init [] =
|
|||
"Imm32|Imm32S|Imm64|Disp32" },
|
||||
{ "OPERAND_TYPE_IMM32_32S_64_DISP32_64",
|
||||
"Imm32|Imm32S|Imm64|Disp32|Disp64" },
|
||||
{ "OPERAND_TYPE_VEX_IMM4",
|
||||
"VEX_Imm4" },
|
||||
};
|
||||
|
||||
typedef struct bitfield
|
||||
|
|
@ -239,6 +251,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuSSSE3),
|
||||
BITFIELD (CpuSSE4_1),
|
||||
BITFIELD (CpuSSE4_2),
|
||||
BITFIELD (CpuAVX),
|
||||
BITFIELD (CpuSSE4a),
|
||||
BITFIELD (CpuSSE5),
|
||||
BITFIELD (Cpu3dnow),
|
||||
|
|
@ -248,8 +261,11 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuVMX),
|
||||
BITFIELD (CpuSMX),
|
||||
BITFIELD (CpuABM),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (CpuXsave),
|
||||
BITFIELD (CpuAES),
|
||||
BITFIELD (CpuCLMUL),
|
||||
BITFIELD (CpuFMA),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
#ifdef CpuUnused
|
||||
|
|
@ -285,6 +301,7 @@ static bitfield opcode_modifiers[] =
|
|||
BITFIELD (IsString),
|
||||
BITFIELD (RegKludge),
|
||||
BITFIELD (FirstXmm0),
|
||||
BITFIELD (Implicit1stXmm0),
|
||||
BITFIELD (ByteOkIntel),
|
||||
BITFIELD (ToDword),
|
||||
BITFIELD (ToQword),
|
||||
|
|
@ -297,6 +314,18 @@ static bitfield opcode_modifiers[] =
|
|||
BITFIELD (Drex),
|
||||
BITFIELD (Drexv),
|
||||
BITFIELD (Drexc),
|
||||
BITFIELD (Vex),
|
||||
BITFIELD (Vex256),
|
||||
BITFIELD (VexNDD),
|
||||
BITFIELD (VexNDS),
|
||||
BITFIELD (VexW0),
|
||||
BITFIELD (VexW1),
|
||||
BITFIELD (Vex0F),
|
||||
BITFIELD (Vex0F38),
|
||||
BITFIELD (Vex0F3A),
|
||||
BITFIELD (Vex3Sources),
|
||||
BITFIELD (VexImmExt),
|
||||
BITFIELD (SSE2AVX),
|
||||
BITFIELD (OldGcc),
|
||||
BITFIELD (ATTMnemonic),
|
||||
BITFIELD (ATTSyntax),
|
||||
|
|
@ -312,6 +341,7 @@ static bitfield operand_types[] =
|
|||
BITFIELD (FloatReg),
|
||||
BITFIELD (RegMMX),
|
||||
BITFIELD (RegXMM),
|
||||
BITFIELD (RegYMM),
|
||||
BITFIELD (Imm8),
|
||||
BITFIELD (Imm8S),
|
||||
BITFIELD (Imm16),
|
||||
|
|
@ -345,8 +375,10 @@ static bitfield operand_types[] =
|
|||
BITFIELD (Qword),
|
||||
BITFIELD (Tbyte),
|
||||
BITFIELD (Xmmword),
|
||||
BITFIELD (Ymmword),
|
||||
BITFIELD (Unspecified),
|
||||
BITFIELD (Anysize),
|
||||
BITFIELD (Vex_Imm4),
|
||||
#ifdef OTUnused
|
||||
BITFIELD (OTUnused),
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,378 +20,404 @@
|
|||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE5_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGYMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16_INOUTPORTREG \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_VEX_IMM4 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0 } }
|
||||
|
|
|
|||
|
|
@ -80,10 +80,18 @@
|
|||
#define CpuSSE4_2 (CpuSSE4_1 + 1)
|
||||
/* SSE5 support required */
|
||||
#define CpuSSE5 (CpuSSE4_2 + 1)
|
||||
/* AVX support required */
|
||||
#define CpuAVX (CpuSSE5 + 1)
|
||||
/* Xsave/xrstor New Instuctions support required */
|
||||
#define CpuXsave (CpuSSE5 + 1)
|
||||
#define CpuXsave (CpuAVX + 1)
|
||||
/* AES support required */
|
||||
#define CpuAES (CpuXsave + 1)
|
||||
/* CLMUL support required */
|
||||
#define CpuCLMUL (CpuAES + 1)
|
||||
/* FMA support required */
|
||||
#define CpuFMA (CpuCLMUL + 1)
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
#define CpuLM (CpuXsave + 1)
|
||||
#define CpuLM (CpuFMA + 1)
|
||||
/* 64bit support required */
|
||||
#define Cpu64 (CpuLM + 1)
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -131,7 +139,11 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpusse4_1:1;
|
||||
unsigned int cpusse4_2:1;
|
||||
unsigned int cpusse5:1;
|
||||
unsigned int cpuavx:1;
|
||||
unsigned int cpuxsave:1;
|
||||
unsigned int cpuaes:1;
|
||||
unsigned int cpuclmul:1;
|
||||
unsigned int cpufma:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
|
|
@ -198,8 +210,10 @@ typedef union i386_cpu_flags
|
|||
#define RegKludge (IsString + 1)
|
||||
/* The first operand must be xmm0 */
|
||||
#define FirstXmm0 (RegKludge + 1)
|
||||
/* An implicit xmm0 as the first operand */
|
||||
#define Implicit1stXmm0 (FirstXmm0 + 1)
|
||||
/* BYTE is OK in Intel syntax. */
|
||||
#define ByteOkIntel (FirstXmm0 + 1)
|
||||
#define ByteOkIntel (Implicit1stXmm0 + 1)
|
||||
/* Convert to DWORD */
|
||||
#define ToDword (ByteOkIntel + 1)
|
||||
/* Convert to QWORD */
|
||||
|
|
@ -221,8 +235,34 @@ typedef union i386_cpu_flags
|
|||
#define Drexv (Drex + 1)
|
||||
/* special DREX for comparisons */
|
||||
#define Drexc (Drexv + 1)
|
||||
/* insn has VEX prefix. */
|
||||
#define Vex (Drexc + 1)
|
||||
/* insn has 256bit VEX prefix. */
|
||||
#define Vex256 (Vex + 1)
|
||||
/* insn has VEX NDS. Register-only source is encoded in Vex
|
||||
prefix. */
|
||||
#define VexNDS (Vex256 + 1)
|
||||
/* insn has VEX NDD. Register destination is encoded in Vex
|
||||
prefix. */
|
||||
#define VexNDD (VexNDS + 1)
|
||||
/* insn has VEX W0. */
|
||||
#define VexW0 (VexNDD + 1)
|
||||
/* insn has VEX W1. */
|
||||
#define VexW1 (VexW0 + 1)
|
||||
/* insn has VEX 0x0F opcode prefix. */
|
||||
#define Vex0F (VexW1 + 1)
|
||||
/* insn has VEX 0x0F38 opcode prefix. */
|
||||
#define Vex0F38 (Vex0F + 1)
|
||||
/* insn has VEX 0x0F3A opcode prefix. */
|
||||
#define Vex0F3A (Vex0F38 + 1)
|
||||
/* insn has VEX prefix with 3 soures. */
|
||||
#define Vex3Sources (Vex0F3A + 1)
|
||||
/* instruction has VEX 8 bit imm */
|
||||
#define VexImmExt (Vex3Sources + 1)
|
||||
/* SSE to AVX support required */
|
||||
#define SSE2AVX (VexImmExt + 1)
|
||||
/* Compatible with old (<= 2.8.1) versions of gcc */
|
||||
#define OldGcc (Drexc + 1)
|
||||
#define OldGcc (SSE2AVX + 1)
|
||||
/* AT&T mnemonic. */
|
||||
#define ATTMnemonic (OldGcc + 1)
|
||||
/* AT&T syntax. */
|
||||
|
|
@ -260,6 +300,7 @@ typedef struct i386_opcode_modifier
|
|||
unsigned int isstring:1;
|
||||
unsigned int regkludge:1;
|
||||
unsigned int firstxmm0:1;
|
||||
unsigned int implicit1stxmm0:1;
|
||||
unsigned int byteokintel:1;
|
||||
unsigned int todword:1;
|
||||
unsigned int toqword:1;
|
||||
|
|
@ -272,6 +313,18 @@ typedef struct i386_opcode_modifier
|
|||
unsigned int drex:1;
|
||||
unsigned int drexv:1;
|
||||
unsigned int drexc:1;
|
||||
unsigned int vex:1;
|
||||
unsigned int vex256:1;
|
||||
unsigned int vexnds:1;
|
||||
unsigned int vexndd:1;
|
||||
unsigned int vexw0:1;
|
||||
unsigned int vexw1:1;
|
||||
unsigned int vex0f:1;
|
||||
unsigned int vex0f38:1;
|
||||
unsigned int vex0f3a:1;
|
||||
unsigned int vex3sources:1;
|
||||
unsigned int veximmext:1;
|
||||
unsigned int sse2avx:1;
|
||||
unsigned int oldgcc:1;
|
||||
unsigned int attmnemonic:1;
|
||||
unsigned int attsyntax:1;
|
||||
|
|
@ -294,8 +347,10 @@ typedef struct i386_opcode_modifier
|
|||
#define RegMMX (FloatReg + 1)
|
||||
/* SSE register */
|
||||
#define RegXMM (RegMMX + 1)
|
||||
/* AVX registers */
|
||||
#define RegYMM (RegXMM + 1)
|
||||
/* Control register */
|
||||
#define Control (RegXMM + 1)
|
||||
#define Control (RegYMM + 1)
|
||||
/* Debug register */
|
||||
#define Debug (Control + 1)
|
||||
/* Test register */
|
||||
|
|
@ -371,13 +426,18 @@ typedef struct i386_opcode_modifier
|
|||
#define Tbyte (Qword + 1)
|
||||
/* XMMWORD memory. */
|
||||
#define Xmmword (Tbyte + 1)
|
||||
/* YMMWORD memory. */
|
||||
#define Ymmword (Xmmword + 1)
|
||||
/* Unspecified memory size. */
|
||||
#define Unspecified (Xmmword + 1)
|
||||
#define Unspecified (Ymmword + 1)
|
||||
/* Any memory size. */
|
||||
#define Anysize (Unspecified + 1)
|
||||
|
||||
/* VEX 4 bit immediate */
|
||||
#define Vex_Imm4 (Anysize + 1)
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
#define OTMax Anysize
|
||||
#define OTMax Vex_Imm4
|
||||
|
||||
#define OTNumOfUints \
|
||||
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
||||
|
|
@ -399,6 +459,7 @@ typedef union i386_operand_type
|
|||
unsigned int floatreg:1;
|
||||
unsigned int regmmx:1;
|
||||
unsigned int regxmm:1;
|
||||
unsigned int regymm:1;
|
||||
unsigned int control:1;
|
||||
unsigned int debug:1;
|
||||
unsigned int test:1;
|
||||
|
|
@ -432,8 +493,10 @@ typedef union i386_operand_type
|
|||
unsigned int qword:1;
|
||||
unsigned int tbyte:1;
|
||||
unsigned int xmmword:1;
|
||||
unsigned int ymmword:1;
|
||||
unsigned int unspecified:1;
|
||||
unsigned int anysize:1;
|
||||
unsigned int vex_imm4:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
|
|
|
|||
1190
opcodes/i386-opc.tbl
1190
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load Diff
|
|
@ -188,6 +188,23 @@ xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
|
|||
xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
|
||||
xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
|
||||
xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
|
||||
// AVX registers.
|
||||
ymm0, RegYMM, 0, 0, 53, 70
|
||||
ymm1, RegYMM, 0, 1, 54, 71
|
||||
ymm2, RegYMM, 0, 2, 55, 72
|
||||
ymm3, RegYMM, 0, 3, 56, 73
|
||||
ymm4, RegYMM, 0, 4, 57, 74
|
||||
ymm5, RegYMM, 0, 5, 58, 75
|
||||
ymm6, RegYMM, 0, 6, 59, 76
|
||||
ymm7, RegYMM, 0, 7, 60, 77
|
||||
ymm8, RegYMM, RegRex, 0, Dw2Inval, 78
|
||||
ymm9, RegYMM, RegRex, 1, Dw2Inval, 79
|
||||
ymm10, RegYMM, RegRex, 2, Dw2Inval, 80
|
||||
ymm11, RegYMM, RegRex, 3, Dw2Inval, 81
|
||||
ymm12, RegYMM, RegRex, 4, Dw2Inval, 82
|
||||
ymm13, RegYMM, RegRex, 5, Dw2Inval, 83
|
||||
ymm14, RegYMM, RegRex, 6, Dw2Inval, 84
|
||||
ymm15, RegYMM, RegRex, 7, Dw2Inval, 85
|
||||
// No type will make these registers rejected for all purposes except
|
||||
// for addressing. This saves creating one extra type for RIP/EIP.
|
||||
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
|
||||
|
|
|
|||
40876
opcodes/i386-tbl.h
40876
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue