Replace defines with those from intl/libgettext.h to quieten gcc warnings.
This commit is contained in:
Nick Clifton
parent
c1a72ffdd6
commit
c1485d85e0
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@ -1,3 +1,9 @@
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2000-05-30 Nick Clifton <nickc@cygnus.com>
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* opintl.h (gettext, dgettext, dcgettext, textdomain,
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bindtextdomain): Replace defines with those from intl/libgettext.h
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to quieten gcc warnings.
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2000-05-26 Alan Modra <alan@linuxcare.com.au>
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* Makefile.am: Update dependencies with "make dep-am"
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File diff suppressed because it is too large
Load Diff
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@ -282,7 +282,7 @@ disassembler (abfd)
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void
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disassembler_usage (stream)
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FILE *stream ATTRIBUTE_UNUSED;
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FILE * stream ATTRIBUTE_UNUSED;
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{
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#ifdef ARCH_arm
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print_arm_disassembler_options (stream);
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@ -165,11 +165,11 @@ bfd_h8_disassemble (addr, info, mode)
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if (looking_for & DBIT)
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{
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if ((looking_for & 5) != (thisnib &5)) goto fail;
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if ((looking_for & 5) != (thisnib & 5)) goto fail;
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abs = (thisnib & 0x8) ? 2 : 1;
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}
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else if (looking_for & (REG | IND|INC|DEC))
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else if (looking_for & (REG | IND|INC|DEC))
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{
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if (looking_for & SRC)
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{
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File diff suppressed because it is too large
Load Diff
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@ -800,8 +800,8 @@ irf_operand (int op, const char *field)
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if (!field)
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{
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return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3
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|| op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3
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|| op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3
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|| op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3
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|| op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3
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|| op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3;
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}
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else
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@ -1710,6 +1710,7 @@ add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index)
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{
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abort ();
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}
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while (ent != NULL)
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{
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ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits;
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@ -2550,7 +2551,6 @@ insert_completer_entry (opc, tabent, order)
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(*ptr)->is_terminal = 1;
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(*ptr)->mask = (ia64_insn)-1;
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(*ptr)->bits = opc->opcode;
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(*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr);
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(*ptr)->order = order;
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}
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@ -2684,6 +2684,7 @@ add_opcode_entry (opc)
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}
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ordered_table[otlen++] = nent;
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}
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insert_completer_entry (opc, *place, opcode_count++);
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}
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@ -1,5 +1,5 @@
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/* Disassemble MN10300 instructions.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -169,7 +169,7 @@ print_insn_mcore (memaddr, info)
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if (strcmp (op->name, "bsr") == 0)
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{
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/* for bsr, we'll try to get a symbol for the target */
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/* For bsr, we'll try to get a symbol for the target. */
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val = memaddr + 2 + (val << 1);
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if (info->print_address_func && val != 0)
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@ -268,12 +268,12 @@ print_insn_mcore (memaddr, info)
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break;
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default:
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/* if the disassembler lags the instruction set */
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/* If the disassembler lags the instruction set. */
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fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
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break;
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}
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}
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/* Say how many bytes we consumed? */
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/* Say how many bytes we consumed. */
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return 2;
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}
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@ -155,9 +155,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
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{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 },
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{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|M1 },
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{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
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{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 },
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{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|M1 },
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{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
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@ -222,99 +222,99 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
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{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
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{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
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{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
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{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
|
||||
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
|
||||
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
|
||||
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
|
||||
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 },
|
||||
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 },
|
||||
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1 },
|
||||
|
|
@ -539,8 +539,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
|
||||
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
|
||||
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
|
||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
|
||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
|
||||
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
|
||||
|
|
|
|||
|
|
@ -12,19 +12,18 @@
|
|||
|
||||
#ifdef ENABLE_NLS
|
||||
# include <libintl.h>
|
||||
# define _(String) dgettext (PACKAGE, String)
|
||||
# define _(String) gettext (String)
|
||||
# ifdef gettext_noop
|
||||
# define N_(String) gettext_noop (String)
|
||||
# else
|
||||
# define N_(String) (String)
|
||||
# endif
|
||||
#else
|
||||
/* Stubs that do something close enough. */
|
||||
# define textdomain(String) (String)
|
||||
# define gettext(String) (String)
|
||||
# define dgettext(Domain,Message) (Message)
|
||||
# define dcgettext(Domain,Message,Type) (Message)
|
||||
# define bindtextdomain(Domain,Directory) (Domain)
|
||||
# define gettext(Msgid) (Msgid)
|
||||
# define dgettext(Domainname, Msgid) (Msgid)
|
||||
# define dcgettext(Domainname, Msgid, Category) (Msgid)
|
||||
# define textdomain(Domainname) while (0) /* nothing */
|
||||
# define bindtextdomain(Domainname, Dirname) while (0) /* nothing */
|
||||
# define _(String) (String)
|
||||
# define N_(String) (String)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ arc-dis.c
|
|||
arc-opc.c
|
||||
arm-dis.c
|
||||
arm-opc.h
|
||||
avr-dis.c
|
||||
cgen-asm.c
|
||||
cgen-dis.c
|
||||
cgen-opc.c
|
||||
|
|
@ -12,8 +13,8 @@ d10v-dis.c
|
|||
d10v-opc.c
|
||||
d30v-dis.c
|
||||
d30v-opc.c
|
||||
dis-buf.c
|
||||
disassemble.c
|
||||
dis-buf.c
|
||||
fr30-asm.c
|
||||
fr30-desc.c
|
||||
fr30-desc.h
|
||||
|
|
@ -29,6 +30,18 @@ i370-dis.c
|
|||
i370-opc.c
|
||||
i386-dis.c
|
||||
i960-dis.c
|
||||
ia64-asmtab.c
|
||||
ia64-asmtab.h
|
||||
ia64-dis.c
|
||||
ia64-gen.c
|
||||
ia64-opc-a.c
|
||||
ia64-opc-b.c
|
||||
ia64-opc.c
|
||||
ia64-opc-d.c
|
||||
ia64-opc-f.c
|
||||
ia64-opc.h
|
||||
ia64-opc-i.c
|
||||
ia64-opc-m.c
|
||||
m10200-dis.c
|
||||
m10200-opc.c
|
||||
m10300-dis.c
|
||||
|
|
@ -46,9 +59,9 @@ m68k-opc.c
|
|||
m88k-dis.c
|
||||
mcore-dis.c
|
||||
mcore-opc.h
|
||||
mips16-opc.c
|
||||
mips-dis.c
|
||||
mips-opc.c
|
||||
mips16-opc.c
|
||||
ns32k-dis.c
|
||||
pj-dis.c
|
||||
pj-opc.c
|
||||
|
|
@ -60,6 +73,8 @@ sparc-dis.c
|
|||
sparc-opc.c
|
||||
sysdep.h
|
||||
tic30-dis.c
|
||||
tic54x-dis.c
|
||||
tic54x-opc.c
|
||||
tic80-dis.c
|
||||
tic80-opc.c
|
||||
v850-dis.c
|
||||
|
|
@ -68,5 +83,5 @@ vax-dis.c
|
|||
w65-dis.c
|
||||
w65-opc.h
|
||||
z8k-dis.c
|
||||
z8k-opc.h
|
||||
z8kgen.c
|
||||
z8k-opc.h
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
msgid ""
|
||||
msgstr ""
|
||||
"Project-Id-Version: PACKAGE VERSION\n"
|
||||
"POT-Creation-Date: 2000-04-04 23:21+0930\n"
|
||||
"POT-Creation-Date: 2000-05-30 11:33-0700\n"
|
||||
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
|
||||
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
|
||||
"Language-Team: LANGUAGE <LL@li.org>\n"
|
||||
|
|
@ -22,7 +22,7 @@ msgstr ""
|
|||
msgid "jump hint unaligned"
|
||||
msgstr ""
|
||||
|
||||
#: arc-dis.c:231
|
||||
#: arc-dis.c:232
|
||||
msgid "*unknown*"
|
||||
msgstr ""
|
||||
|
||||
|
|
@ -48,21 +48,21 @@ msgstr ""
|
|||
msgid "branch address not on 4 byte boundary"
|
||||
msgstr ""
|
||||
|
||||
#: arm-dis.c:470
|
||||
#: arm-dis.c:476
|
||||
msgid "<illegal precision>"
|
||||
msgstr ""
|
||||
|
||||
#: arm-dis.c:882
|
||||
#: arm-dis.c:888
|
||||
#, c-format
|
||||
msgid "Unrecognised register name set: %s\n"
|
||||
msgstr ""
|
||||
|
||||
#: arm-dis.c:889
|
||||
#: arm-dis.c:895
|
||||
#, c-format
|
||||
msgid "Unrecognised disassembler option: %s\n"
|
||||
msgstr ""
|
||||
|
||||
#: arm-dis.c:1053
|
||||
#: arm-dis.c:1059
|
||||
msgid ""
|
||||
"\n"
|
||||
"The following ARM specific disassembler options are supported for use with\n"
|
||||
|
|
@ -83,7 +83,7 @@ msgstr ""
|
|||
msgid "operand out of range (%lu not between %lu and %lu)"
|
||||
msgstr ""
|
||||
|
||||
#: d30v-dis.c:305
|
||||
#: d30v-dis.c:306
|
||||
#, c-format
|
||||
msgid "<unknown register %d>"
|
||||
msgstr ""
|
||||
|
|
@ -171,23 +171,23 @@ msgstr ""
|
|||
msgid "Unrecognized field %d while setting vma operand.\n"
|
||||
msgstr ""
|
||||
|
||||
#: h8300-dis.c:404
|
||||
#: h8300-dis.c:405
|
||||
#, c-format
|
||||
msgid "Hmmmm %x"
|
||||
msgstr ""
|
||||
|
||||
#: h8300-dis.c:416
|
||||
#: h8300-dis.c:417
|
||||
#, c-format
|
||||
msgid "Don't understand %x \n"
|
||||
msgstr ""
|
||||
|
||||
#: h8500-dis.c:139
|
||||
#: h8500-dis.c:140
|
||||
#, c-format
|
||||
msgid "can't cope with insert %d\n"
|
||||
msgstr ""
|
||||
|
||||
#. Couldn't understand anything
|
||||
#: h8500-dis.c:344
|
||||
#: h8500-dis.c:345
|
||||
#, c-format
|
||||
msgid "%02x\t\t*unknown*"
|
||||
msgstr ""
|
||||
|
|
@ -202,27 +202,27 @@ msgstr ""
|
|||
msgid "unknown\t0x%04lx"
|
||||
msgstr ""
|
||||
|
||||
#: m10300-dis.c:680
|
||||
#: m10300-dis.c:685
|
||||
#, c-format
|
||||
msgid "unknown\t0x%04x"
|
||||
msgstr ""
|
||||
|
||||
#: m68k-dis.c:410
|
||||
#: m68k-dis.c:412
|
||||
#, c-format
|
||||
msgid "<internal error in opcode table: %s %s>\n"
|
||||
msgstr ""
|
||||
|
||||
#: m68k-dis.c:988
|
||||
#: m68k-dis.c:990
|
||||
#, c-format
|
||||
msgid "<function code %d>"
|
||||
msgstr ""
|
||||
|
||||
#: m88k-dis.c:273
|
||||
#: m88k-dis.c:274
|
||||
#, c-format
|
||||
msgid "# <dis error: %08x>"
|
||||
msgstr ""
|
||||
|
||||
#: mips-dis.c:237
|
||||
#: mips-dis.c:242
|
||||
#, c-format
|
||||
msgid "# internal error, undefined modifier(%c)"
|
||||
msgstr ""
|
||||
|
|
@ -237,50 +237,50 @@ msgstr ""
|
|||
msgid "$<undefined>"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:586 ppc-opc.c:617
|
||||
#: ppc-opc.c:619 ppc-opc.c:650
|
||||
msgid "invalid conditional option"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:619
|
||||
#: ppc-opc.c:652
|
||||
msgid "attempt to set y bit when using + or - modifier"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:674
|
||||
#: ppc-opc.c:707
|
||||
msgid "ignoring least significant bits in branch offset"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:709 ppc-opc.c:746
|
||||
#: ppc-opc.c:742 ppc-opc.c:779
|
||||
msgid "illegal bitmask"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:815
|
||||
#: ppc-opc.c:848
|
||||
msgid "value out of range"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:889
|
||||
#: ppc-opc.c:922
|
||||
msgid "index register in load range"
|
||||
msgstr ""
|
||||
|
||||
#: ppc-opc.c:904
|
||||
#: ppc-opc.c:937
|
||||
msgid "invalid register operand when updating"
|
||||
msgstr ""
|
||||
|
||||
#. Mark as non-valid instruction
|
||||
#: sparc-dis.c:744
|
||||
#: sparc-dis.c:743
|
||||
msgid "unknown"
|
||||
msgstr ""
|
||||
|
||||
#: sparc-dis.c:816
|
||||
#: sparc-dis.c:815
|
||||
#, c-format
|
||||
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
|
||||
msgstr ""
|
||||
|
||||
#: sparc-dis.c:827
|
||||
#: sparc-dis.c:826
|
||||
#, c-format
|
||||
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
|
||||
msgstr ""
|
||||
|
||||
#: sparc-dis.c:876
|
||||
#: sparc-dis.c:875
|
||||
#, c-format
|
||||
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
|
||||
msgstr ""
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#include <errno.h>
|
||||
#include <math.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "sysdep.h"
|
||||
#include "dis-asm.h"
|
||||
#include "opcode/tic54x.h"
|
||||
#include "coff/tic54x.h"
|
||||
|
|
|
|||
|
|
@ -17,8 +17,7 @@
|
|||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
|
||||
02111-1307, USA. */
|
||||
|
||||
#include <stdio.h>
|
||||
#include "ansidecl.h"
|
||||
#include "sysdep.h"
|
||||
#include "opcode/tic54x.h"
|
||||
|
||||
/* these are the only register names not found in mmregs */
|
||||
|
|
|
|||
Loading…
Reference in New Issue