* Makefile.in (SPARC64_OBJS): Add dev64.o.
(CPU_OBJS): New variable. (SIM_OBJS): Add sparc-desc.o. (SIM_EXTRA_DEPS): Replace cpu-opc.h with sparc-desc.h. (sim-core.o): Add dev64.h dependency. (dev64.o): Add rule. (stamp-arch,stamp-cpu32): Update FLAGS variable, option syntax changed. (stamp-cpu64): Ditto. (stamp-desc): New rule. * configure.in (sim_link_files,sim_link_links): Delete. Set cpu_objs to one of SPARC32_OBJS,SPARC64_OBJS. * configure: Rebuild. * acconfig.h: Rebuild. * config.in: Rebuild. * dev64.c: New file. * dev64.h: New file. * sparc64.c: New file. * trap64.h: New file. * arch.c,arch.h,cpuall.h: Rebuild. * cpu32.c,decode32.c,decode32.h,model32.c,sem32.c: Rebuild. * sim-if.c (sparc_disassemble_insn): New function. (sim_open): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. Set disassembler. (sim_close): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open. * sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include sparc-desc.h,sparc-opc.h,sparc-sim.h.
This commit is contained in:
Doug Evans
parent
9aa2d8ddaf
commit
c14d22a7a7
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@ -38,6 +38,8 @@ decode32.c
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decode32.h
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dev32.c
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dev32.h
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dev64.c
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dev64.h
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mloop32.in
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model32.c
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regs32.h
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@ -47,9 +49,11 @@ sim-main.h
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sparc-sim.h
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sparc.c
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sparc32.c
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sparc64.c
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tconfig.in
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trap32.c
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trap32.h
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trap64.h
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Things-to-lose:
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@ -0,0 +1,32 @@
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1999-02-09 Doug Evans <devans@casey.cygnus.com>
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* Makefile.in (SPARC64_OBJS): Add dev64.o.
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(CPU_OBJS): New variable.
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(SIM_OBJS): Add sparc-desc.o.
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(SIM_EXTRA_DEPS): Replace cpu-opc.h with sparc-desc.h.
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(sim-core.o): Add dev64.h dependency.
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(dev64.o): Add rule.
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(stamp-arch,stamp-cpu32): Update FLAGS variable, option syntax changed.
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(stamp-cpu64): Ditto.
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(stamp-desc): New rule.
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* configure.in (sim_link_files,sim_link_links): Delete.
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Set cpu_objs to one of SPARC32_OBJS,SPARC64_OBJS.
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* configure: Rebuild.
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* acconfig.h: Rebuild.
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* config.in: Rebuild.
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* dev64.c: New file.
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* dev64.h: New file.
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* sparc64.c: New file.
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* trap64.h: New file.
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* arch.c,arch.h,cpuall.h: Rebuild.
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* cpu32.c,decode32.c,decode32.h,model32.c,sem32.c: Rebuild.
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* sim-if.c (sparc_disassemble_insn): New function.
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(sim_open): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open.
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Set disassembler.
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(sim_close): sparc_cgen_cpu_open renamed from sparc_cgen_opcode_open.
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* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
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sparc-desc.h,sparc-opc.h,sparc-sim.h.
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1999-02-02 Doug Evans <devans@casey.cygnus.com>
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* Directory created.
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@ -4,7 +4,10 @@
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## COMMON_PRE_CONFIG_FRAG
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SPARC32_OBJS = sparc32.o trap32.o dev32.o cpu32.o decode32.o model32.o mloop32.o sem32.o
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SPARC64_OBJS = sparc64.o trap64.o cpu64.o decode64.o model64.o mloop64.o sem64.o
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SPARC64_OBJS = sparc64.o trap64.o dev64.o cpu64.o decode64.o model64.o mloop64.o sem64.o
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# Set to one of SPARC32_OBJS/SPARC64_OBJS.
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CPU_OBJS = @cpu_objs@
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SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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@ -15,14 +18,14 @@ SIM_OBJS = \
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sim-reg.o \
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cgen-utils.o cgen-trace.o cgen-scache.o \
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cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
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sim-if.o sparc.o arch.o \
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$(SPARC32_OBJS)
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sim-if.o sparc.o arch.o sparc-desc.o \
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$(CPU_OBJS)
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# Extra headers included by sim-main.h.
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# This plus sim_main_headers is used by Make-common.in for files in common.
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SIM_EXTRA_DEPS = \
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$(CGEN_INCLUDE_DEPS) \
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arch.h cpuall.h cpu-opc.h
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arch.h cpuall.h sparc-desc.h
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# sparc-sim.h kept out for now (too much unnecessary recompilation)
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SIM_EXTRA_CFLAGS =
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@ -37,7 +40,8 @@ NL_TARGET = -DNL_TARGET_sparc
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arch = sparc
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sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h dev32.h
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sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h \
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dev32.h dev64.h
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sparc.o: sparc.c $(SIM_MAIN_DEPS) \
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$(srcdir)/../common/cgen-mem.h \
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$(srcdir)/../common/cgen-ops.h
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@ -81,6 +85,7 @@ SPARC64_INCLUDE_DEPS = \
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sparc64.o: sparc64.c $(SPARC64_INCLUDE_DEPS)
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trap64.o: trap64.c $(SPARC64_INCLUDE_DEPS)
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dev64.o: dev64.c $(SPARC32_INCLUDE_DEPS) dev64.h
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# FIXME: Use of `mono' is wip.
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mloop64.c eng64.h: stamp-mloop64
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@ -98,38 +103,50 @@ decode64.o: decode64.c $(SPARC64_INCLUDE_DEPS)
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model64.o: model64.c $(SPARC64_INCLUDE_DEPS)
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sparc-clean:
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rm -f mloop32.c eng32.h mloop64.c eng64.h stamp-mloop32 stamp-mloop64
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rm -f stamp-arch stamp-cpu32 stamp-cpu64
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rm -f mloop32.c eng32.h stamp-mloop32
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rm -f mloop64.c eng64.h stamp-mloop64
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rm -f stamp-arch stamp-cpu32 stamp-cpu64 stamp-desc
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rm -f tmp-*
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# cgen support
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stamp-arch: $(CGEN_MAIN_SCM) $(CGEN_ARCH_SCM) \
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stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) \
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$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu \
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$(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu
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$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=sparc-v8,sparclite
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$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \
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mach=sparc-v8,sparclite,sparc-v9 \
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FLAGS="copyright=cygnus package=cygsim"
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touch stamp-arch
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arch.h arch.c cpuall.h: $(CGEN_MAIN) stamp-arch
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@true
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# Add with-scache to FLAGS when switching to -pbb.
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stamp-cpu32: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
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stamp-cpu32: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
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$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=sparc32 mach=sparc-v8,sparclite SUFFIX=32 \
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FLAGS="with-profile fn" \
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FLAGS="with-profile=fn copyright=cygnus package=cygsim" \
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EXTRAFILES="$(CGEN_CPU_SEM)"
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touch stamp-cpu32
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cpu32.h decode32.h decode32.c model32.c sem32.c sem32-switch.c: $(CGEN_MAINT) stamp-cpu32
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@true
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# Add with-scache to FLAGS when switching to -pbb.
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stamp-cpu64: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
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stamp-cpu64: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) \
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$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc64.cpu
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$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
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cpu=sparc64 mach=sparc-v9,sparc-v9a SUFFIX=64 \
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FLAGS="with-profile fn" \
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cpu=sparc64 mach=sparc-v9 SUFFIX=64 \
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FLAGS="with-profile=fn copyright=cygnus package=cygsim" \
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EXTRAFILES="$(CGEN_CPU_SEM)"
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touch stamp-cpu64
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cpu64.h decode64.h decode64.c model64.c sem64.c sem64-switch.c: $(CGEN_MAINT) stamp-cpu64
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@true
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stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \
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$(srccgen)/sparc.cpu $(srccgen)/sparccom.cpu $(srccgen)/sparc32.cpu $(srccgen)/sparc64.cpu
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$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
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cpu=sparc mach=all \
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FLAGS="copyright=cygnus package=cygsim"
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touch stamp-desc
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sparc-desc.c sparc-desc.h sparc-opc: $(CGEN_MAINT) stamp-desc
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@true
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@ -13,3 +13,6 @@
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/* Define if your locale.h file contains LC_MESSAGES. */
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#undef HAVE_LC_MESSAGES
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/* Define if sparc64 target. */
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#undef SPARC64_P
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,149 @@
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/* Simulator header for sparc.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1999 Cygnus Solutions, Inc.
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This file is part of the Cygnus Simulators.
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*/
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#ifndef SPARC_ARCH_H
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#define SPARC_ARCH_H
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#define TARGET_BIG_ENDIAN 1
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/* Cover fns for register access. */
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USI a_sparc_h_pc_get (SIM_CPU *);
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void a_sparc_h_pc_set (SIM_CPU *, USI);
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SI a_sparc_h_npc_get (SIM_CPU *);
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void a_sparc_h_npc_set (SIM_CPU *, SI);
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SI a_sparc_h_gr_get (SIM_CPU *, UINT);
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void a_sparc_h_gr_set (SIM_CPU *, UINT, SI);
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BI a_sparc_h_icc_c_get (SIM_CPU *);
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void a_sparc_h_icc_c_set (SIM_CPU *, BI);
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BI a_sparc_h_icc_n_get (SIM_CPU *);
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void a_sparc_h_icc_n_set (SIM_CPU *, BI);
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BI a_sparc_h_icc_v_get (SIM_CPU *);
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void a_sparc_h_icc_v_set (SIM_CPU *, BI);
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BI a_sparc_h_icc_z_get (SIM_CPU *);
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void a_sparc_h_icc_z_set (SIM_CPU *, BI);
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BI a_sparc_h_xcc_c_get (SIM_CPU *);
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void a_sparc_h_xcc_c_set (SIM_CPU *, BI);
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BI a_sparc_h_xcc_n_get (SIM_CPU *);
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void a_sparc_h_xcc_n_set (SIM_CPU *, BI);
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BI a_sparc_h_xcc_v_get (SIM_CPU *);
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void a_sparc_h_xcc_v_set (SIM_CPU *, BI);
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BI a_sparc_h_xcc_z_get (SIM_CPU *);
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void a_sparc_h_xcc_z_set (SIM_CPU *, BI);
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SI a_sparc_h_y_get (SIM_CPU *);
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void a_sparc_h_y_set (SIM_CPU *, SI);
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SI a_sparc_h_asr_get (SIM_CPU *, UINT);
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void a_sparc_h_asr_set (SIM_CPU *, UINT, SI);
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BI a_sparc_h_annul_p_get (SIM_CPU *);
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void a_sparc_h_annul_p_set (SIM_CPU *, BI);
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SF a_sparc_h_fr_get (SIM_CPU *, UINT);
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void a_sparc_h_fr_set (SIM_CPU *, UINT, SF);
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USI a_sparc_h_psr_get (SIM_CPU *);
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void a_sparc_h_psr_set (SIM_CPU *, USI);
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BI a_sparc_h_s_get (SIM_CPU *);
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void a_sparc_h_s_set (SIM_CPU *, BI);
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BI a_sparc_h_ps_get (SIM_CPU *);
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void a_sparc_h_ps_set (SIM_CPU *, BI);
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UQI a_sparc_h_pil_get (SIM_CPU *);
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void a_sparc_h_pil_set (SIM_CPU *, UQI);
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BI a_sparc_h_et_get (SIM_CPU *);
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void a_sparc_h_et_set (SIM_CPU *, BI);
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SI a_sparc_h_tbr_get (SIM_CPU *);
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void a_sparc_h_tbr_set (SIM_CPU *, SI);
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UQI a_sparc_h_cwp_get (SIM_CPU *);
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void a_sparc_h_cwp_set (SIM_CPU *, UQI);
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USI a_sparc_h_wim_get (SIM_CPU *);
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void a_sparc_h_wim_set (SIM_CPU *, USI);
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QI a_sparc_h_ag_get (SIM_CPU *);
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void a_sparc_h_ag_set (SIM_CPU *, QI);
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BI a_sparc_h_ec_get (SIM_CPU *);
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void a_sparc_h_ec_set (SIM_CPU *, BI);
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BI a_sparc_h_ef_get (SIM_CPU *);
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void a_sparc_h_ef_set (SIM_CPU *, BI);
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USI a_sparc_h_fsr_get (SIM_CPU *);
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void a_sparc_h_fsr_set (SIM_CPU *, USI);
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UDI a_sparc_h_ver_get (SIM_CPU *);
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void a_sparc_h_ver_set (SIM_CPU *, UDI);
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UDI a_sparc_h_pstate_get (SIM_CPU *);
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void a_sparc_h_pstate_set (SIM_CPU *, UDI);
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UDI a_sparc_h_tba_get (SIM_CPU *);
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void a_sparc_h_tba_set (SIM_CPU *, UDI);
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UDI a_sparc_h_tt_get (SIM_CPU *);
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void a_sparc_h_tt_set (SIM_CPU *, UDI);
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UQI a_sparc_h_asi_get (SIM_CPU *);
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void a_sparc_h_asi_set (SIM_CPU *, UQI);
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UQI a_sparc_h_tl_get (SIM_CPU *);
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void a_sparc_h_tl_set (SIM_CPU *, UQI);
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UDI a_sparc_h_tpc_get (SIM_CPU *);
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void a_sparc_h_tpc_set (SIM_CPU *, UDI);
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UDI a_sparc_h_tnpc_get (SIM_CPU *);
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void a_sparc_h_tnpc_set (SIM_CPU *, UDI);
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UDI a_sparc_h_tstate_get (SIM_CPU *);
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void a_sparc_h_tstate_set (SIM_CPU *, UDI);
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UDI a_sparc_h_tick_get (SIM_CPU *);
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void a_sparc_h_tick_set (SIM_CPU *, UDI);
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UDI a_sparc_h_cansave_get (SIM_CPU *);
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void a_sparc_h_cansave_set (SIM_CPU *, UDI);
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UDI a_sparc_h_canrestore_get (SIM_CPU *);
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void a_sparc_h_canrestore_set (SIM_CPU *, UDI);
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UDI a_sparc_h_otherwin_get (SIM_CPU *);
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void a_sparc_h_otherwin_set (SIM_CPU *, UDI);
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UDI a_sparc_h_cleanwin_get (SIM_CPU *);
|
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void a_sparc_h_cleanwin_set (SIM_CPU *, UDI);
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UDI a_sparc_h_wstate_get (SIM_CPU *);
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void a_sparc_h_wstate_set (SIM_CPU *, UDI);
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UQI a_sparc_h_fcc0_get (SIM_CPU *);
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void a_sparc_h_fcc0_set (SIM_CPU *, UQI);
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UQI a_sparc_h_fcc1_get (SIM_CPU *);
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void a_sparc_h_fcc1_set (SIM_CPU *, UQI);
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UQI a_sparc_h_fcc2_get (SIM_CPU *);
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void a_sparc_h_fcc2_set (SIM_CPU *, UQI);
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||||
UQI a_sparc_h_fcc3_get (SIM_CPU *);
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||||
void a_sparc_h_fcc3_set (SIM_CPU *, UQI);
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UQI a_sparc_h_fsr_rd_get (SIM_CPU *);
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void a_sparc_h_fsr_rd_set (SIM_CPU *, UQI);
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UQI a_sparc_h_fsr_tem_get (SIM_CPU *);
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void a_sparc_h_fsr_tem_set (SIM_CPU *, UQI);
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BI a_sparc_h_fsr_ns_get (SIM_CPU *);
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void a_sparc_h_fsr_ns_set (SIM_CPU *, BI);
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UQI a_sparc_h_fsr_ver_get (SIM_CPU *);
|
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void a_sparc_h_fsr_ver_set (SIM_CPU *, UQI);
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UQI a_sparc_h_fsr_ftt_get (SIM_CPU *);
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void a_sparc_h_fsr_ftt_set (SIM_CPU *, UQI);
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BI a_sparc_h_fsr_qne_get (SIM_CPU *);
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void a_sparc_h_fsr_qne_set (SIM_CPU *, BI);
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UQI a_sparc_h_fsr_aexc_get (SIM_CPU *);
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void a_sparc_h_fsr_aexc_set (SIM_CPU *, UQI);
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UQI a_sparc_h_fsr_cexc_get (SIM_CPU *);
|
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void a_sparc_h_fsr_cexc_set (SIM_CPU *, UQI);
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||||
BI a_sparc_h_fpsr_fef_get (SIM_CPU *);
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void a_sparc_h_fpsr_fef_set (SIM_CPU *, BI);
|
||||
BI a_sparc_h_fpsr_du_get (SIM_CPU *);
|
||||
void a_sparc_h_fpsr_du_set (SIM_CPU *, BI);
|
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BI a_sparc_h_fpsr_dl_get (SIM_CPU *);
|
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void a_sparc_h_fpsr_dl_set (SIM_CPU *, BI);
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||||
UQI a_sparc_h_fpsr_get (SIM_CPU *);
|
||||
void a_sparc_h_fpsr_set (SIM_CPU *, UQI);
|
||||
|
||||
/* Enum declaration for model types. */
|
||||
typedef enum model_type {
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MODEL_SPARC32_DEF, MODEL_SPARC64_DEF, MODEL_MAX
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} MODEL_TYPE;
|
||||
|
||||
#define MAX_MODELS ((int) MODEL_MAX)
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||||
|
||||
/* Enum declaration for unit types. */
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typedef enum unit_type {
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UNIT_NONE, UNIT_SPARC32_DEF_U_EXEC, UNIT_SPARC64_DEF_U_EXEC, UNIT_MAX
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} UNIT_TYPE;
|
||||
|
||||
#define MAX_UNITS (1)
|
||||
|
||||
#endif /* SPARC_ARCH_H */
|
||||
|
|
@ -0,0 +1,618 @@
|
|||
/* CPU family header for sparc32.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1999 Cygnus Solutions, Inc.
|
||||
|
||||
This file is part of the Cygnus Simulators.
|
||||
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CPU_SPARC32_H
|
||||
#define CPU_SPARC32_H
|
||||
|
||||
/* Maximum number of instructions that are fetched at a time.
|
||||
This is for LIW type instructions sets (e.g. m32r). */
|
||||
#define MAX_LIW_INSNS 1
|
||||
|
||||
/* Maximum number of instructions that can be executed in parallel. */
|
||||
#define MAX_PARALLEL_INSNS 1
|
||||
|
||||
/* CPU state information. */
|
||||
typedef struct {
|
||||
/* Hardware elements. */
|
||||
struct {
|
||||
/* program counter */
|
||||
USI h_pc;
|
||||
#define GET_H_PC() CPU (h_pc)
|
||||
#define SET_H_PC(x) (CPU (h_pc) = (x))
|
||||
/* next pc */
|
||||
SI h_npc;
|
||||
#define GET_H_NPC() CPU (h_npc)
|
||||
#define SET_H_NPC(x) (CPU (h_npc) = (x))
|
||||
/* GET_H_GR macro user-written */
|
||||
/* SET_H_GR macro user-written */
|
||||
/* icc carry bit */
|
||||
BI h_icc_c;
|
||||
#define GET_H_ICC_C() CPU (h_icc_c)
|
||||
#define SET_H_ICC_C(x) (CPU (h_icc_c) = (x))
|
||||
/* icc negative bit */
|
||||
BI h_icc_n;
|
||||
#define GET_H_ICC_N() CPU (h_icc_n)
|
||||
#define SET_H_ICC_N(x) (CPU (h_icc_n) = (x))
|
||||
/* icc overflow bit */
|
||||
BI h_icc_v;
|
||||
#define GET_H_ICC_V() CPU (h_icc_v)
|
||||
#define SET_H_ICC_V(x) (CPU (h_icc_v) = (x))
|
||||
/* icc zero bit */
|
||||
BI h_icc_z;
|
||||
#define GET_H_ICC_Z() CPU (h_icc_z)
|
||||
#define SET_H_ICC_Z(x) (CPU (h_icc_z) = (x))
|
||||
/* xcc carry bit */
|
||||
BI h_xcc_c;
|
||||
#define GET_H_XCC_C() CPU (h_xcc_c)
|
||||
#define SET_H_XCC_C(x) (CPU (h_xcc_c) = (x))
|
||||
/* xcc negative bit */
|
||||
BI h_xcc_n;
|
||||
#define GET_H_XCC_N() CPU (h_xcc_n)
|
||||
#define SET_H_XCC_N(x) (CPU (h_xcc_n) = (x))
|
||||
/* xcc overflow bit */
|
||||
BI h_xcc_v;
|
||||
#define GET_H_XCC_V() CPU (h_xcc_v)
|
||||
#define SET_H_XCC_V(x) (CPU (h_xcc_v) = (x))
|
||||
/* xcc zero bit */
|
||||
BI h_xcc_z;
|
||||
#define GET_H_XCC_Z() CPU (h_xcc_z)
|
||||
#define SET_H_XCC_Z(x) (CPU (h_xcc_z) = (x))
|
||||
/* GET_H_Y macro user-written */
|
||||
/* SET_H_Y macro user-written */
|
||||
/* ancilliary state registers */
|
||||
SI h_asr[32];
|
||||
#define GET_H_ASR(a1) CPU (h_asr)[a1]
|
||||
#define SET_H_ASR(a1, x) (CPU (h_asr)[a1] = (x))
|
||||
/* annul next insn? - assists execution */
|
||||
BI h_annul_p;
|
||||
#define GET_H_ANNUL_P() CPU (h_annul_p)
|
||||
#define SET_H_ANNUL_P(x) (CPU (h_annul_p) = (x))
|
||||
/* floating point regs */
|
||||
SF h_fr[32];
|
||||
#define GET_H_FR(a1) CPU (h_fr)[a1]
|
||||
#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
|
||||
/* psr register */
|
||||
USI h_psr;
|
||||
/* GET_H_PSR macro user-written */
|
||||
/* SET_H_PSR macro user-written */
|
||||
/* supervisor bit */
|
||||
BI h_s;
|
||||
#define GET_H_S() CPU (h_s)
|
||||
#define SET_H_S(x) (CPU (h_s) = (x))
|
||||
/* previous supervisor bit */
|
||||
BI h_ps;
|
||||
#define GET_H_PS() CPU (h_ps)
|
||||
#define SET_H_PS(x) (CPU (h_ps) = (x))
|
||||
/* processor interrupt level */
|
||||
UQI h_pil;
|
||||
#define GET_H_PIL() CPU (h_pil)
|
||||
#define SET_H_PIL(x) (CPU (h_pil) = (x))
|
||||
/* enable traps bit */
|
||||
BI h_et;
|
||||
#define GET_H_ET() CPU (h_et)
|
||||
#define SET_H_ET(x) (CPU (h_et) = (x))
|
||||
/* tbr register */
|
||||
SI h_tbr;
|
||||
/* GET_H_TBR macro user-written */
|
||||
/* SET_H_TBR macro user-written */
|
||||
/* current window pointer */
|
||||
UQI h_cwp;
|
||||
/* GET_H_CWP macro user-written */
|
||||
/* SET_H_CWP macro user-written */
|
||||
/* window invalid mask */
|
||||
USI h_wim;
|
||||
/* GET_H_WIM macro user-written */
|
||||
/* SET_H_WIM macro user-written */
|
||||
/* alternate global indicator */
|
||||
QI h_ag;
|
||||
#define GET_H_AG() CPU (h_ag)
|
||||
#define SET_H_AG(x) (CPU (h_ag) = (x))
|
||||
/* enable coprocessor bit */
|
||||
BI h_ec;
|
||||
#define GET_H_EC() CPU (h_ec)
|
||||
#define SET_H_EC(x) (CPU (h_ec) = (x))
|
||||
/* enable fpu bit */
|
||||
BI h_ef;
|
||||
#define GET_H_EF() CPU (h_ef)
|
||||
#define SET_H_EF(x) (CPU (h_ef) = (x))
|
||||
/* floating point status register */
|
||||
USI h_fsr;
|
||||
#define GET_H_FSR() CPU (h_fsr)
|
||||
#define SET_H_FSR(x) (CPU (h_fsr) = (x))
|
||||
} hardware;
|
||||
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
|
||||
} SPARC32_CPU_DATA;
|
||||
|
||||
/* Cover fns for register access. */
|
||||
USI sparc32_h_pc_get (SIM_CPU *);
|
||||
void sparc32_h_pc_set (SIM_CPU *, USI);
|
||||
SI sparc32_h_npc_get (SIM_CPU *);
|
||||
void sparc32_h_npc_set (SIM_CPU *, SI);
|
||||
SI sparc32_h_gr_get (SIM_CPU *, UINT);
|
||||
void sparc32_h_gr_set (SIM_CPU *, UINT, SI);
|
||||
BI sparc32_h_icc_c_get (SIM_CPU *);
|
||||
void sparc32_h_icc_c_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_icc_n_get (SIM_CPU *);
|
||||
void sparc32_h_icc_n_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_icc_v_get (SIM_CPU *);
|
||||
void sparc32_h_icc_v_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_icc_z_get (SIM_CPU *);
|
||||
void sparc32_h_icc_z_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_xcc_c_get (SIM_CPU *);
|
||||
void sparc32_h_xcc_c_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_xcc_n_get (SIM_CPU *);
|
||||
void sparc32_h_xcc_n_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_xcc_v_get (SIM_CPU *);
|
||||
void sparc32_h_xcc_v_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_xcc_z_get (SIM_CPU *);
|
||||
void sparc32_h_xcc_z_set (SIM_CPU *, BI);
|
||||
SI sparc32_h_y_get (SIM_CPU *);
|
||||
void sparc32_h_y_set (SIM_CPU *, SI);
|
||||
SI sparc32_h_asr_get (SIM_CPU *, UINT);
|
||||
void sparc32_h_asr_set (SIM_CPU *, UINT, SI);
|
||||
BI sparc32_h_annul_p_get (SIM_CPU *);
|
||||
void sparc32_h_annul_p_set (SIM_CPU *, BI);
|
||||
SF sparc32_h_fr_get (SIM_CPU *, UINT);
|
||||
void sparc32_h_fr_set (SIM_CPU *, UINT, SF);
|
||||
USI sparc32_h_psr_get (SIM_CPU *);
|
||||
void sparc32_h_psr_set (SIM_CPU *, USI);
|
||||
BI sparc32_h_s_get (SIM_CPU *);
|
||||
void sparc32_h_s_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_ps_get (SIM_CPU *);
|
||||
void sparc32_h_ps_set (SIM_CPU *, BI);
|
||||
UQI sparc32_h_pil_get (SIM_CPU *);
|
||||
void sparc32_h_pil_set (SIM_CPU *, UQI);
|
||||
BI sparc32_h_et_get (SIM_CPU *);
|
||||
void sparc32_h_et_set (SIM_CPU *, BI);
|
||||
SI sparc32_h_tbr_get (SIM_CPU *);
|
||||
void sparc32_h_tbr_set (SIM_CPU *, SI);
|
||||
UQI sparc32_h_cwp_get (SIM_CPU *);
|
||||
void sparc32_h_cwp_set (SIM_CPU *, UQI);
|
||||
USI sparc32_h_wim_get (SIM_CPU *);
|
||||
void sparc32_h_wim_set (SIM_CPU *, USI);
|
||||
QI sparc32_h_ag_get (SIM_CPU *);
|
||||
void sparc32_h_ag_set (SIM_CPU *, QI);
|
||||
BI sparc32_h_ec_get (SIM_CPU *);
|
||||
void sparc32_h_ec_set (SIM_CPU *, BI);
|
||||
BI sparc32_h_ef_get (SIM_CPU *);
|
||||
void sparc32_h_ef_set (SIM_CPU *, BI);
|
||||
USI sparc32_h_fsr_get (SIM_CPU *);
|
||||
void sparc32_h_fsr_set (SIM_CPU *, USI);
|
||||
|
||||
/* These must be hand-written. */
|
||||
extern CPUREG_FETCH_FN sparc32_fetch_register;
|
||||
extern CPUREG_STORE_FN sparc32_store_register;
|
||||
|
||||
typedef struct {
|
||||
int empty;
|
||||
} MODEL_SPARC32_DEF_DATA;
|
||||
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* cpu specific data follows */
|
||||
CGEN_INSN_INT insn;
|
||||
int written;
|
||||
};
|
||||
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
|
||||
/* Macros to simplify extraction, reading and semantic code.
|
||||
These define and assign the local vars that contain the insn's fields. */
|
||||
|
||||
#define EXTRACT_IFMT_EMPTY_VARS \
|
||||
/* Instruction fields. */ \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EMPTY_CODE \
|
||||
length = 0; \
|
||||
|
||||
#define EXTRACT_IFMT_RD_ASR_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_RD_ASR_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_WR_ASR_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
INT f_res_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_WR_ASR_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_WR_ASR_IMM_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_WR_ASR_IMM_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_RD_PSR_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_RD_PSR_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_WR_PSR_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
INT f_res_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_WR_PSR_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_WR_PSR_IMM_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_WR_PSR_IMM_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_LDSTUB_REG_REG_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
INT f_res_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDSTUB_REG_REG_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_LDSTUB_REG_IMM_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDSTUB_REG_IMM_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
UINT f_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDSTUB_REG_REG_ASI_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_LDD_REG_REG_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
INT f_res_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDD_REG_REG_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_LDD_REG_IMM_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDD_REG_IMM_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_LDD_REG_REG_ASI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
UINT f_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDD_REG_REG_ASI_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_FP_LD_REG_REG_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
INT f_res_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_FP_LD_REG_REG_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_FP_LD_REG_IMM_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_FP_LD_REG_IMM_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
UINT f_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_FP_LD_REG_REG_ASI_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_asi = EXTRACT_UINT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_SETHI_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_hi22; \
|
||||
UINT f_op2; \
|
||||
UINT f_rd; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_SETHI_CODE \
|
||||
length = 4; \
|
||||
f_hi22 = EXTRACT_INT (insn, 32, 21, 22); \
|
||||
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
||||
f_rd = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_UNIMP_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_imm22; \
|
||||
UINT f_op2; \
|
||||
UINT f_rd_res; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_UNIMP_CODE \
|
||||
length = 4; \
|
||||
f_imm22 = EXTRACT_INT (insn, 32, 21, 22); \
|
||||
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
||||
f_rd_res = EXTRACT_UINT (insn, 32, 29, 5); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_CALL_VARS \
|
||||
/* Instruction fields. */ \
|
||||
SI f_disp30; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_CALL_CODE \
|
||||
length = 4; \
|
||||
f_disp30 = ((((EXTRACT_INT (insn, 32, 29, 30)) << (2))) + (pc)); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_BA_VARS \
|
||||
/* Instruction fields. */ \
|
||||
SI f_disp22; \
|
||||
UINT f_op2; \
|
||||
UINT f_fmt2_cond; \
|
||||
UINT f_a; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_BA_CODE \
|
||||
length = 4; \
|
||||
f_disp22 = ((((EXTRACT_INT (insn, 32, 21, 22)) << (2))) + (pc)); \
|
||||
f_op2 = EXTRACT_UINT (insn, 32, 24, 3); \
|
||||
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
||||
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_TA_VARS \
|
||||
/* Instruction fields. */ \
|
||||
UINT f_rs2; \
|
||||
INT f_res_asi; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_fmt2_cond; \
|
||||
UINT f_a; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_TA_CODE \
|
||||
length = 4; \
|
||||
f_rs2 = EXTRACT_UINT (insn, 32, 4, 5); \
|
||||
f_res_asi = EXTRACT_INT (insn, 32, 12, 8); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
||||
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
#define EXTRACT_IFMT_TA_IMM_VARS \
|
||||
/* Instruction fields. */ \
|
||||
INT f_simm13; \
|
||||
UINT f_i; \
|
||||
UINT f_rs1; \
|
||||
UINT f_op3; \
|
||||
UINT f_fmt2_cond; \
|
||||
UINT f_a; \
|
||||
UINT f_op; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_TA_IMM_CODE \
|
||||
length = 4; \
|
||||
f_simm13 = EXTRACT_INT (insn, 32, 12, 13); \
|
||||
f_i = EXTRACT_UINT (insn, 32, 13, 1); \
|
||||
f_rs1 = EXTRACT_UINT (insn, 32, 18, 5); \
|
||||
f_op3 = EXTRACT_UINT (insn, 32, 24, 6); \
|
||||
f_fmt2_cond = EXTRACT_UINT (insn, 32, 28, 4); \
|
||||
f_a = EXTRACT_UINT (insn, 32, 29, 1); \
|
||||
f_op = EXTRACT_UINT (insn, 32, 31, 2); \
|
||||
|
||||
/* Collection of various things for the trace handler to use. */
|
||||
|
||||
typedef struct trace_record {
|
||||
IADDR pc;
|
||||
/* FIXME:wip */
|
||||
} TRACE_RECORD;
|
||||
|
||||
#endif /* CPU_SPARC32_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,285 @@
|
|||
/* Decode header for sparc32.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1999 Cygnus Solutions, Inc.
|
||||
|
||||
This file is part of the Cygnus Simulators.
|
||||
|
||||
|
||||
*/
|
||||
|
||||
#ifndef SPARC32_DECODE_H
|
||||
#define SPARC32_DECODE_H
|
||||
|
||||
extern const IDESC *sparc32_decode (SIM_CPU *, IADDR,
|
||||
CGEN_INSN_INT, CGEN_INSN_INT,
|
||||
ARGBUF *);
|
||||
extern void sparc32_init_idesc_table (SIM_CPU *);
|
||||
|
||||
/* Enum declaration for instructions in cpu family sparc32. */
|
||||
typedef enum sparc32_insn_type {
|
||||
SPARC32_INSN_X_INVALID, SPARC32_INSN_X_AFTER, SPARC32_INSN_X_BEFORE, SPARC32_INSN_X_CTI_CHAIN
|
||||
, SPARC32_INSN_X_CHAIN, SPARC32_INSN_X_BEGIN, SPARC32_INSN_RD_ASR, SPARC32_INSN_WR_ASR
|
||||
, SPARC32_INSN_WR_ASR_IMM, SPARC32_INSN_RD_PSR, SPARC32_INSN_WR_PSR, SPARC32_INSN_WR_PSR_IMM
|
||||
, SPARC32_INSN_RD_WIM, SPARC32_INSN_WR_WIM, SPARC32_INSN_WR_WIM_IMM, SPARC32_INSN_RD_TBR
|
||||
, SPARC32_INSN_WR_TBR, SPARC32_INSN_WR_TBR_IMM, SPARC32_INSN_LDSTUB_REG_REG, SPARC32_INSN_LDSTUB_REG_IMM
|
||||
, SPARC32_INSN_LDSTUB_REG_REG_ASI, SPARC32_INSN_SWAP_REG_REG, SPARC32_INSN_SWAP_REG_IMM, SPARC32_INSN_SWAP_REG_REG_ASI
|
||||
, SPARC32_INSN_LDSB_REG_REG, SPARC32_INSN_LDSB_REG_IMM, SPARC32_INSN_LDSB_REG_REG_ASI, SPARC32_INSN_LDUB_REG_REG
|
||||
, SPARC32_INSN_LDUB_REG_IMM, SPARC32_INSN_LDUB_REG_REG_ASI, SPARC32_INSN_LDSH_REG_REG, SPARC32_INSN_LDSH_REG_IMM
|
||||
, SPARC32_INSN_LDSH_REG_REG_ASI, SPARC32_INSN_LDUH_REG_REG, SPARC32_INSN_LDUH_REG_IMM, SPARC32_INSN_LDUH_REG_REG_ASI
|
||||
, SPARC32_INSN_LDSW_REG_REG, SPARC32_INSN_LDSW_REG_IMM, SPARC32_INSN_LDSW_REG_REG_ASI, SPARC32_INSN_LDUW_REG_REG
|
||||
, SPARC32_INSN_LDUW_REG_IMM, SPARC32_INSN_LDUW_REG_REG_ASI, SPARC32_INSN_LDD_REG_REG, SPARC32_INSN_LDD_REG_IMM
|
||||
, SPARC32_INSN_LDD_REG_REG_ASI, SPARC32_INSN_STB_REG_REG, SPARC32_INSN_STB_REG_IMM, SPARC32_INSN_STB_REG_REG_ASI
|
||||
, SPARC32_INSN_STH_REG_REG, SPARC32_INSN_STH_REG_IMM, SPARC32_INSN_STH_REG_REG_ASI, SPARC32_INSN_ST_REG_REG
|
||||
, SPARC32_INSN_ST_REG_IMM, SPARC32_INSN_ST_REG_REG_ASI, SPARC32_INSN_STD_REG_REG, SPARC32_INSN_STD_REG_IMM
|
||||
, SPARC32_INSN_STD_REG_REG_ASI, SPARC32_INSN_FP_LD_REG_REG, SPARC32_INSN_FP_LD_REG_IMM, SPARC32_INSN_FP_LD_REG_REG_ASI
|
||||
, SPARC32_INSN_SETHI, SPARC32_INSN_ADD, SPARC32_INSN_ADD_IMM, SPARC32_INSN_SUB
|
||||
, SPARC32_INSN_SUB_IMM, SPARC32_INSN_ADDCC, SPARC32_INSN_ADDCC_IMM, SPARC32_INSN_SUBCC
|
||||
, SPARC32_INSN_SUBCC_IMM, SPARC32_INSN_ADDX, SPARC32_INSN_ADDX_IMM, SPARC32_INSN_SUBX
|
||||
, SPARC32_INSN_SUBX_IMM, SPARC32_INSN_ADDXCC, SPARC32_INSN_ADDXCC_IMM, SPARC32_INSN_SUBXCC
|
||||
, SPARC32_INSN_SUBXCC_IMM, SPARC32_INSN_AND, SPARC32_INSN_AND_IMM, SPARC32_INSN_ANDCC
|
||||
, SPARC32_INSN_ANDCC_IMM, SPARC32_INSN_OR, SPARC32_INSN_OR_IMM, SPARC32_INSN_ORCC
|
||||
, SPARC32_INSN_ORCC_IMM, SPARC32_INSN_XOR, SPARC32_INSN_XOR_IMM, SPARC32_INSN_XORCC
|
||||
, SPARC32_INSN_XORCC_IMM, SPARC32_INSN_ANDN, SPARC32_INSN_ANDN_IMM, SPARC32_INSN_ANDNCC
|
||||
, SPARC32_INSN_ANDNCC_IMM, SPARC32_INSN_ORN, SPARC32_INSN_ORN_IMM, SPARC32_INSN_ORNCC
|
||||
, SPARC32_INSN_ORNCC_IMM, SPARC32_INSN_XNOR, SPARC32_INSN_XNOR_IMM, SPARC32_INSN_XNORCC
|
||||
, SPARC32_INSN_XNORCC_IMM, SPARC32_INSN_SLL, SPARC32_INSN_SLL_IMM, SPARC32_INSN_SRL
|
||||
, SPARC32_INSN_SRL_IMM, SPARC32_INSN_SRA, SPARC32_INSN_SRA_IMM, SPARC32_INSN_SMUL
|
||||
, SPARC32_INSN_SMUL_IMM, SPARC32_INSN_SMUL_CC, SPARC32_INSN_SMUL_CC_IMM, SPARC32_INSN_UMUL
|
||||
, SPARC32_INSN_UMUL_IMM, SPARC32_INSN_UMUL_CC, SPARC32_INSN_UMUL_CC_IMM, SPARC32_INSN_SDIV
|
||||
, SPARC32_INSN_SDIV_IMM, SPARC32_INSN_SDIV_CC, SPARC32_INSN_SDIV_CC_IMM, SPARC32_INSN_UDIV
|
||||
, SPARC32_INSN_UDIV_IMM, SPARC32_INSN_UDIV_CC, SPARC32_INSN_UDIV_CC_IMM, SPARC32_INSN_MULSCC
|
||||
, SPARC32_INSN_SAVE, SPARC32_INSN_SAVE_IMM, SPARC32_INSN_RESTORE, SPARC32_INSN_RESTORE_IMM
|
||||
, SPARC32_INSN_RETT, SPARC32_INSN_RETT_IMM, SPARC32_INSN_UNIMP, SPARC32_INSN_CALL
|
||||
, SPARC32_INSN_JMPL, SPARC32_INSN_JMPL_IMM, SPARC32_INSN_BA, SPARC32_INSN_TA
|
||||
, SPARC32_INSN_TA_IMM, SPARC32_INSN_BN, SPARC32_INSN_TN, SPARC32_INSN_TN_IMM
|
||||
, SPARC32_INSN_BNE, SPARC32_INSN_TNE, SPARC32_INSN_TNE_IMM, SPARC32_INSN_BE
|
||||
, SPARC32_INSN_TE, SPARC32_INSN_TE_IMM, SPARC32_INSN_BG, SPARC32_INSN_TG
|
||||
, SPARC32_INSN_TG_IMM, SPARC32_INSN_BLE, SPARC32_INSN_TLE, SPARC32_INSN_TLE_IMM
|
||||
, SPARC32_INSN_BGE, SPARC32_INSN_TGE, SPARC32_INSN_TGE_IMM, SPARC32_INSN_BL
|
||||
, SPARC32_INSN_TL, SPARC32_INSN_TL_IMM, SPARC32_INSN_BGU, SPARC32_INSN_TGU
|
||||
, SPARC32_INSN_TGU_IMM, SPARC32_INSN_BLEU, SPARC32_INSN_TLEU, SPARC32_INSN_TLEU_IMM
|
||||
, SPARC32_INSN_BCC, SPARC32_INSN_TCC, SPARC32_INSN_TCC_IMM, SPARC32_INSN_BCS
|
||||
, SPARC32_INSN_TCS, SPARC32_INSN_TCS_IMM, SPARC32_INSN_BPOS, SPARC32_INSN_TPOS
|
||||
, SPARC32_INSN_TPOS_IMM, SPARC32_INSN_BNEG, SPARC32_INSN_TNEG, SPARC32_INSN_TNEG_IMM
|
||||
, SPARC32_INSN_BVC, SPARC32_INSN_TVC, SPARC32_INSN_TVC_IMM, SPARC32_INSN_BVS
|
||||
, SPARC32_INSN_TVS, SPARC32_INSN_TVS_IMM, SPARC32_INSN_MAX
|
||||
} SPARC32_INSN_TYPE;
|
||||
|
||||
#if ! WITH_SEM_SWITCH_FULL
|
||||
#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,fn);
|
||||
#else
|
||||
#define SEMFULL(fn)
|
||||
#endif
|
||||
|
||||
#if ! WITH_SEM_SWITCH_FAST
|
||||
#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (sparc32,_semf_,fn);
|
||||
#else
|
||||
#define SEMFAST(fn)
|
||||
#endif
|
||||
|
||||
#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
|
||||
|
||||
/* The function version of the before/after handlers is always needed,
|
||||
so we always want the SEMFULL declaration of them. */
|
||||
extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,x_before);
|
||||
extern SEMANTIC_FN CONCAT3 (sparc32,_sem_,x_after);
|
||||
|
||||
SEM (x_invalid)
|
||||
SEM (x_after)
|
||||
SEM (x_before)
|
||||
SEM (x_cti_chain)
|
||||
SEM (x_chain)
|
||||
SEM (x_begin)
|
||||
SEM (rd_asr)
|
||||
SEM (wr_asr)
|
||||
SEM (wr_asr_imm)
|
||||
SEM (rd_psr)
|
||||
SEM (wr_psr)
|
||||
SEM (wr_psr_imm)
|
||||
SEM (rd_wim)
|
||||
SEM (wr_wim)
|
||||
SEM (wr_wim_imm)
|
||||
SEM (rd_tbr)
|
||||
SEM (wr_tbr)
|
||||
SEM (wr_tbr_imm)
|
||||
SEM (ldstub_reg_reg)
|
||||
SEM (ldstub_reg_imm)
|
||||
SEM (ldstub_reg_reg_asi)
|
||||
SEM (swap_reg_reg)
|
||||
SEM (swap_reg_imm)
|
||||
SEM (swap_reg_reg_asi)
|
||||
SEM (ldsb_reg_reg)
|
||||
SEM (ldsb_reg_imm)
|
||||
SEM (ldsb_reg_reg_asi)
|
||||
SEM (ldub_reg_reg)
|
||||
SEM (ldub_reg_imm)
|
||||
SEM (ldub_reg_reg_asi)
|
||||
SEM (ldsh_reg_reg)
|
||||
SEM (ldsh_reg_imm)
|
||||
SEM (ldsh_reg_reg_asi)
|
||||
SEM (lduh_reg_reg)
|
||||
SEM (lduh_reg_imm)
|
||||
SEM (lduh_reg_reg_asi)
|
||||
SEM (ldsw_reg_reg)
|
||||
SEM (ldsw_reg_imm)
|
||||
SEM (ldsw_reg_reg_asi)
|
||||
SEM (lduw_reg_reg)
|
||||
SEM (lduw_reg_imm)
|
||||
SEM (lduw_reg_reg_asi)
|
||||
SEM (ldd_reg_reg)
|
||||
SEM (ldd_reg_imm)
|
||||
SEM (ldd_reg_reg_asi)
|
||||
SEM (stb_reg_reg)
|
||||
SEM (stb_reg_imm)
|
||||
SEM (stb_reg_reg_asi)
|
||||
SEM (sth_reg_reg)
|
||||
SEM (sth_reg_imm)
|
||||
SEM (sth_reg_reg_asi)
|
||||
SEM (st_reg_reg)
|
||||
SEM (st_reg_imm)
|
||||
SEM (st_reg_reg_asi)
|
||||
SEM (std_reg_reg)
|
||||
SEM (std_reg_imm)
|
||||
SEM (std_reg_reg_asi)
|
||||
SEM (fp_ld_reg_reg)
|
||||
SEM (fp_ld_reg_imm)
|
||||
SEM (fp_ld_reg_reg_asi)
|
||||
SEM (sethi)
|
||||
SEM (add)
|
||||
SEM (add_imm)
|
||||
SEM (sub)
|
||||
SEM (sub_imm)
|
||||
SEM (addcc)
|
||||
SEM (addcc_imm)
|
||||
SEM (subcc)
|
||||
SEM (subcc_imm)
|
||||
SEM (addx)
|
||||
SEM (addx_imm)
|
||||
SEM (subx)
|
||||
SEM (subx_imm)
|
||||
SEM (addxcc)
|
||||
SEM (addxcc_imm)
|
||||
SEM (subxcc)
|
||||
SEM (subxcc_imm)
|
||||
SEM (and)
|
||||
SEM (and_imm)
|
||||
SEM (andcc)
|
||||
SEM (andcc_imm)
|
||||
SEM (or)
|
||||
SEM (or_imm)
|
||||
SEM (orcc)
|
||||
SEM (orcc_imm)
|
||||
SEM (xor)
|
||||
SEM (xor_imm)
|
||||
SEM (xorcc)
|
||||
SEM (xorcc_imm)
|
||||
SEM (andn)
|
||||
SEM (andn_imm)
|
||||
SEM (andncc)
|
||||
SEM (andncc_imm)
|
||||
SEM (orn)
|
||||
SEM (orn_imm)
|
||||
SEM (orncc)
|
||||
SEM (orncc_imm)
|
||||
SEM (xnor)
|
||||
SEM (xnor_imm)
|
||||
SEM (xnorcc)
|
||||
SEM (xnorcc_imm)
|
||||
SEM (sll)
|
||||
SEM (sll_imm)
|
||||
SEM (srl)
|
||||
SEM (srl_imm)
|
||||
SEM (sra)
|
||||
SEM (sra_imm)
|
||||
SEM (smul)
|
||||
SEM (smul_imm)
|
||||
SEM (smul_cc)
|
||||
SEM (smul_cc_imm)
|
||||
SEM (umul)
|
||||
SEM (umul_imm)
|
||||
SEM (umul_cc)
|
||||
SEM (umul_cc_imm)
|
||||
SEM (sdiv)
|
||||
SEM (sdiv_imm)
|
||||
SEM (sdiv_cc)
|
||||
SEM (sdiv_cc_imm)
|
||||
SEM (udiv)
|
||||
SEM (udiv_imm)
|
||||
SEM (udiv_cc)
|
||||
SEM (udiv_cc_imm)
|
||||
SEM (mulscc)
|
||||
SEM (save)
|
||||
SEM (save_imm)
|
||||
SEM (restore)
|
||||
SEM (restore_imm)
|
||||
SEM (rett)
|
||||
SEM (rett_imm)
|
||||
SEM (unimp)
|
||||
SEM (call)
|
||||
SEM (jmpl)
|
||||
SEM (jmpl_imm)
|
||||
SEM (ba)
|
||||
SEM (ta)
|
||||
SEM (ta_imm)
|
||||
SEM (bn)
|
||||
SEM (tn)
|
||||
SEM (tn_imm)
|
||||
SEM (bne)
|
||||
SEM (tne)
|
||||
SEM (tne_imm)
|
||||
SEM (be)
|
||||
SEM (te)
|
||||
SEM (te_imm)
|
||||
SEM (bg)
|
||||
SEM (tg)
|
||||
SEM (tg_imm)
|
||||
SEM (ble)
|
||||
SEM (tle)
|
||||
SEM (tle_imm)
|
||||
SEM (bge)
|
||||
SEM (tge)
|
||||
SEM (tge_imm)
|
||||
SEM (bl)
|
||||
SEM (tl)
|
||||
SEM (tl_imm)
|
||||
SEM (bgu)
|
||||
SEM (tgu)
|
||||
SEM (tgu_imm)
|
||||
SEM (bleu)
|
||||
SEM (tleu)
|
||||
SEM (tleu_imm)
|
||||
SEM (bcc)
|
||||
SEM (tcc)
|
||||
SEM (tcc_imm)
|
||||
SEM (bcs)
|
||||
SEM (tcs)
|
||||
SEM (tcs_imm)
|
||||
SEM (bpos)
|
||||
SEM (tpos)
|
||||
SEM (tpos_imm)
|
||||
SEM (bneg)
|
||||
SEM (tneg)
|
||||
SEM (tneg_imm)
|
||||
SEM (bvc)
|
||||
SEM (tvc)
|
||||
SEM (tvc_imm)
|
||||
SEM (bvs)
|
||||
SEM (tvs)
|
||||
SEM (tvs_imm)
|
||||
|
||||
#undef SEMFULL
|
||||
#undef SEMFAST
|
||||
#undef SEM
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int sparc32_model_sparc32_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void sparc32_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void sparc32_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* SPARC32_DECODE_H */
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* sparc64 device support
|
||||
Copyright (C) 1999 Cygnus Solutions. */
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "dev64.h"
|
||||
|
||||
#ifdef HAVE_DV_SOCKSER
|
||||
#include "dv-sockser.h"
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* sparc64 device support
|
||||
Copyright (C) 1999 Cygnus Solutions. */
|
||||
|
||||
#ifndef DEV64_H
|
||||
#define DEV64_H
|
||||
|
||||
/* From libgloss/sparc/erc32-io.c. */
|
||||
|
||||
#define ERC32_DEVICE_ADDR 0x1f80000
|
||||
#define ERC32_DEVICE_LEN (0x2000000 - 0x1f80000)
|
||||
|
||||
#define RXADATA 0x01F800E0
|
||||
#define RXBDATA 0x01F800E4
|
||||
#define RXSTAT 0x01F800E8
|
||||
|
||||
extern device sparc_devices;
|
||||
|
||||
/* FIXME: Temporary, until device support ready. */
|
||||
struct _device { int foo; };
|
||||
|
||||
#endif /* DEV64_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,264 @@
|
|||
/* sparc64 simulator support code
|
||||
Copyright (C) 1999 Cygnus Solutions. */
|
||||
|
||||
#define WANT_CPU_SPARC64
|
||||
|
||||
#include "sim-main.h"
|
||||
#include <signal.h>
|
||||
#include "libiberty.h"
|
||||
#include "bfd.h"
|
||||
#include "cgen-mem.h"
|
||||
#include "cgen-ops.h"
|
||||
#include "targ-vals.h"
|
||||
#include "trap64.h"
|
||||
|
||||
/* Initialize the program counter. */
|
||||
|
||||
void
|
||||
sparc64_init_pc (SIM_CPU *current_cpu, DI pc, DI npc)
|
||||
{
|
||||
SET_H_PC (pc);
|
||||
SET_H_NPC (npc);
|
||||
}
|
||||
|
||||
#if WITH_PROFILE_MODEL_P
|
||||
|
||||
void
|
||||
sparc64_model_mark_get_h_gr (SIM_CPU *cpu, SPARC64_ARGBUF *abuf)
|
||||
{
|
||||
if ((CPU_PROFILE_STATE (cpu)->h_gr & abuf->h_gr_get) != 0)
|
||||
{
|
||||
PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2;
|
||||
if (TRACE_INSN_P (cpu))
|
||||
cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_model_mark_set_h_gr (SIM_CPU *cpu, SPARC64_ARGBUF *abuf)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_model_mark_busy_reg (SIM_CPU *cpu, SPARC64_ARGBUF *abuf)
|
||||
{
|
||||
CPU_PROFILE_STATE (cpu)->h_gr = abuf->h_gr_set;
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_model_mark_unbusy_reg (SIM_CPU *cpu, SPARC64_ARGBUF *abuf)
|
||||
{
|
||||
CPU_PROFILE_STATE (cpu)->h_gr = 0;
|
||||
}
|
||||
|
||||
#endif /* WITH_PROFILE_MODEL_P */
|
||||
|
||||
UDI
|
||||
sparc64_h_gr_get (SIM_CPU *current_cpu, unsigned int regno)
|
||||
{
|
||||
return GET_INT_REG (cpu, regno);
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_h_gr_set (SIM_CPU *current_cpu, unsigned int regno, UDI new_val)
|
||||
{
|
||||
SET_INT_REG (cpu, regno, new_val);
|
||||
}
|
||||
|
||||
DI *
|
||||
sparc64_h_gr_regno_get_addr (SIM_CPU *current_cpu, int regno)
|
||||
{
|
||||
}
|
||||
|
||||
DI
|
||||
sparc64_h_gr_regno_get (SIM_CPU *current_cpu, int regno)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_h_gr_regno_set (SIM_CPU *current_cpu, int regno, DI new_val)
|
||||
{
|
||||
}
|
||||
|
||||
DI
|
||||
sparc64_do_save (SIM_CPU *current_cpu, DI rs1, DI rs2_simm13)
|
||||
{
|
||||
DI rd;
|
||||
|
||||
/* If this is a user program, watch for stack overflow ... */
|
||||
|
||||
#if 0
|
||||
if (STATE_user_prog && GET_AREG (GET_REG (REG_SP)) < mem_end)
|
||||
{
|
||||
if (user_prog)
|
||||
fprintf (stderr, "sim: stack space exhausted!\n");
|
||||
sim_signal (SIM_SIGACCESS);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (GET_CANSAVE (current_cpu) == 0)
|
||||
{
|
||||
return trap (TRAP_SPILL);
|
||||
}
|
||||
if (GET_CLEANWIN (current_cpu) - GET_CANRESTORE (current_cpu) == 0)
|
||||
{
|
||||
return trap (TRAP_CLEAN_WINDOW);
|
||||
}
|
||||
|
||||
/* The calculation is done using the old window's values
|
||||
[those passed in to us]. */
|
||||
|
||||
rd = ADDDI (rs1, rs2_simm13);
|
||||
|
||||
/* Switch to a new window. */
|
||||
|
||||
save_window ();
|
||||
|
||||
return rd;
|
||||
}
|
||||
|
||||
DI
|
||||
sparc64_do_restore (SIM_CPU *current_cpu, DI rs1, DI rs2_simm13)
|
||||
{
|
||||
DI rd;
|
||||
|
||||
return rd;
|
||||
|
||||
}
|
||||
|
||||
/* Initialize the register window mechanism. */
|
||||
|
||||
void
|
||||
sparc64_alloc_register_windows (SIM_CPU *cpu, int nwindows)
|
||||
{
|
||||
int ag,i,r,w;
|
||||
DI *(*v)[32];
|
||||
|
||||
cpu->greg_lookup_table = (DI *(*)[2][32]) xmalloc (nwindows * 2 * 32 * sizeof (void *));
|
||||
cpu->globals = (DI (*)[][8]) zalloc (2 * 8 * sizeof (DI));
|
||||
cpu->win_regs = (DI (*)[][16]) zalloc (nwindows * 16 * sizeof (DI));
|
||||
|
||||
v = &cpu->greg_lookup_table[0][0];
|
||||
for (w = 0; w < nwindows; w++)
|
||||
{
|
||||
for (ag = 0; ag < 2; ag++, v++)
|
||||
{
|
||||
/* Initialize pointers to the global registers ... */
|
||||
for (r = 0; r < 8; r++)
|
||||
(*v)[r] = &cpu->globals[ag][r];
|
||||
|
||||
/* Initialize pointers to the output registers ... */
|
||||
for (r = 0; r < 8; r++)
|
||||
(*v)[r + 8] = &cpu->win_regs[(w == nwindows - 1 ? 0 : ((w + 1) * 16)) + r];
|
||||
|
||||
/* Initialize pointers to the local registers ... */
|
||||
for (r = 0; r < 8; r++)
|
||||
(*v)[r + 16] = &cpu->win_regs[(w * 16) + 8 + r];
|
||||
|
||||
/* Initialize pointers to the input registers ... */
|
||||
for (r = 0; r < 8; r++)
|
||||
(*v)[r + 24] = &cpu->win_regs[(w * 16) + r];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_free_register_windows (SIM_CPU *cpu)
|
||||
{
|
||||
free (cpu->win_regs);
|
||||
cpu->win_regs = NULL;
|
||||
free (cpu->globals);
|
||||
cpu->globals = NULL;
|
||||
free (cpu->greg_lookup_table);
|
||||
cpu->greg_lookup_table = NULL;
|
||||
}
|
||||
|
||||
/* Assign a new value to CWP.
|
||||
|
||||
The register windows are recorded in a seemingly backwards manner.
|
||||
%i0-7 live at lower addresses in memory than %o0-7 (even though they
|
||||
have higher register numbers). This is because the stack grows upwards
|
||||
in the sense that CWP increases during a "push" operation.
|
||||
|
||||
FIXME: True for v9, but also for v8? */
|
||||
|
||||
void
|
||||
sparc64_set_cwp (SIM_CPU *current_cpu, int x)
|
||||
{
|
||||
if (x < 0 || x >= GET_NWINDOWS (cpu))
|
||||
abort ();
|
||||
|
||||
/* We can't use SET_CWP here because it uses us. */
|
||||
|
||||
cpu->cgen_cpu.cpu.h_cwp = x;
|
||||
|
||||
cpu->current_greg_lookup_table = &cpu->greg_lookup_table[x][GET_AG (cpu)][0];
|
||||
}
|
||||
|
||||
/* Create a new window. We assume there is room.
|
||||
|
||||
WARNING: The following must always be true:
|
||||
|
||||
CANSAVE + CANRESTORE + OTHERWIN == NWINDOWS - 2
|
||||
|
||||
We only watch for this during saves. */
|
||||
|
||||
void
|
||||
sparc64_save_window (SIM_CPU *current_cpu)
|
||||
{
|
||||
if (GET_CANSAVE (cpu) + GET_CANRESTORE (cpu) + GET_OTHERWIN (cpu) != GET_NWINDOWS (cpu) - 2)
|
||||
abort ();
|
||||
|
||||
SET_CWP (cpu, ROUND_WIN (GET_CWP (cpu) + 1));
|
||||
SET_CANSAVE (cpu, ROUND_WIN (GET_CANSAVE (cpu) - 1));
|
||||
SET_CANRESTORE (cpu, ROUND_WIN (GET_CANRESTORE (cpu) + 1));
|
||||
}
|
||||
|
||||
/* Pop a window. We assume no traps possible. */
|
||||
|
||||
void
|
||||
sparc64_restore_window (SIM_CPU *current_cpu)
|
||||
{
|
||||
SET_CWP (cpu, ROUND_WIN (GET_CWP (cpu) - 1));
|
||||
SET_CANSAVE (cpu, ROUND_WIN (GET_CANSAVE (cpu) + 1));
|
||||
SET_CANRESTORE (cpu, ROUND_WIN (GET_CANRESTORE (cpu) - 1));
|
||||
}
|
||||
|
||||
/* Flush the register windows to memory.
|
||||
This is necessary, for example, when we want to walk the stack in gdb.
|
||||
|
||||
We use restore_window() and save_window() to traverse the register windows.
|
||||
This is the cleanest and simplest thing to do. */
|
||||
|
||||
void
|
||||
sparc64_flush_windows (SIM_CPU *cpu)
|
||||
{
|
||||
int i,count = GET_CANRESTORE (cpu) + 1;
|
||||
|
||||
/* Save the register windows, changing the current one as we go ... */
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
{
|
||||
AI sp = GET_INT_REG (cpu, REG_SP) /*+ stack_bias*/;
|
||||
flush_one_window (cpu, sp, CURRENT_LREGS (cpu), CURRENT_IREGS (cpu));
|
||||
if (i + 1 != count) /* don't restore window if there isn't one */
|
||||
restore_window (cpu);
|
||||
}
|
||||
|
||||
/* Restore the window state ... */
|
||||
|
||||
for (i = 1; i < count; i++)
|
||||
save_window (cpu);
|
||||
}
|
||||
|
||||
void
|
||||
sparc64_flush_one_window (SIM_CPU *current_cpu, AI addr, DI *lregs, DI *iregs)
|
||||
{
|
||||
sim_core_write_buffer (CPU_STATE (cpu), cpu,
|
||||
sim_core_write_map,
|
||||
lregs, addr, 8 * sizeof (DI));
|
||||
sim_core_write_buffer (CPU_STATE (cpu), cpu,
|
||||
sim_core_write_map,
|
||||
iregs, addr + 8 * sizeof (DI), 8 * sizeof (DI));
|
||||
}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* sparc64 trap definitions
|
||||
Copyright (C) 1999 Cygnus Solutions. */
|
||||
|
||||
#ifndef TRAP64_H
|
||||
#define TRAP64_H
|
||||
|
||||
/* D1.2.4 page 107 */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TRAP64_POWER_ON_RESET = 1,
|
||||
TRAP64_WATCHDOG_RESET = 2,
|
||||
TRAP64_EXTERNALLY_INITIATED_RESET = 3,
|
||||
TRAP64_SOFTWARE_INITIATED_RESET = 4,
|
||||
TRAP64_RED_STATE_EXCEPTION = 5,
|
||||
TRAP64_INSN_ACCESS_EXCEPTION = 8,
|
||||
TRAP64_INSN_ACCESS_MMU_MISS = 9,
|
||||
TRAP64_INSN_ACCESS_ERROR = 10,
|
||||
TRAP64_ILLEGAL_INSN = 16,
|
||||
TRAP64_PRIVILEDGED_OPCODE = 17,
|
||||
TRAP64_UNIMPLEMENTED_LDD = 18,
|
||||
TRAP64_UNIMPLEMENTED_STD = 19,
|
||||
TRAP64_FP_DISABLED = 32,
|
||||
TRAP64_FP_EXCEPTION_IEEE_754 = 33,
|
||||
TRAP64_FP_EXCEPTION_OTHER = 34,
|
||||
TRAP64_TAG_OVERFLOW = 35,
|
||||
TRAP64_CLEAN_WINDOW = 36,
|
||||
TRAP64_DIVISION_BY_ZERO = 40,
|
||||
TRAP64_INTERNAL_PROCESSOR_ERROR = 41,
|
||||
TRAP64_DATA_ACCESS_EXCEPTION = 48,
|
||||
TRAP64_DATA_ACCESS_MMU_MISS = 49,
|
||||
TRAP64_DATA_ACCESS_ERROR = 50,
|
||||
TRAP64_DATA_ACCESS_PROTECTION = 51,
|
||||
TRAP64_MEM_ADDRESS_NOT_ALIGNED = 52,
|
||||
TRAP64_LDDF_MEM_ADDRESS_NOT_ALIGNED = 53, /* impdep # 109 */
|
||||
TRAP64_STDF_MEM_ADDRESS_NOT_ALIGNED = 54, /* impdep # 110 */
|
||||
TRAP64_PRIVILEDGED_ACTION = 55,
|
||||
TRAP64_LDQF_MEM_ADDRESS_NOT_ALIGNED = 56, /* impdep # 111 */
|
||||
TRAP64_STQF_MEM_ADDRESS_NOT_ALIGNED = 57, /* impdep # 112 */
|
||||
TRAP64_ASYNC_DATA_ERROR = 64,
|
||||
TRAP64_INTERRUPT_LEVEL_0 = 65, /* n = 1..15 */
|
||||
TRAP64_IMPDEP_EXCEPTION_0 = 96, /* n = 0..31 */
|
||||
|
||||
/* IMPDEP codes used by the simulator in ENVIRONMENT_USER. */
|
||||
TRAP64_SIM_UNIMPLEMENTED_OPCODE = 124,
|
||||
TRAP64_SIM_RESERVED_INSN = 125,
|
||||
TRAP64_SIM_SPILL = 126,
|
||||
TRAP64_SIM_FILL = 127,
|
||||
|
||||
TRAP64_SPILL_0_NORMAL = 128, /* n = 0..7 */
|
||||
TRAP64_SPILL_0_OTHER = 160, /* n = 0..7 */
|
||||
TRAP64_FILL_0_NORMAL = 192, /* n = 0..7 */
|
||||
TRAP64_FILL_0_OTHER = 224, /* n = 0..7 */
|
||||
TRAP64_INSTRUCTION = 256, /* n = 0..127 */
|
||||
TRAP64_BREAKPOINT = 257, /* convention */
|
||||
TRAP64_MAX = 0x17f
|
||||
} TRAP64_TYPE;
|
||||
|
||||
#define MAX_NUM_TRAPS 1024
|
||||
|
||||
#define TRAP64_TABLE_SIZE (32 * MAX_NUM_TRAPS) /* in bytes */
|
||||
|
||||
/* We record the fact that the cpu is in error state by setting TL to be
|
||||
something greater than MAXTL, usually MAXTL+1. */
|
||||
|
||||
#define ERROR_STATE_P() (GET_TL () > MAXTL)
|
||||
|
||||
#if 0
|
||||
fastint trap (trap_type_e);
|
||||
int trap_priority (trap_type_e);
|
||||
|
||||
fastint reserved (void);
|
||||
fastint deprecated (void);
|
||||
fastint not_impl (void);
|
||||
fastint illegal (void);
|
||||
fastint priviledged (void);
|
||||
fastint unimp_fpop (void);
|
||||
fastint fp_disabled (void);
|
||||
|
||||
/* When running user level programs, we supply all the necessary trap handlers.
|
||||
These handlers run on the host, not in the emulation environment. */
|
||||
|
||||
typedef fastint (trap_handler_t) (void);
|
||||
#endif
|
||||
|
||||
#endif /* TRAP64_H */
|
||||
Loading…
Reference in New Issue