gas/:
* config/bfin-parse.y (check_macfunc_option): New. (check_macfuncs): Check option by calling check_macfunc_option. Fix comparison always true warnings. Both scalar instructions of vector instruction must share the same mode option. Only allow option mode at the end of the second instruction of the vector. (asm_1): Check option by calling check_macfunc_option. gas/testsuite/: * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add tests for bad options of "multiply and multipy-accumulate to accumulator" instructions. Add new vector instruction option mode tests. * gas/bfin/vector2.s: Add new vector instruction option mode test. * gas/bfin/vector2.d: Adjust accordingly. * gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test for mismatched half registers in vector multipy-accumulate instructions.
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@ -2,8 +2,14 @@
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From Jie Zhang <jie.zhang@analog.com>
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From Jie Zhang <jie.zhang@analog.com>
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* config/bfin-parse.y (asm_1): Check AREGS in comparison
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* config/bfin-parse.y (asm_1): Check AREGS in comparison
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instructions. And call yyerror () when comparing PREG with
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instructions. And call yyerror when comparing PREG with
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DREG.
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DREG.
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(check_macfunc_option): New.
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(check_macfuncs): Check option by calling check_macfunc_option.
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Fix comparison always true warnings. Both scalar instructions
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of vector instruction must share the same mode option. Only allow
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option mode at the end of the second instruction of the vector.
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(asm_1): Check option by calling check_macfunc_option.
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2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
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2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
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@ -264,6 +264,35 @@ check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
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}
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}
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/* Check mac option. */
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static int
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check_macfunc_option (Macfunc *a, Opt_mode *opt)
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{
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/* Default option is always valid. */
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if (opt->mod == 0)
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return 0;
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if ((a->op == 3 && a->w == 1 && a->P == 1
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&& opt->mod != M_FU && opt->mod != M_S2RND && opt->mod != M_ISS2)
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|| (a->op == 3 && a->w == 1 && a->P == 0
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&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
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&& opt->mod != M_T && opt->mod != M_S2RND && opt->mod != M_ISS2
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&& opt->mod != M_IH)
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|| (a->w == 0 && a->P == 0
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&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32)
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|| (a->w == 1 && a->P == 1
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&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_S2RND
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&& opt->mod != M_ISS2)
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|| (a->w == 1 && a->P == 0
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&& opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
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&& opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
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&& opt->mod != M_ISS2 && opt->mod != M_IH))
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return -1;
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return 0;
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}
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/* Check (vector) mac funcs and ops. */
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/* Check (vector) mac funcs and ops. */
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static int
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static int
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@ -274,6 +303,11 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
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Macfunc mtmp;
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Macfunc mtmp;
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Opt_mode otmp;
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Opt_mode otmp;
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/* The option mode should be put at the end of the second instruction
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of the vector except M, which should follow MAC1 instruction. */
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if (opa->mod != 0)
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return yyerror ("Bad opt mode");
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/* If a0macfunc comes before a1macfunc, swap them. */
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/* If a0macfunc comes before a1macfunc, swap them. */
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if (aa->n == 0)
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if (aa->n == 0)
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@ -291,16 +325,14 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
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{
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{
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if (opb->MM != 0)
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if (opb->MM != 0)
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return yyerror ("(M) not allowed with A0MAC");
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return yyerror ("(M) not allowed with A0MAC");
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if (opa->mod != 0)
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return yyerror ("Bad opt mode");
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if (ab->n != 0)
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if (ab->n != 0)
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return yyerror ("Vector AxMACs can't be same");
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return yyerror ("Vector AxMACs can't be same");
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}
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}
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/* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
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/* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
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assignment_or_macfuncs. */
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assignment_or_macfuncs. */
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if (aa->op < 3 && aa->op >=0
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if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
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&& ab->op < 3 && ab->op >= 0)
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&& (ab->op == 0 || ab->op == 1 || ab->op == 2))
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{
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{
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if (check_multiply_halfregs (aa, ab) < 0)
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if (check_multiply_halfregs (aa, ab) < 0)
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return -1;
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return -1;
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@ -330,11 +362,17 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
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|| (ab->w && !aa->P && IS_H (ab->dst)))
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|| (ab->w && !aa->P && IS_H (ab->dst)))
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return yyerror ("High/Low register assignment mismatch");
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return yyerror ("High/Low register assignment mismatch");
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/* Make sure mod flags get ORed, too. */
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opb->mod |= opa->mod;
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/* Check option. */
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if (check_macfunc_option (aa, opb) < 0
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&& check_macfunc_option (ab, opb) < 0)
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return yyerror ("bad option");
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/* Make sure first macfunc has got both P flags ORed. */
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/* Make sure first macfunc has got both P flags ORed. */
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aa->P |= ab->P;
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aa->P |= ab->P;
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/* Make sure mod flags get ORed, too. */
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opb->mod |= opa->mod;
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return 0;
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return 0;
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}
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}
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@ -660,6 +698,9 @@ asm_1:
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int w0 = 0, w1 = 0;
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int w0 = 0, w1 = 0;
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int h00, h10, h01, h11;
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int h00, h10, h01, h11;
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if (check_macfunc_option (&$1, &$2) < 0)
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return yyerror ("bad option");
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if ($1.n == 0)
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if ($1.n == 0)
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{
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{
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if ($2.MM)
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if ($2.MM)
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@ -5,6 +5,17 @@
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* gas/bfin/expected_comparison_errors.l: New test.
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* gas/bfin/expected_comparison_errors.l: New test.
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* gas/bfin/expected_comparison_errors.s: New test.
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* gas/bfin/expected_comparison_errors.s: New test.
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* gas/bfin/bfin.exp: Add expected_comparison_errors.
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* gas/bfin/bfin.exp: Add expected_comparison_errors.
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* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add
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tests for bad options of "multiply and multipy-accumulate to
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accumulator" instructions. Add new vector instruction option
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mode tests.
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* gas/bfin/vector2.s: Add new vector instruction option mode test.
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* gas/bfin/vector2.d: Adjust accordingly.
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From Mike Frysinger <michael.frysinger@analog.com>
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* gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test
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for mismatched half registers in vector multipy-accumulate
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instructions.
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2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
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2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
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@ -8,3 +8,12 @@
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.*:10: Error: Bad constant value.
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.*:10: Error: Bad constant value.
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.*:11: Error: Bad constant value.
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.*:11: Error: Bad constant value.
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.*:13: Error: Dregs expected. Input text was R3.L.
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.*:13: Error: Dregs expected. Input text was R3.L.
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.*:15: Error: Source multiplication register mismatch. Input text was \).
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.*:17: Error: bad option.
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.*:18: Error: bad option.
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.*:19: Error: bad option.
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.*:20: Error: bad option.
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.*:21: Error: bad option.
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.*:22: Error: bad option.
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.*:23: Error: Bad opt mode.
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.*:24: Error: Bad opt mode.
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@ -11,3 +11,14 @@
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CC = R3 <= 8;
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CC = R3 <= 8;
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A1 -= M2.h * R3.L, A0 -= M2.l * R3.L;
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A1 -= M2.h * R3.L, A0 -= M2.l * R3.L;
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R1.H = (A1=R7.L*R5.L) , A0 += R1.L*R0.L (IS);
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a0 += R2.L * R3.L (IU);
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a0 += R2.L * R3.L (T);
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a0 += R2.L * R3.L (TFU);
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a0 += R2.L * R3.L (S2RND);
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a0 += R2.L * R3.L (ISS2);
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a0 += R2.L * R3.L (IH);
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R0.H = (A1 = R4.L * R3.L) (T), A0 = R4.H * R3.L;
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R0.L = (A0 = R7.L * R4.H) (T), A1 += R7.H * R4.H;
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@ -472,3 +472,8 @@ Disassembly of section .text:
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740: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L;
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740: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L;
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744: 1c c2 b8 60 R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L;
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744: 1c c2 b8 60 R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L;
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748: 1c c0 b8 60 R3 = \(a1 = R7.L \* R0.H\) \(M\), R2 = \(a0 = R7.L \* R0.L\);
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748: 1c c0 b8 60 R3 = \(a1 = R7.L \* R0.H\) \(M\), R2 = \(a0 = R7.L \* R0.L\);
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74c: 44 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\), a0 = R4.H \* R3.L \(T\);
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750: 54 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\) \(M\), a0 = R4.H \* R3.L \(T\);
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754: 44 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\), a0 = R4.H \* R3.L \(T\);
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758: 54 c0 23 04 R0.H = \(a1 = R4.L \* R3.L\) \(M\), a0 = R4.H \* R3.L \(T\);
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75c: 41 c0 3c e2 a1 \+= R7.H \* R4.H, R0.L = \(a0 = R7.L \* R4.H\) \(T\);
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@ -671,3 +671,10 @@ r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */
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r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;
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r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;
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R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);
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R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);
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R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);
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R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);
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/* Both scalar instructions must share the same mode option. */
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R0.H = (A1 = R4.L * R3.L), A0 = R4.H * R3.L (T);
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R0.H = (A1 = R4.L * R3.L) (M), A0 = R4.H * R3.L (T);
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A0 = R4.H * R3.L, R0.H = (A1 = R4.L * R3.L) (T);
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A0 = R4.H * R3.L, R0.H = (A1 = R4.L * R3.L) (T,M);
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A1 += R7.H * R4.H, R0.L = (A0 = R7.L * R4.H) (T);
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