x86: allow VEX et al encodings in 16-bit (protected) mode
These encodings aren't valid in real and VM86 modes, but they are very well usable in 16-bit protected mode. A few adjustments in the disassembler tables are needed where Ev or Gv were wrongly used. Additionally an adjustment is needed to avoid printing "addr32" when that's already recognizable by the use of %eiz. Furthermore the Iq operand template was wrong for XOP:0Ah encoding insns: They're having a uniform 32-bit immediate. Drop Iq and introduce Id instead. Clone a few existing test cases to exercise assembler and disassembler.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
65bd27298d
commit
c1dc7af521
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@ -1,3 +1,21 @@
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2019-06-27 Jan Beulich <jbeulich@suse.com>
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config/tc-i386.c (md_assemble): Check for protected mode
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incapable processor before encoding VEX and alike insns.
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* testsuite/gas/i386/inval-16.s: For 80186 architecture.
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* testsuite/gas/i386/inval-16.l: Adjust expectations.
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* testsuite/gas/i386/avx-16bit.d,
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testsuite/gas/i386/avx-16bit.s,
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testsuite/gas/i386/avx512f-16bit.d,
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testsuite/gas/i386/avx512f-16bit.s,
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testsuite/gas/i386/bmi-16bit.d,
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testsuite/gas/i386/bmi-16bit.s,
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testsuite/gas/i386/bmi2-16bit.d,
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testsuite/gas/i386/bmi2-16bit.s,
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testsuite/gas/i386/lwp-16bit.d,
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testsuite/gas/i386/lwp-16bit.s: New
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testsuite/gas/i386/i386.exp: Run new tests.
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2019-06-26 Jim Wilson <jimw@sifive.com>
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* testsuite/gas/xstormy16/allinsn.sh: Change first line to
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@ -4388,9 +4388,9 @@ md_assemble (char *line)
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if (is_any_vex_encoding (&i.tm))
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{
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if (flag_code == CODE_16BIT)
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if (!cpu_arch_flags.bitfield.cpui286)
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{
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as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
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as_bad (_("instruction `%s' isn't supported outside of protected mode."),
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i.tm.name);
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return;
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,7 @@
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# Check AVX instructions in 16-bit mode
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.code16
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.include "avx.s"
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.att_syntax prefix
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vaddps (%bx),%ymm6,%ymm2
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,4 @@
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# Check AVX512F instructions in 16-bit mode
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.code16
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.include "avx512f.s"
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@ -0,0 +1,46 @@
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#as: -I${srcdir}/$subdir
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#objdump: -dwMaddr16 -Mdata16
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#name: i386 16-bit BMI
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %ax,%bx
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[ ]*[a-f0-9]+: 67 f3 0f bc 19 tzcnt \(%ecx\),%bx
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[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %eax,%ebx
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[ ]*[a-f0-9]+: 67 66 f3 0f bc 19 tzcnt \(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 19 blsi \(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 09 blsr \(%ecx\),%ebx
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[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %ax,%bx
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[ ]*[a-f0-9]+: 67 f3 0f bc 19 tzcnt \(%ecx\),%bx
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[ ]*[a-f0-9]+: 67 f3 0f bc 19 tzcnt \(%ecx\),%bx
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[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %eax,%ebx
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[ ]*[a-f0-9]+: 67 66 f3 0f bc 19 tzcnt \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 67 66 f3 0f bc 19 tzcnt \(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 19 blsi \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 19 blsi \(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 09 blsr \(%ecx\),%ebx
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[ ]*[a-f0-9]+: 67 c4 e2 60 f3 09 blsr \(%ecx\),%ebx
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#pass
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@ -0,0 +1,4 @@
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# Check 16-bit BMI instructions
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.code16
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.include "bmi.s"
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@ -0,0 +1,51 @@
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#as: -I${srcdir}/$subdir
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#objdump: -dwMaddr16 -Mdata16
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#name: i386 16-bit BMI2
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: c4 e3 7b f0 d8 07 rorx \$0x7,%eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e3 7b f0 19 07 rorx \$0x7,\(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 63 f6 f0 mulx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f6 31 mulx \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 63 f5 f0 pdep %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f5 31 pdep \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 62 f5 f0 pext %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 62 f5 31 pext \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 78 f5 f3 bzhi %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f5 31 bzhi %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e3 7b f0 d8 07 rorx \$0x7,%eax,%ebx
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[ ]*[a-f0-9]+: 67 c4 e3 7b f0 19 07 rorx \$0x7,\(%ecx\),%ebx
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[ ]*[a-f0-9]+: 67 c4 e3 7b f0 19 07 rorx \$0x7,\(%ecx\),%ebx
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[ ]*[a-f0-9]+: c4 e2 63 f6 f0 mulx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f6 31 mulx \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f6 31 mulx \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 63 f5 f0 pdep %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f5 31 pdep \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f5 31 pdep \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 62 f5 f0 pext %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 62 f5 31 pext \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 62 f5 31 pext \(%ecx\),%ebx,%esi
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[ ]*[a-f0-9]+: c4 e2 78 f5 f3 bzhi %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f5 31 bzhi %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 67 c4 e2 60 f5 31 bzhi %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 67 c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 67 c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx %eax,%ebx,%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 67 c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
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#pass
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@ -0,0 +1,4 @@
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# Check 16-bit BMI2 instructions
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.code16
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.include "bmi2.s"
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@ -209,6 +209,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "avx-scalar"
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run_dump_test "avx-scalar-intel"
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run_dump_test "avx-scalar-2"
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run_dump_test "avx-16bit"
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run_dump_test "avx256int"
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run_dump_test "avx256int-intel"
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run_dump_test "avx2"
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@ -225,6 +226,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "avx512f-nondef"
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run_list_test "avx512f-plain" "-al"
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run_dump_test "avx512f-ymm"
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run_dump_test "avx512f-16bit"
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run_dump_test "avx512cd"
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run_dump_test "avx512cd-intel"
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run_dump_test "avx512er"
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@ -276,6 +278,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "sse2avx-opts-intel"
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run_dump_test "bmi2"
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run_dump_test "bmi2-intel"
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run_dump_test "bmi2-16bit"
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run_dump_test "fma"
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run_dump_test "fma-intel"
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run_dump_test "fma-scalar"
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@ -287,12 +290,15 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "rtm-intel"
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run_dump_test "fma4"
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run_dump_test "lwp"
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run_dump_test "lwp-16bit"
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run_dump_test "xop"
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run_dump_test "xop32reg"
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run_dump_test "bmi"
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run_dump_test "bmi-intel"
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run_dump_test "bmi-16bit"
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run_dump_test "tbm"
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run_dump_test "tbm-intel"
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run_dump_test "tbm-16bit"
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run_dump_test "f16c"
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run_dump_test "f16c-intel"
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run_dump_test "fsgs"
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@ -10,7 +10,7 @@ GAS LISTING .*
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[ ]*1[ ]+\.text
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[ ]*2[ ]+\.code16
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[ ]*2[ ]+\.arch i186; \.code16
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[ ]*3[ ]+vmovapd %xmm0,%xmm1
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[ ]*4[ ]+vaddsd %xmm4, %xmm5, %xmm6\{%k7\}
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[ ]*5[ ]+vfrczpd %xmm7,%xmm7
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@ -1,5 +1,5 @@
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.text
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.code16
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.arch i186; .code16
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vmovapd %xmm0,%xmm1
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vaddsd %xmm4, %xmm5, %xmm6{%k7}
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vfrczpd %xmm7,%xmm7
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@ -0,0 +1,74 @@
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#as: -I${srcdir}/$subdir
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#objdump: -dwMaddr16 -Mdata16
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#name: i386 16-bit LWP
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 8f e9 78 12 c0[ ]+llwpcb %eax
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[ ]*[a-f0-9]+: 8f e9 78 12 c1[ ]+llwpcb %ecx
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[ ]*[a-f0-9]+: 8f e9 78 12 c2[ ]+llwpcb %edx
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[ ]*[a-f0-9]+: 8f e9 78 12 c3[ ]+llwpcb %ebx
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[ ]*[a-f0-9]+: 8f e9 78 12 c4[ ]+llwpcb %esp
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[ ]*[a-f0-9]+: 8f e9 78 12 c5[ ]+llwpcb %ebp
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[ ]*[a-f0-9]+: 8f e9 78 12 c6[ ]+llwpcb %esi
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[ ]*[a-f0-9]+: 8f e9 78 12 c7[ ]+llwpcb %edi
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[ ]*[a-f0-9]+: 8f e9 78 12 cf[ ]+slwpcb %edi
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[ ]*[a-f0-9]+: 8f e9 78 12 ce[ ]+slwpcb %esi
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[ ]*[a-f0-9]+: 8f e9 78 12 cd[ ]+slwpcb %ebp
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[ ]*[a-f0-9]+: 8f e9 78 12 cc[ ]+slwpcb %esp
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[ ]*[a-f0-9]+: 8f e9 78 12 cb[ ]+slwpcb %ebx
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[ ]*[a-f0-9]+: 8f e9 78 12 ca[ ]+slwpcb %edx
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[ ]*[a-f0-9]+: 8f e9 78 12 c9[ ]+slwpcb %ecx
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[ ]*[a-f0-9]+: 8f e9 78 12 c8[ ]+slwpcb %eax
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[ ]*[a-f0-9]+: 8f ea 78 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%eax
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[ ]*[a-f0-9]+: 8f ea 70 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%ecx
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[ ]*[a-f0-9]+: 8f ea 68 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%edx
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[ ]*[a-f0-9]+: 8f ea 60 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%ebx
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[ ]*[a-f0-9]+: 8f ea 58 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%esp
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[ ]*[a-f0-9]+: 8f ea 50 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%ebp
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[ ]*[a-f0-9]+: 8f ea 48 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%esi
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[ ]*[a-f0-9]+: 8f ea 40 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%edi
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[ ]*[a-f0-9]+: 8f ea 78 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%eax
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[ ]*[a-f0-9]+: 8f ea 70 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%ecx
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[ ]*[a-f0-9]+: 8f ea 68 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%edx
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[ ]*[a-f0-9]+: 8f ea 60 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%ebx
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[ ]*[a-f0-9]+: 8f ea 58 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%esp
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[ ]*[a-f0-9]+: 8f ea 50 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%ebp
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[ ]*[a-f0-9]+: 8f ea 48 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%esi
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[ ]*[a-f0-9]+: 8f ea 40 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%edi
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[ ]*[a-f0-9]+: 67 8f ea 78 12 07 78 56 34 12[ ]+lwpins \$0x12345678,\(%edi\),%eax
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[ ]*[a-f0-9]+: 67 8f ea 70 12 06 78 56 34 12[ ]+lwpins \$0x12345678,\(%esi\),%ecx
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[ ]*[a-f0-9]+: 67 8f ea 68 12 45 00 78 56 34 12[ ]+lwpins \$0x12345678,0x0\(%ebp\),%edx
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[ ]*[a-f0-9]+: 67 8f ea 60 12 04 24 78 56 34 12[ ]+lwpins \$0x12345678,\(%esp\),%ebx
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[ ]*[a-f0-9]+: 67 8f ea 58 12 03 78 56 34 12[ ]+lwpins \$0x12345678,\(%ebx\),%esp
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[ ]*[a-f0-9]+: 67 8f ea 50 12 02 78 56 34 12[ ]+lwpins \$0x12345678,\(%edx\),%ebp
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[ ]*[a-f0-9]+: 67 8f ea 48 12 01 78 56 34 12[ ]+lwpins \$0x12345678,\(%ecx\),%esi
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[ ]*[a-f0-9]+: 67 8f ea 40 12 00 78 56 34 12[ ]+lwpins \$0x12345678,\(%eax\),%edi
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[ ]*[a-f0-9]+: 67 8f ea 78 12 0f 78 56 34 12[ ]+lwpval \$0x12345678,\(%edi\),%eax
|
||||
[ ]*[a-f0-9]+: 67 8f ea 70 12 0e 78 56 34 12[ ]+lwpval \$0x12345678,\(%esi\),%ecx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 68 12 4d 00 78 56 34 12[ ]+lwpval \$0x12345678,0x0\(%ebp\),%edx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 60 12 0c 24 78 56 34 12[ ]+lwpval \$0x12345678,\(%esp\),%ebx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 58 12 0b 78 56 34 12[ ]+lwpval \$0x12345678,\(%ebx\),%esp
|
||||
[ ]*[a-f0-9]+: 67 8f ea 50 12 0a 78 56 34 12[ ]+lwpval \$0x12345678,\(%edx\),%ebp
|
||||
[ ]*[a-f0-9]+: 67 8f ea 48 12 09 78 56 34 12[ ]+lwpval \$0x12345678,\(%ecx\),%esi
|
||||
[ ]*[a-f0-9]+: 67 8f ea 40 12 08 78 56 34 12[ ]+lwpval \$0x12345678,\(%eax\),%edi
|
||||
[ ]*[a-f0-9]+: 67 8f ea 78 12 87 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edi\),%eax
|
||||
[ ]*[a-f0-9]+: 67 8f ea 70 12 86 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esi\),%ecx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 68 12 85 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebp\),%edx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 60 12 84 24 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esp\),%ebx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 58 12 83 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebx\),%esp
|
||||
[ ]*[a-f0-9]+: 67 8f ea 50 12 82 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edx\),%ebp
|
||||
[ ]*[a-f0-9]+: 67 8f ea 48 12 81 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ecx\),%esi
|
||||
[ ]*[a-f0-9]+: 67 8f ea 40 12 80 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%eax\),%edi
|
||||
[ ]*[a-f0-9]+: 67 8f ea 78 12 8f fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edi\),%eax
|
||||
[ ]*[a-f0-9]+: 67 8f ea 70 12 8e fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esi\),%ecx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 68 12 8d fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebp\),%edx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 60 12 8c 24 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esp\),%ebx
|
||||
[ ]*[a-f0-9]+: 67 8f ea 58 12 8b fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebx\),%esp
|
||||
[ ]*[a-f0-9]+: 67 8f ea 50 12 8a fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edx\),%ebp
|
||||
[ ]*[a-f0-9]+: 67 8f ea 48 12 89 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ecx\),%esi
|
||||
[ ]*[a-f0-9]+: 67 8f ea 40 12 88 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%eax\),%edi
|
||||
#pass
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
# Check 16-bit LWP instructions
|
||||
|
||||
.code16
|
||||
.include "lwp.s"
|
||||
|
|
@ -1,3 +1,15 @@
|
|||
2019-06-27 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-dis.c (Iq): Delete.
|
||||
(Id): New.
|
||||
(reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
|
||||
TBM insns.
|
||||
(vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
|
||||
vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
|
||||
(OP_E_memory): Also honor needindex when deciding whether an
|
||||
address size prefix needs printing.
|
||||
(OP_I): Remove handling of q_mode. Add handling of d_mode.
|
||||
|
||||
2019-06-26 Jim Wilson <jimw@sifive.com>
|
||||
|
||||
PR binutils/24739
|
||||
|
|
|
|||
|
|
@ -291,8 +291,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
|
||||
#define Iv { OP_I, v_mode }
|
||||
#define sIv { OP_sI, v_mode }
|
||||
#define Iq { OP_I, q_mode }
|
||||
#define Iv64 { OP_I64, v_mode }
|
||||
#define Id { OP_I, d_mode }
|
||||
#define Iw { OP_I, w_mode }
|
||||
#define I1 { OP_I, const_1_mode }
|
||||
#define Jb { OP_J, b_mode }
|
||||
|
|
@ -3596,29 +3596,29 @@ static const struct dis386 reg_table[][8] = {
|
|||
},
|
||||
/* REG_XOP_LWP */
|
||||
{
|
||||
{ "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
|
||||
{ "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
|
||||
{ "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
|
||||
{ "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
|
||||
},
|
||||
/* REG_XOP_TBM_01 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ "blcs", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ "blcic", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ "blsic", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
},
|
||||
/* REG_XOP_TBM_02 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
|
||||
{ "blci", { { OP_LWP_E, 0 }, Edq }, 0 },
|
||||
},
|
||||
|
||||
#include "i386-dis-evex-reg.h"
|
||||
|
|
@ -8150,7 +8150,7 @@ static const struct dis386 xop_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 10 */
|
||||
{ "bextr", { Gv, Ev, Iq }, 0 },
|
||||
{ "bextrS", { Gdq, Edq, Id }, 0 },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_XOP_LWP) },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -9343,38 +9343,38 @@ static const struct dis386 vex_len_table[][2] = {
|
|||
|
||||
/* VEX_LEN_0F2A_P_1 */
|
||||
{
|
||||
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
|
||||
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
|
||||
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
|
||||
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F2A_P_3 */
|
||||
{
|
||||
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
|
||||
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
|
||||
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
|
||||
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F2C_P_1 */
|
||||
{
|
||||
{ "vcvttss2si", { Gv, EXdScalar }, 0 },
|
||||
{ "vcvttss2si", { Gv, EXdScalar }, 0 },
|
||||
{ "vcvttss2si", { Gdq, EXdScalar }, 0 },
|
||||
{ "vcvttss2si", { Gdq, EXdScalar }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F2C_P_3 */
|
||||
{
|
||||
{ "vcvttsd2si", { Gv, EXqScalar }, 0 },
|
||||
{ "vcvttsd2si", { Gv, EXqScalar }, 0 },
|
||||
{ "vcvttsd2si", { Gdq, EXqScalar }, 0 },
|
||||
{ "vcvttsd2si", { Gdq, EXqScalar }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F2D_P_1 */
|
||||
{
|
||||
{ "vcvtss2si", { Gv, EXdScalar }, 0 },
|
||||
{ "vcvtss2si", { Gv, EXdScalar }, 0 },
|
||||
{ "vcvtss2si", { Gdq, EXdScalar }, 0 },
|
||||
{ "vcvtss2si", { Gdq, EXdScalar }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F2D_P_3 */
|
||||
{
|
||||
{ "vcvtsd2si", { Gv, EXqScalar }, 0 },
|
||||
{ "vcvtsd2si", { Gv, EXqScalar }, 0 },
|
||||
{ "vcvtsd2si", { Gdq, EXqScalar }, 0 },
|
||||
{ "vcvtsd2si", { Gdq, EXqScalar }, 0 },
|
||||
},
|
||||
|
||||
/* VEX_LEN_0F41_P_0 */
|
||||
|
|
@ -14203,7 +14203,7 @@ OP_E_memory (int bytemode, int sizeflag)
|
|||
}
|
||||
}
|
||||
|
||||
if ((havebase || haveindex || needaddr32 || riprel)
|
||||
if ((havebase || haveindex || needindex || needaddr32 || riprel)
|
||||
&& (bytemode != v_bnd_mode)
|
||||
&& (bytemode != v_bndmk_mode)
|
||||
&& (bytemode != bnd_mode)
|
||||
|
|
@ -14729,13 +14729,6 @@ OP_I (int bytemode, int sizeflag)
|
|||
op = *codep++;
|
||||
mask = 0xff;
|
||||
break;
|
||||
case q_mode:
|
||||
if (address_mode == mode_64bit)
|
||||
{
|
||||
op = get32s ();
|
||||
break;
|
||||
}
|
||||
/* Fall through. */
|
||||
case v_mode:
|
||||
USED_REX (REX_W);
|
||||
if (rex & REX_W)
|
||||
|
|
@ -14755,6 +14748,10 @@ OP_I (int bytemode, int sizeflag)
|
|||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
break;
|
||||
case d_mode:
|
||||
mask = 0xffffffff;
|
||||
op = get32 ();
|
||||
break;
|
||||
case w_mode:
|
||||
mask = 0xfffff;
|
||||
op = get16 ();
|
||||
|
|
|
|||
Loading…
Reference in New Issue