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x86: allow VEX et al encodings in 16-bit (protected) mode

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These encodings aren't valid in real and VM86 modes, but they are very
well usable in 16-bit protected mode.

A few adjustments in the disassembler tables are needed where Ev or Gv
were wrongly used. Additionally an adjustment is needed to avoid
printing "addr32" when that's already recognizable by the use of %eiz.

Furthermore the Iq operand template was wrong for XOP:0Ah encoding
insns: They're having a uniform 32-bit immediate. Drop Iq and introduce
Id instead.

Clone a few existing test cases to exercise assembler and disassembler.
This commit is contained in:
Jan Beulich 2019-06-27 08:49:40 +02:00 committed by Jan Beulich
parent 65bd27298d
commit c1dc7af521
17 changed files with 16835 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
gas/ChangeLog
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@ -1,3 +1,21 @@
2019-06-27 Jan Beulich <jbeulich@suse.com>
config/tc-i386.c (md_assemble): Check for protected mode
incapable processor before encoding VEX and alike insns.
* testsuite/gas/i386/inval-16.s: For 80186 architecture.
* testsuite/gas/i386/inval-16.l: Adjust expectations.
* testsuite/gas/i386/avx-16bit.d,
testsuite/gas/i386/avx-16bit.s,
testsuite/gas/i386/avx512f-16bit.d,
testsuite/gas/i386/avx512f-16bit.s,
testsuite/gas/i386/bmi-16bit.d,
testsuite/gas/i386/bmi-16bit.s,
testsuite/gas/i386/bmi2-16bit.d,
testsuite/gas/i386/bmi2-16bit.s,
testsuite/gas/i386/lwp-16bit.d,
testsuite/gas/i386/lwp-16bit.s: New
testsuite/gas/i386/i386.exp: Run new tests.
2019-06-26 Jim Wilson <jimw@sifive.com>
* testsuite/gas/xstormy16/allinsn.sh: Change first line to

4
gas/config/tc-i386.c
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@ -4388,9 +4388,9 @@ md_assemble (char *line)
if (is_any_vex_encoding (&i.tm))
{
if (flag_code == CODE_16BIT)
if (!cpu_arch_flags.bitfield.cpui286)
{
as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
as_bad (_("instruction `%s' isn't supported outside of protected mode."),
i.tm.name);
return;
}

3274
gas/testsuite/gas/i386/avx-16bit.d Normal file
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7
gas/testsuite/gas/i386/avx-16bit.s Normal file
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@ -0,0 +1,7 @@
# Check AVX instructions in 16-bit mode
.code16
.include "avx.s"
.att_syntax prefix
vaddps (%bx),%ymm6,%ymm2

13297
gas/testsuite/gas/i386/avx512f-16bit.d Normal file
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4
gas/testsuite/gas/i386/avx512f-16bit.s Normal file
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@ -0,0 +1,4 @@
# Check AVX512F instructions in 16-bit mode
.code16
.include "avx512f.s"

46
gas/testsuite/gas/i386/bmi-16bit.d Normal file
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@ -0,0 +1,46 @@
#as: -I${srcdir}/$subdir
#objdump: -dwMaddr16 -Mdata16
#name: i386 16-bit BMI
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %ax,%bx
[ ]*[a-f0-9]+: 67 f3 0f bc 19 tzcnt \(%ecx\),%bx
[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %eax,%ebx
[ ]*[a-f0-9]+: 67 66 f3 0f bc 19 tzcnt \(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 19 blsi \(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 09 blsr \(%ecx\),%ebx
[ ]*[a-f0-9]+: f3 0f bc d8 tzcnt %ax,%bx
[ ]*[a-f0-9]+: 67 f3 0f bc 19 tzcnt \(%ecx\),%bx
[ ]*[a-f0-9]+: 67 f3 0f bc 19 tzcnt \(%ecx\),%bx
[ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 78 f7 f3 bextr %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f7 31 bextr %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 66 f3 0f bc d8 tzcnt %eax,%ebx
[ ]*[a-f0-9]+: 67 66 f3 0f bc 19 tzcnt \(%ecx\),%ebx
[ ]*[a-f0-9]+: 67 66 f3 0f bc 19 tzcnt \(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 d8 blsi %eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 19 blsi \(%ecx\),%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 19 blsi \(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 d0 blsmsk %eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 11 blsmsk \(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 60 f3 c8 blsr %eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 09 blsr \(%ecx\),%ebx
[ ]*[a-f0-9]+: 67 c4 e2 60 f3 09 blsr \(%ecx\),%ebx
#pass

4
gas/testsuite/gas/i386/bmi-16bit.s Normal file
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@ -0,0 +1,4 @@
# Check 16-bit BMI instructions
.code16
.include "bmi.s"

51
gas/testsuite/gas/i386/bmi2-16bit.d Normal file
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@ -0,0 +1,51 @@
#as: -I${srcdir}/$subdir
#objdump: -dwMaddr16 -Mdata16
#name: i386 16-bit BMI2
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: c4 e3 7b f0 d8 07 rorx \$0x7,%eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e3 7b f0 19 07 rorx \$0x7,\(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 63 f6 f0 mulx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f6 31 mulx \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 63 f5 f0 pdep %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f5 31 pdep \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 62 f5 f0 pext %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 62 f5 31 pext \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 78 f5 f3 bzhi %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f5 31 bzhi %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e3 7b f0 d8 07 rorx \$0x7,%eax,%ebx
[ ]*[a-f0-9]+: 67 c4 e3 7b f0 19 07 rorx \$0x7,\(%ecx\),%ebx
[ ]*[a-f0-9]+: 67 c4 e3 7b f0 19 07 rorx \$0x7,\(%ecx\),%ebx
[ ]*[a-f0-9]+: c4 e2 63 f6 f0 mulx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f6 31 mulx \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f6 31 mulx \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 63 f5 f0 pdep %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f5 31 pdep \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f5 31 pdep \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 62 f5 f0 pext %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 62 f5 31 pext \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 62 f5 31 pext \(%ecx\),%ebx,%esi
[ ]*[a-f0-9]+: c4 e2 78 f5 f3 bzhi %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f5 31 bzhi %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 c4 e2 60 f5 31 bzhi %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx %eax,%ebx,%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
#pass

4
gas/testsuite/gas/i386/bmi2-16bit.s Normal file
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@ -0,0 +1,4 @@
# Check 16-bit BMI2 instructions
.code16
.include "bmi2.s"

6
gas/testsuite/gas/i386/i386.exp
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@ -209,6 +209,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx-scalar"
run_dump_test "avx-scalar-intel"
run_dump_test "avx-scalar-2"
run_dump_test "avx-16bit"
run_dump_test "avx256int"
run_dump_test "avx256int-intel"
run_dump_test "avx2"
@ -225,6 +226,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx512f-nondef"
run_list_test "avx512f-plain" "-al"
run_dump_test "avx512f-ymm"
run_dump_test "avx512f-16bit"
run_dump_test "avx512cd"
run_dump_test "avx512cd-intel"
run_dump_test "avx512er"
@ -276,6 +278,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "sse2avx-opts-intel"
run_dump_test "bmi2"
run_dump_test "bmi2-intel"
run_dump_test "bmi2-16bit"
run_dump_test "fma"
run_dump_test "fma-intel"
run_dump_test "fma-scalar"
@ -287,12 +290,15 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "rtm-intel"
run_dump_test "fma4"
run_dump_test "lwp"
run_dump_test "lwp-16bit"
run_dump_test "xop"
run_dump_test "xop32reg"
run_dump_test "bmi"
run_dump_test "bmi-intel"
run_dump_test "bmi-16bit"
run_dump_test "tbm"
run_dump_test "tbm-intel"
run_dump_test "tbm-16bit"
run_dump_test "f16c"
run_dump_test "f16c-intel"
run_dump_test "fsgs"

2
gas/testsuite/gas/i386/inval-16.l
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@ -10,7 +10,7 @@ GAS LISTING .*
[ ]*1[ ]+\.text
[ ]*2[ ]+\.code16
[ ]*2[ ]+\.arch i186; \.code16
[ ]*3[ ]+vmovapd %xmm0,%xmm1
[ ]*4[ ]+vaddsd %xmm4, %xmm5, %xmm6\{%k7\}
[ ]*5[ ]+vfrczpd %xmm7,%xmm7

2
gas/testsuite/gas/i386/inval-16.s
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@ -1,5 +1,5 @@
.text
.code16
.arch i186; .code16
vmovapd %xmm0,%xmm1
vaddsd %xmm4, %xmm5, %xmm6{%k7}
vfrczpd %xmm7,%xmm7

74
gas/testsuite/gas/i386/lwp-16bit.d Normal file
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@ -0,0 +1,74 @@
#as: -I${srcdir}/$subdir
#objdump: -dwMaddr16 -Mdata16
#name: i386 16-bit LWP
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 8f e9 78 12 c0[ ]+llwpcb %eax
[ ]*[a-f0-9]+: 8f e9 78 12 c1[ ]+llwpcb %ecx
[ ]*[a-f0-9]+: 8f e9 78 12 c2[ ]+llwpcb %edx
[ ]*[a-f0-9]+: 8f e9 78 12 c3[ ]+llwpcb %ebx
[ ]*[a-f0-9]+: 8f e9 78 12 c4[ ]+llwpcb %esp
[ ]*[a-f0-9]+: 8f e9 78 12 c5[ ]+llwpcb %ebp
[ ]*[a-f0-9]+: 8f e9 78 12 c6[ ]+llwpcb %esi
[ ]*[a-f0-9]+: 8f e9 78 12 c7[ ]+llwpcb %edi
[ ]*[a-f0-9]+: 8f e9 78 12 cf[ ]+slwpcb %edi
[ ]*[a-f0-9]+: 8f e9 78 12 ce[ ]+slwpcb %esi
[ ]*[a-f0-9]+: 8f e9 78 12 cd[ ]+slwpcb %ebp
[ ]*[a-f0-9]+: 8f e9 78 12 cc[ ]+slwpcb %esp
[ ]*[a-f0-9]+: 8f e9 78 12 cb[ ]+slwpcb %ebx
[ ]*[a-f0-9]+: 8f e9 78 12 ca[ ]+slwpcb %edx
[ ]*[a-f0-9]+: 8f e9 78 12 c9[ ]+slwpcb %ecx
[ ]*[a-f0-9]+: 8f e9 78 12 c8[ ]+slwpcb %eax
[ ]*[a-f0-9]+: 8f ea 78 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%eax
[ ]*[a-f0-9]+: 8f ea 70 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%ecx
[ ]*[a-f0-9]+: 8f ea 68 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%edx
[ ]*[a-f0-9]+: 8f ea 60 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%ebx
[ ]*[a-f0-9]+: 8f ea 58 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%esp
[ ]*[a-f0-9]+: 8f ea 50 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%ebp
[ ]*[a-f0-9]+: 8f ea 48 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%esi
[ ]*[a-f0-9]+: 8f ea 40 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%edi
[ ]*[a-f0-9]+: 8f ea 78 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%eax
[ ]*[a-f0-9]+: 8f ea 70 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%ecx
[ ]*[a-f0-9]+: 8f ea 68 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%edx
[ ]*[a-f0-9]+: 8f ea 60 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%ebx
[ ]*[a-f0-9]+: 8f ea 58 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%esp
[ ]*[a-f0-9]+: 8f ea 50 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%ebp
[ ]*[a-f0-9]+: 8f ea 48 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%esi
[ ]*[a-f0-9]+: 8f ea 40 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%edi
[ ]*[a-f0-9]+: 67 8f ea 78 12 07 78 56 34 12[ ]+lwpins \$0x12345678,\(%edi\),%eax
[ ]*[a-f0-9]+: 67 8f ea 70 12 06 78 56 34 12[ ]+lwpins \$0x12345678,\(%esi\),%ecx
[ ]*[a-f0-9]+: 67 8f ea 68 12 45 00 78 56 34 12[ ]+lwpins \$0x12345678,0x0\(%ebp\),%edx
[ ]*[a-f0-9]+: 67 8f ea 60 12 04 24 78 56 34 12[ ]+lwpins \$0x12345678,\(%esp\),%ebx
[ ]*[a-f0-9]+: 67 8f ea 58 12 03 78 56 34 12[ ]+lwpins \$0x12345678,\(%ebx\),%esp
[ ]*[a-f0-9]+: 67 8f ea 50 12 02 78 56 34 12[ ]+lwpins \$0x12345678,\(%edx\),%ebp
[ ]*[a-f0-9]+: 67 8f ea 48 12 01 78 56 34 12[ ]+lwpins \$0x12345678,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 8f ea 40 12 00 78 56 34 12[ ]+lwpins \$0x12345678,\(%eax\),%edi
[ ]*[a-f0-9]+: 67 8f ea 78 12 0f 78 56 34 12[ ]+lwpval \$0x12345678,\(%edi\),%eax
[ ]*[a-f0-9]+: 67 8f ea 70 12 0e 78 56 34 12[ ]+lwpval \$0x12345678,\(%esi\),%ecx
[ ]*[a-f0-9]+: 67 8f ea 68 12 4d 00 78 56 34 12[ ]+lwpval \$0x12345678,0x0\(%ebp\),%edx
[ ]*[a-f0-9]+: 67 8f ea 60 12 0c 24 78 56 34 12[ ]+lwpval \$0x12345678,\(%esp\),%ebx
[ ]*[a-f0-9]+: 67 8f ea 58 12 0b 78 56 34 12[ ]+lwpval \$0x12345678,\(%ebx\),%esp
[ ]*[a-f0-9]+: 67 8f ea 50 12 0a 78 56 34 12[ ]+lwpval \$0x12345678,\(%edx\),%ebp
[ ]*[a-f0-9]+: 67 8f ea 48 12 09 78 56 34 12[ ]+lwpval \$0x12345678,\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 8f ea 40 12 08 78 56 34 12[ ]+lwpval \$0x12345678,\(%eax\),%edi
[ ]*[a-f0-9]+: 67 8f ea 78 12 87 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edi\),%eax
[ ]*[a-f0-9]+: 67 8f ea 70 12 86 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esi\),%ecx
[ ]*[a-f0-9]+: 67 8f ea 68 12 85 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebp\),%edx
[ ]*[a-f0-9]+: 67 8f ea 60 12 84 24 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esp\),%ebx
[ ]*[a-f0-9]+: 67 8f ea 58 12 83 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebx\),%esp
[ ]*[a-f0-9]+: 67 8f ea 50 12 82 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edx\),%ebp
[ ]*[a-f0-9]+: 67 8f ea 48 12 81 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 8f ea 40 12 80 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%eax\),%edi
[ ]*[a-f0-9]+: 67 8f ea 78 12 8f fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edi\),%eax
[ ]*[a-f0-9]+: 67 8f ea 70 12 8e fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esi\),%ecx
[ ]*[a-f0-9]+: 67 8f ea 68 12 8d fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebp\),%edx
[ ]*[a-f0-9]+: 67 8f ea 60 12 8c 24 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esp\),%ebx
[ ]*[a-f0-9]+: 67 8f ea 58 12 8b fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebx\),%esp
[ ]*[a-f0-9]+: 67 8f ea 50 12 8a fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edx\),%ebp
[ ]*[a-f0-9]+: 67 8f ea 48 12 89 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ecx\),%esi
[ ]*[a-f0-9]+: 67 8f ea 40 12 88 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%eax\),%edi
#pass

4
gas/testsuite/gas/i386/lwp-16bit.s Normal file
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@ -0,0 +1,4 @@
# Check 16-bit LWP instructions
.code16
.include "lwp.s"

12
opcodes/ChangeLog
View File

@ -1,3 +1,15 @@
2019-06-27 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (Iq): Delete.
(Id): New.
(reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
TBM insns.
(vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
(OP_E_memory): Also honor needindex when deciding whether an
address size prefix needs printing.
(OP_I): Remove handling of q_mode. Add handling of d_mode.
2019-06-26 Jim Wilson <jimw@sifive.com>
PR binutils/24739

63
opcodes/i386-dis.c
View File

@ -291,8 +291,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
#define Iv { OP_I, v_mode }
#define sIv { OP_sI, v_mode }
#define Iq { OP_I, q_mode }
#define Iv64 { OP_I64, v_mode }
#define Id { OP_I, d_mode }
#define Iw { OP_I, w_mode }
#define I1 { OP_I, const_1_mode }
#define Jb { OP_J, b_mode }
@ -3596,29 +3596,29 @@ static const struct dis386 reg_table[][8] = {
},
/* REG_XOP_LWP */
{
{ "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
{ "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
{ "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
{ "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
},
/* REG_XOP_TBM_01 */
{
{ Bad_Opcode },
{ "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 },
{ "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 },
{ "blcs", { { OP_LWP_E, 0 }, Edq }, 0 },
{ "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
{ "blcic", { { OP_LWP_E, 0 }, Edq }, 0 },
{ "blsic", { { OP_LWP_E, 0 }, Edq }, 0 },
{ "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
},
/* REG_XOP_TBM_02 */
{
{ Bad_Opcode },
{ "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
{ "blci", { { OP_LWP_E, 0 }, Edq }, 0 },
},
#include "i386-dis-evex-reg.h"
@ -8150,7 +8150,7 @@ static const struct dis386 xop_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ "bextr", { Gv, Ev, Iq }, 0 },
{ "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
@ -9343,38 +9343,38 @@ static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F2A_P_1 */
{
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
{ "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
},
/* VEX_LEN_0F2A_P_3 */
{
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
{ "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
},
/* VEX_LEN_0F2C_P_1 */
{
{ "vcvttss2si", { Gv, EXdScalar }, 0 },
{ "vcvttss2si", { Gv, EXdScalar }, 0 },
{ "vcvttss2si", { Gdq, EXdScalar }, 0 },
{ "vcvttss2si", { Gdq, EXdScalar }, 0 },
},
/* VEX_LEN_0F2C_P_3 */
{
{ "vcvttsd2si", { Gv, EXqScalar }, 0 },
{ "vcvttsd2si", { Gv, EXqScalar }, 0 },
{ "vcvttsd2si", { Gdq, EXqScalar }, 0 },
{ "vcvttsd2si", { Gdq, EXqScalar }, 0 },
},
/* VEX_LEN_0F2D_P_1 */
{
{ "vcvtss2si", { Gv, EXdScalar }, 0 },
{ "vcvtss2si", { Gv, EXdScalar }, 0 },
{ "vcvtss2si", { Gdq, EXdScalar }, 0 },
{ "vcvtss2si", { Gdq, EXdScalar }, 0 },
},
/* VEX_LEN_0F2D_P_3 */
{
{ "vcvtsd2si", { Gv, EXqScalar }, 0 },
{ "vcvtsd2si", { Gv, EXqScalar }, 0 },
{ "vcvtsd2si", { Gdq, EXqScalar }, 0 },
{ "vcvtsd2si", { Gdq, EXqScalar }, 0 },
},
/* VEX_LEN_0F41_P_0 */
@ -14203,7 +14203,7 @@ OP_E_memory (int bytemode, int sizeflag)
}
}
if ((havebase || haveindex || needaddr32 || riprel)
if ((havebase || haveindex || needindex || needaddr32 || riprel)
&& (bytemode != v_bnd_mode)
&& (bytemode != v_bndmk_mode)
&& (bytemode != bnd_mode)
@ -14729,13 +14729,6 @@ OP_I (int bytemode, int sizeflag)
op = *codep++;
mask = 0xff;
break;
case q_mode:
if (address_mode == mode_64bit)
{
op = get32s ();
break;
}
/* Fall through. */
case v_mode:
USED_REX (REX_W);
if (rex & REX_W)
@ -14755,6 +14748,10 @@ OP_I (int bytemode, int sizeflag)
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
case d_mode:
mask = 0xffffffff;
op = get32 ();
break;
case w_mode:
mask = 0xfffff;
op = get16 ();