PR binutils/10924
* arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro. (print_insn_arm): Extend %s format control code to check for unpredictable addressing modes. Add support for %S format control code which suppresses this check. (W_BIT, I_BIT, U_BIT, P_BIT): New macros. (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET, PRE_BIT_SET): New macros. (print_insn_coprocessor): Use the new macros instead of magic constants. (print_arm_address): Likewise. (pirnt_insn_arm): Likewise. (print_insn_thumb32): Likewise.
This commit is contained in:
parent
41327c9d6d
commit
c1e2689731
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@ -1,3 +1,19 @@
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2009-11-11 Nick Clifton <nickc@redhat.com>
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PR binutils/10924
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* arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro.
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(print_insn_arm): Extend %s format control code to check for
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unpredictable addressing modes. Add support for %S format control
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code which suppresses this check.
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(W_BIT, I_BIT, U_BIT, P_BIT): New macros.
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(WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET,
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PRE_BIT_SET): New macros.
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(print_insn_coprocessor): Use the new macros instead of magic
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constants.
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(print_arm_address): Likewise.
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(pirnt_insn_arm): Likewise.
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(print_insn_thumb32): Likewise.
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2009-11-11 Nick Clifton <nickc@redhat.com>
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* po/id.po: Updated Indonesian translation.
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@ -114,6 +114,7 @@ enum opcode_sentinel_enum
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} opcode_sentinels;
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#define UNDEFINED_INSTRUCTION "undefined instruction %0-31x"
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#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
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/* Common coprocessor opcodes shared between Arm and Thumb-2. */
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@ -776,6 +777,7 @@ static const struct opcode32 neon_opcodes[] =
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%a print address for ldr/str instruction
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%s print address for ldr/str halfword/signextend instruction
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%S like %s but allow UNPREDICTABLE addressing
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%b print branch destination
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%c print condition code (always bits 28-31)
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%m print register mask for ldm/stm instruction
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@ -823,8 +825,8 @@ static const struct opcode32 arm_opcodes[] =
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{ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
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{ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
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{ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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{ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"},
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{ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"},
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{ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %S"},
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{ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %S"},
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{ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
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{ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
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{ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
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@ -1701,6 +1703,16 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
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}
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}
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#define W_BIT 21
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#define I_BIT 22
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#define U_BIT 23
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#define P_BIT 24
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#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
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#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
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#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
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#define PRE_BIT_SET (given & (1 << P_BIT))
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/* Print one coprocessor instruction on INFO->STREAM.
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Return TRUE if the instuction matched, FALSE if this is not a
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recognised coprocessor instruction. */
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@ -1801,15 +1813,15 @@ print_insn_coprocessor (bfd_vma pc,
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func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
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value_in_comment = offset * 4;
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if ((given & 0x00800000) == 0)
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if (NEGATIVE_BIT_SET)
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value_in_comment = - value_in_comment;
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if ((given & (1 << 24)) != 0)
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if (PRE_BIT_SET)
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{
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if (offset)
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func (stream, ", #%d]%s",
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value_in_comment,
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((given & 0x00200000) != 0 ? "!" : ""));
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WRITEBACK_BIT_SET ? "!" : "");
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else
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func (stream, "]");
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}
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@ -1817,7 +1829,7 @@ print_insn_coprocessor (bfd_vma pc,
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{
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func (stream, "]");
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if (given & (1 << 21))
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if (WRITEBACK_BIT_SET)
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{
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if (offset)
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func (stream, ", #%d", value_in_comment);
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@ -1849,14 +1861,13 @@ print_insn_coprocessor (bfd_vma pc,
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{
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int rn = (given >> 16) & 0xf;
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int offset = (given & 0xff) * 4;
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int add = (given >> 23) & 1;
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func (stream, "[%s", arm_regnames[rn]);
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if (offset)
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{
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if (!add)
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offset = -offset;
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if (NEGATIVE_BIT_SET)
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offset = - offset;
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func (stream, ", #%d", offset);
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if (rn != 15)
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value_in_comment = offset;
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@ -2159,20 +2170,20 @@ print_insn_coprocessor (bfd_vma pc,
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if (multiplier > 1)
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{
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value_in_comment = offset * multiplier;
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if ((given & 0x00800000) == 0)
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if (NEGATIVE_BIT_SET)
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value_in_comment = - value_in_comment;
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}
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if (offset)
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{
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if ((given & 0x01000000) != 0)
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if (PRE_BIT_SET)
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func (stream, ", #%s%d]%s",
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((given & 0x00800000) == 0 ? "-" : ""),
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NEGATIVE_BIT_SET ? "-" : "",
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offset * multiplier,
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((given & 0x00200000) != 0 ? "!" : ""));
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WRITEBACK_BIT_SET ? "!" : "");
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else
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func (stream, "], #%s%d",
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((given & 0x00800000) == 0 ? "-" : ""),
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NEGATIVE_BIT_SET ? "-" : "",
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offset * multiplier);
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}
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else
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@ -2183,8 +2194,8 @@ print_insn_coprocessor (bfd_vma pc,
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case 'r':
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{
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int imm4 = (given >> 4) & 0xf;
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int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1);
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int ubit = (given >> 23) & 1;
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int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
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int ubit = ! NEGATIVE_BIT_SET;
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const char *rm = arm_regnames [given & 0xf];
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const char *rn = arm_regnames [(given >> 16) & 0xf];
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@ -2259,9 +2270,9 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
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func (stream, "[pc");
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if (given & 0x01000000)
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if (PRE_BIT_SET)
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{
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if ((given & 0x00800000) == 0)
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if (NEGATIVE_BIT_SET)
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offset = - offset;
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/* Pre-indexed. */
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@ -2273,15 +2284,14 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
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being used. Probably a very dangerous thing
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for the programmer to do, but who are we to
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argue ? */
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if (given & 0x00200000)
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if (WRITEBACK_BIT_SET)
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func (stream, "!");
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}
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else
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else /* Post indexed. */
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{
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/* Post indexed. */
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func (stream, "], #%d", offset);
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/* ie ignore the offset. */
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/* Ie ignore the offset. */
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offset = pc + 8;
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}
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@ -2293,26 +2303,25 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
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{
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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if (PRE_BIT_SET)
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{
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if ((given & 0x02000000) == 0)
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{
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offset = given & 0xfff;
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if (offset)
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func (stream, ", #%s%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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NEGATIVE_BIT_SET ? "-" : "", offset);
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}
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else
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{
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func (stream, ", %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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NEGATIVE_BIT_SET ? "-" : "");
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arm_decode_shift (given, func, stream, TRUE);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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WRITEBACK_BIT_SET ? "!" : "");
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}
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else
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{
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@ -2321,16 +2330,14 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
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offset = given & 0xfff;
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if (offset)
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func (stream, "], #%s%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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NEGATIVE_BIT_SET ? "-" : "", offset);
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else
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func (stream, "]");
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}
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else
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{
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func (stream, "], %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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NEGATIVE_BIT_SET ? "-" : "");
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arm_decode_shift (given, func, stream, TRUE);
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}
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}
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@ -2669,16 +2676,16 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
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valbytes[3] = (value >> 24) & 0xff;
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floatformat_to_double
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(&floatformat_ieee_single_little, valbytes,
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&fvalue);
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(& floatformat_ieee_single_little, valbytes,
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& fvalue);
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func (stream, "#%.7g\t; 0x%.8lx", fvalue,
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value);
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}
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else
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func (stream, "#%ld\t; 0x%.8lx",
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(long) ((value & 0x80000000)
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? value | ~0xffffffffl : value), value);
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(long) (NEGATIVE_BIT_SET ? value | ~0xffffffffL : value),
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value);
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break;
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case 64:
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@ -2841,6 +2848,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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{
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if (*c == '%')
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{
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bfd_boolean allow_unpredictable = FALSE;
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switch (*++c)
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{
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case '%':
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@ -2854,58 +2863,54 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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case 'P':
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/* Set P address bit and use normal address
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printing routine. */
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value_in_comment = print_arm_address (pc, info, given | (1 << 24));
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value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
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break;
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case 'S':
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allow_unpredictable = TRUE;
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case 's':
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if ((given & 0x004f0000) == 0x004f0000)
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{
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/* PC relative with immediate offset. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if ((given & 0x00800000) == 0)
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offset = -offset;
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if (NEGATIVE_BIT_SET)
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offset = - offset;
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func (stream, "[pc, #%d]\t; ", offset);
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info->print_address_func (offset + pc + 8, info);
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}
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else
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{
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bfd_boolean negative = (given & 0x00800000) == 0;
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (negative)
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offset = -offset;
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if (NEGATIVE_BIT_SET)
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offset = - offset;
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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if (PRE_BIT_SET)
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{
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/* Pre-indexed. */
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if ((given & 0x00400000) == 0x00400000)
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if (IMMEDIATE_BIT_SET)
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{
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/* Immediate. */
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if (offset)
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func (stream, ", #%d", offset);
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value_in_comment = offset;
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}
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else
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{
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/* Register. */
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func (stream, ", %s%s", negative ? "-" : "",
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else /* Register. */
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func (stream, ", %s%s",
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NEGATIVE_BIT_SET ? "-" : "",
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arm_regnames[given & 0xf]);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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WRITEBACK_BIT_SET ? "!" : "");
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}
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else
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else /* Post-indexed. */
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{
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/* Post-indexed. */
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if ((given & 0x00400000) == 0x00400000)
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if (IMMEDIATE_BIT_SET)
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{
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/* Immediate. */
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if (offset)
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func (stream, "], #%d", offset);
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else
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@ -2913,12 +2918,13 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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value_in_comment = offset;
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}
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else
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{
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/* Register. */
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func (stream, "], %s%s", negative ? "-" : "",
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else /* Register. */
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func (stream, "], %s%s",
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NEGATIVE_BIT_SET ? "-" : "",
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arm_regnames[given & 0xf]);
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}
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if (WRITEBACK_BIT_SET && ! allow_unpredictable)
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func (stream, UNPREDICTABLE_INSTRUCTION);
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}
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}
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break;
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@ -2988,17 +2994,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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int offset = given & 0xff;
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value_in_comment = offset * 4;
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if ((given & 0x00800000) == 0)
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if (NEGATIVE_BIT_SET)
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value_in_comment = - value_in_comment;
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func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
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if ((given & (1 << 24)) != 0)
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if (PRE_BIT_SET)
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{
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if (offset)
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func (stream, ", #%d]%s",
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value_in_comment,
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((given & 0x00200000) != 0 ? "!" : ""));
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WRITEBACK_BIT_SET ? "!" : "");
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else
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func (stream, "]");
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}
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@ -3006,7 +3012,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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{
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func (stream, "]");
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if (given & (1 << 21))
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if (WRITEBACK_BIT_SET)
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{
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if (offset)
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func (stream, ", #%d", value_in_comment);
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@ -3026,7 +3032,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
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bfd_vma address;
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bfd_vma offset = 0;
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if (given & 0x00800000)
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if (! NEGATIVE_BIT_SET)
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/* Is signed, hi bits should be ones. */
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offset = (-1) ^ 0x00ffffff;
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@ -3543,9 +3549,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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switch (mod)
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{
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case 0: imm = imm8; break;
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case 1: imm = ((imm8<<16) | imm8); break;
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case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
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case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
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case 1: imm = ((imm8 << 16) | imm8); break;
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case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
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case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
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default:
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mod = (bits & 0xf80) >> 7;
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imm8 = (bits & 0x07f) | 0x80;
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@ -3621,7 +3627,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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case 'a':
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{
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unsigned int Rn = (given & 0x000f0000) >> 16;
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unsigned int U = (given & 0x00800000) >> 23;
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unsigned int U = ! NEGATIVE_BIT_SET;
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unsigned int op = (given & 0x00000f00) >> 8;
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unsigned int i12 = (given & 0x00000fff);
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unsigned int i8 = (given & 0x000000ff);
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@ -3703,14 +3709,14 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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case 'A':
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{
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unsigned int P = (given & 0x01000000) >> 24;
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unsigned int U = (given & 0x00800000) >> 23;
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unsigned int W = (given & 0x00400000) >> 21;
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unsigned int U = ! NEGATIVE_BIT_SET;
|
||||
unsigned int W = WRITEBACK_BIT_SET;
|
||||
unsigned int Rn = (given & 0x000f0000) >> 16;
|
||||
unsigned int off = (given & 0x000000ff);
|
||||
|
||||
func (stream, "[%s", arm_regnames[Rn]);
|
||||
if (P)
|
||||
|
||||
if (PRE_BIT_SET)
|
||||
{
|
||||
if (off || !U)
|
||||
{
|
||||
|
@ -3845,7 +3851,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
|
|||
|
||||
shift |= (given & 0x000000c0u) >> 6;
|
||||
shift |= (given & 0x00007000u) >> 10;
|
||||
if (given & 0x00200000u)
|
||||
if (WRITEBACK_BIT_SET)
|
||||
func (stream, ", asr #%u", shift);
|
||||
else if (shift)
|
||||
func (stream, ", lsl #%u", shift);
|
||||
|
|
Loading…
Reference in New Issue