* mips-opc.c (CP): New macro.
(mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and dmtc2 Octeon instructions.
This commit is contained in:
Adam Nemet
parent
7b60c20e4c
commit
c27e721e3e
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@ -1,3 +1,10 @@
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2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
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* mips-opc.c (CP): New macro.
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(mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
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membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
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dmtc2 Octeon instructions.
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2008-07-07 Stan Shebs <stan@codesourcery.com>
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* dis-init.c (init_disassemble_info): Init endian_code field.
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@ -62,6 +62,7 @@
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#define WR_C1 INSN_COP
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#define WR_C2 INSN_COP
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#define WR_C3 INSN_COP
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#define CP INSN_COP
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#define WR_HI INSN_WRITE_HI
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#define RD_HI INSN_READ_HI
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@ -577,8 +578,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
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{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
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{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
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{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
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{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
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{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
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{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
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{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
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{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
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{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
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@ -613,14 +614,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
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{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
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{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
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{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
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{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
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{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
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{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT },
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{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
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{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
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{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
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{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
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{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
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{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
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{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
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{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT },
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{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
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{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
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{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
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{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
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{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
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@ -692,8 +693,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
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{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
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{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
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{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
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{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
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{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
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{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
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{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
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{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
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{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 },
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@ -864,9 +865,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
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{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
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{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
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{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
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{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
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{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
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{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT },
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{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
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{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
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{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
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{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
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{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
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@ -939,9 +940,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
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{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
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{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
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{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
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{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
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{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
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{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT },
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{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
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{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
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{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
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{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
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{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
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@ -1491,8 +1492,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
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{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
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{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
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{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
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{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
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{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
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{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
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{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
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{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
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{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
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@ -1958,10 +1961,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
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change the state of the processor and if they do it's up to the
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user to put in nops as necessary. These are at the end so that the
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disassembler recognizes more specific versions first. */
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{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
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{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 },
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{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
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{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
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{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
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{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 },
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{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 },
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{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
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{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
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{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
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