[ARM] Add ARMv8.3 VCMLA and VCADD instructions
Add support for VCMLA and VCADD advanced SIMD complex number instructions. The command line option is -march=armv8.3-a+fp16+simd for enabling all instructions. In arm-dis.c the formatting syntax was abused a bit to select between 0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of duplicating entries in the opcode table. gas/ * config/tc-arm.c (do_vcmla, do_vcadd): Define. (neon_scalar_for_vcmla): Define. (enum operand_parse_code): Add OP_IROT1 and OP_IROT2. (NEON_ENC_TAB): Add DDSI and QQSI variants. (insns): Add vcmla and vcadd. * testsuite/gas/arm/armv8_3-a-simd.d: New. * testsuite/gas/arm/armv8_3-a-simd.s: New. * testsuite/gas/arm/armv8_3-a-simd-bad.d: New. * testsuite/gas/arm/armv8_3-a-simd-bad.l: New. * testsuite/gas/arm/armv8_3-a-simd-bad.s: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
This commit is contained in:
Szabolcs Nagy
parent
0691188992
commit
c28eeff2ea
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@ -1,3 +1,16 @@
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2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-arm.c (do_vcmla, do_vcadd): Define.
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(neon_scalar_for_vcmla): Define.
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(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
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(NEON_ENC_TAB): Add DDSI and QQSI variants.
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(insns): Add vcmla and vcadd.
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* testsuite/gas/arm/armv8_3-a-simd.d: New.
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* testsuite/gas/arm/armv8_3-a-simd.s: New.
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* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
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* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
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* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
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2016-12-05 Claudiu Zissulescu <claziss@synopsys.com>
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* testsuite/gas/arc/textauxregister-1.d: New file.
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@ -6535,6 +6535,8 @@ enum operand_parse_code
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OP_EXPi, /* same, with optional immediate prefix */
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OP_EXPr, /* same, with optional relocation suffix */
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OP_HALF, /* 0 .. 65535 or low/high reloc. */
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OP_IROT1, /* VCADD rotate immediate: 90, 270. */
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OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
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OP_CPSF, /* CPS flags */
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OP_ENDI, /* Endianness specifier */
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@ -13348,6 +13350,8 @@ NEON_ENC_TAB
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X(3, (D, Q, S), MIXED), \
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X(4, (D, D, D, I), DOUBLE), \
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X(4, (Q, Q, Q, I), QUAD), \
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X(4, (D, D, S, I), DOUBLE), \
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X(4, (Q, Q, S, I), QUAD), \
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X(2, (F, F), SINGLE), \
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X(3, (F, F, F), SINGLE), \
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X(2, (F, I), SINGLE), \
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@ -17261,6 +17265,80 @@ do_vrintm (void)
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do_vrint_1 (neon_cvt_mode_m);
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}
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static unsigned
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neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
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{
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unsigned regno = NEON_SCALAR_REG (opnd);
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unsigned elno = NEON_SCALAR_INDEX (opnd);
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if (elsize == 16 && elno < 2 && regno < 16)
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return regno | (elno << 4);
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else if (elsize == 32 && elno == 0)
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return regno;
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first_error (_("scalar out of range"));
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return 0;
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}
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static void
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do_vcmla (void)
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
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_(BAD_FPU));
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constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
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unsigned rot = inst.reloc.exp.X_add_number;
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constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
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_("immediate out of range"));
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rot /= 90;
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if (inst.operands[2].isscalar)
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{
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enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
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unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
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N_KEY | N_F16 | N_F32).size;
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unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
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inst.is_neon = 1;
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inst.instruction = 0xfe000800;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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inst.instruction |= LOW4 (m);
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inst.instruction |= HI1 (m) << 5;
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inst.instruction |= neon_quad (rs) << 6;
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inst.instruction |= rot << 20;
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inst.instruction |= (size == 32) << 23;
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
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unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
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N_KEY | N_F16 | N_F32).size;
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neon_three_same (neon_quad (rs), 0, -1);
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inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
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inst.instruction |= 0xfc200800;
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inst.instruction |= rot << 23;
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inst.instruction |= (size == 32) << 20;
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}
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}
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static void
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do_vcadd (void)
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
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_(BAD_FPU));
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constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
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unsigned rot = inst.reloc.exp.X_add_number;
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constraint (rot != 90 && rot != 270, _("immediate out of range"));
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enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
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unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
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N_KEY | N_F16 | N_F32).size;
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neon_three_same (neon_quad (rs), 0, -1);
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inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
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inst.instruction |= 0xfc800800;
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inst.instruction |= (rot == 270) << 24;
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inst.instruction |= (size == 32) << 20;
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}
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/* Crypto v1 instructions. */
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static void
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do_crypto_2op_1 (unsigned elttype, int op)
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@ -19799,6 +19877,8 @@ static const struct asm_opcode insns[] =
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8_3
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NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
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NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla),
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NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
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@ -0,0 +1,2 @@
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#as: -march=armv8.3-a+fp16+simd
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#error-output: armv8_3-a-simd-bad.l
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@ -0,0 +1,39 @@
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[^:]+: Assembler messages:
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[^:]+:6: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90'
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[^:]+:7: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
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[^:]+:8: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
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[^:]+:9: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
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[^:]+:10: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
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[^:]+:11: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
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[^:]+:13: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
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[^:]+:14: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
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[^:]+:15: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
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[^:]+:16: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
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[^:]+:17: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
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[^:]+:18: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
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[^:]+:19: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
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[^:]+:21: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
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[^:]+:22: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
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[^:]+:23: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
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[^:]+:24: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90'
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[^:]+:25: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90'
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[^:]+:26: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90'
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[^:]+:31: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90'
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[^:]+:32: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
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[^:]+:33: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
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[^:]+:34: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
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[^:]+:35: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
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[^:]+:36: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
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[^:]+:38: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
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[^:]+:39: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
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[^:]+:40: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
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[^:]+:41: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
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[^:]+:42: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
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[^:]+:43: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
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[^:]+:44: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
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[^:]+:46: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
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[^:]+:47: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
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[^:]+:48: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
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[^:]+:49: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90'
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[^:]+:50: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90'
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[^:]+:51: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90'
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@ -0,0 +1,51 @@
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.text
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A1:
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.arm
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vcadd d0,d1,d2,#90
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vcadd.f32 q0,q1,q2,#0
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vcadd.f32 q0,q1,q2,#180
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vcadd.f16 s0,s1,s2,#90
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vcadd.f64 d0,d1,d2,#90
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vcadd.f64 q0,q1,q2,#90
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vcmla d0,d1,d2,#90
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vcmla.f32 q0,q1,q2,#-90
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vcmla.f32 q0,q1,q2,#120
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vcmla.f32 q0,q1,q2,#360
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vcmla.f16 s0,s1,s2,#90
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vcmla.f64 d0,d1,d2,#90
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vcmla.f64 q0,q1,q2,#90
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vcmla.f16 q0,q1,q2[0],#90
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vcmla.f32 q0,q1,q2[0],#90
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vcmla.f16 d0,d1,d2[2],#90
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vcmla.f16 q0,q1,d2[2],#90
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vcmla.f16 q0,q1,d16[1],#90
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vcmla.f32 q0,q1,d2[1],#90
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T1:
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.thumb
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vcadd d0,d1,d2,#90
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vcadd.f32 q0,q1,q2,#0
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vcadd.f32 q0,q1,q2,#180
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vcadd.f16 s0,s1,s2,#90
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vcadd.f64 d0,d1,d2,#90
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vcadd.f64 q0,q1,q2,#90
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vcmla d0,d1,d2,#90
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vcmla.f32 q0,q1,q2,#-90
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vcmla.f32 q0,q1,q2,#120
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vcmla.f32 q0,q1,q2,#360
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vcmla.f16 s0,s1,s2,#90
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vcmla.f64 d0,d1,d2,#90
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vcmla.f64 q0,q1,q2,#90
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vcmla.f16 q0,q1,q2[0],#90
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vcmla.f32 q0,q1,q2[0],#90
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vcmla.f16 d0,d1,d2[2],#90
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vcmla.f16 q0,q1,d2[2],#90
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vcmla.f16 q0,q1,d16[1],#90
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vcmla.f32 q0,q1,d2[1],#90
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@ -0,0 +1,47 @@
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#as: -march=armv8.3-a+fp16+simd
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#objdump: -dr
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#skip: *-*-pe *-wince-* *-*-coff
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.*: +file format .*arm.*
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Disassembly of section .text:
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[0-9a-f]+ <.*>:
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+[0-9a-f]+: fc942846 vcadd.f32 q1, q2, q3, #90
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+[0-9a-f]+: fd942846 vcadd.f32 q1, q2, q3, #270
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+[0-9a-f]+: fcc658a7 vcadd.f16 d21, d22, d23, #90
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+[0-9a-f]+: fc842846 vcadd.f16 q1, q2, q3, #90
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+[0-9a-f]+: fcd658a7 vcadd.f32 d21, d22, d23, #90
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+[0-9a-f]+: fc342846 vcmla.f32 q1, q2, q3, #0
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+[0-9a-f]+: fcb42846 vcmla.f32 q1, q2, q3, #90
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+[0-9a-f]+: fd342846 vcmla.f32 q1, q2, q3, #180
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+[0-9a-f]+: fdb42846 vcmla.f32 q1, q2, q3, #270
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+[0-9a-f]+: fce658a7 vcmla.f16 d21, d22, d23, #90
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+[0-9a-f]+: fca42846 vcmla.f16 q1, q2, q3, #90
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+[0-9a-f]+: fcf658a7 vcmla.f32 d21, d22, d23, #90
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+[0-9a-f]+: fe565883 vcmla.f16 d21, d22, d3\[0\], #90
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+[0-9a-f]+: fe5658a3 vcmla.f16 d21, d22, d3\[1\], #90
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+[0-9a-f]+: fe142843 vcmla.f16 q1, q2, d3\[0\], #90
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+[0-9a-f]+: fe142863 vcmla.f16 q1, q2, d3\[1\], #90
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+[0-9a-f]+: fed658a7 vcmla.f32 d21, d22, d23\[0\], #90
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+[0-9a-f]+: fe942867 vcmla.f32 q1, q2, d23\[0\], #90
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[0-9a-f]+ <.*>:
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+[0-9a-f]+: fc94 2846 vcadd.f32 q1, q2, q3, #90
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+[0-9a-f]+: fd94 2846 vcadd.f32 q1, q2, q3, #270
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+[0-9a-f]+: fcc6 58a7 vcadd.f16 d21, d22, d23, #90
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+[0-9a-f]+: fc84 2846 vcadd.f16 q1, q2, q3, #90
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+[0-9a-f]+: fcd6 58a7 vcadd.f32 d21, d22, d23, #90
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+[0-9a-f]+: fc34 2846 vcmla.f32 q1, q2, q3, #0
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+[0-9a-f]+: fcb4 2846 vcmla.f32 q1, q2, q3, #90
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+[0-9a-f]+: fd34 2846 vcmla.f32 q1, q2, q3, #180
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+[0-9a-f]+: fdb4 2846 vcmla.f32 q1, q2, q3, #270
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+[0-9a-f]+: fce6 58a7 vcmla.f16 d21, d22, d23, #90
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+[0-9a-f]+: fca4 2846 vcmla.f16 q1, q2, q3, #90
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+[0-9a-f]+: fcf6 58a7 vcmla.f32 d21, d22, d23, #90
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+[0-9a-f]+: fe56 5883 vcmla.f16 d21, d22, d3\[0\], #90
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+[0-9a-f]+: fe56 58a3 vcmla.f16 d21, d22, d3\[1\], #90
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+[0-9a-f]+: fe14 2843 vcmla.f16 q1, q2, d3\[0\], #90
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+[0-9a-f]+: fe14 2863 vcmla.f16 q1, q2, d3\[1\], #90
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+[0-9a-f]+: fed6 58a7 vcmla.f32 d21, d22, d23\[0\], #90
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+[0-9a-f]+: fe94 2867 vcmla.f32 q1, q2, d23\[0\], #90
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@ -0,0 +1,49 @@
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.text
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A1:
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.arm
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vcadd.f32 q1,q2,q3,#90
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vcadd.f32 q1,q2,q3,#270
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vcadd.f16 d21,d22,d23,#90
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vcadd.f16 q1,q2,q3,#90
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vcadd.f32 d21,d22,d23,#90
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vcmla.f32 q1,q2,q3,#0
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vcmla.f32 q1,q2,q3,#90
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vcmla.f32 q1,q2,q3,#180
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vcmla.f32 q1,q2,q3,#270
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vcmla.f16 d21,d22,d23,#90
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vcmla.f16 q1,q2,q3,#90
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vcmla.f32 d21,d22,d23,#90
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vcmla.f16 d21,d22,d3[0],#90
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vcmla.f16 d21,d22,d3[1],#90
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vcmla.f16 q1,q2,d3[0],#90
|
||||
vcmla.f16 q1,q2,d3[1],#90
|
||||
vcmla.f32 d21,d22,d23[0],#90
|
||||
vcmla.f32 q1,q2,d23[0],#90
|
||||
|
||||
T1:
|
||||
.thumb
|
||||
|
||||
vcadd.f32 q1,q2,q3,#90
|
||||
vcadd.f32 q1,q2,q3,#270
|
||||
vcadd.f16 d21,d22,d23,#90
|
||||
vcadd.f16 q1,q2,q3,#90
|
||||
vcadd.f32 d21,d22,d23,#90
|
||||
|
||||
vcmla.f32 q1,q2,q3,#0
|
||||
vcmla.f32 q1,q2,q3,#90
|
||||
vcmla.f32 q1,q2,q3,#180
|
||||
vcmla.f32 q1,q2,q3,#270
|
||||
vcmla.f16 d21,d22,d23,#90
|
||||
vcmla.f16 q1,q2,q3,#90
|
||||
vcmla.f32 d21,d22,d23,#90
|
||||
|
||||
vcmla.f16 d21,d22,d3[0],#90
|
||||
vcmla.f16 d21,d22,d3[1],#90
|
||||
vcmla.f16 q1,q2,d3[0],#90
|
||||
vcmla.f16 q1,q2,d3[1],#90
|
||||
vcmla.f32 d21,d22,d23[0],#90
|
||||
vcmla.f32 q1,q2,d23[0],#90
|
||||
|
|
@ -1,3 +1,8 @@
|
|||
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
|
||||
(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
|
||||
|
||||
2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): Add vjcvt.
|
||||
|
|
|
|||
|
|
@ -116,6 +116,7 @@ struct opcode16
|
|||
%<bitfield>G print as an iWMMXt general purpose or control register
|
||||
%<bitfield>D print as a NEON D register
|
||||
%<bitfield>Q print as a NEON Q register
|
||||
%<bitfield>V print as a NEON D or Q register
|
||||
%<bitfield>E print a quarter-float immediate value
|
||||
|
||||
%y<code> print a single precision VFP reg.
|
||||
|
|
@ -882,6 +883,28 @@ static const struct opcode32 coprocessor_opcodes[] =
|
|||
0xfc400000, 0xfff00000,
|
||||
"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
|
||||
|
||||
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
|
||||
0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
|
||||
|
||||
/* V5 coprocessor instructions. */
|
||||
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
|
||||
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
|
||||
|
|
@ -3673,10 +3696,15 @@ print_insn_coprocessor (bfd_vma pc,
|
|||
}
|
||||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
case 'V':
|
||||
if (given & (1 << 6))
|
||||
goto Q;
|
||||
/* FALLTHROUGH */
|
||||
case 'D':
|
||||
func (stream, "d%ld", value);
|
||||
break;
|
||||
case 'Q':
|
||||
Q:
|
||||
if (value & 1)
|
||||
func (stream, "<illegal reg q%ld.5>", value >> 1);
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in New Issue