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[PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr 

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
	New instruction encodings.
	(do_mve_vadc): New encoding instruction.
	(do_mve_vbrsr): Likewise.
	(do_mve_vsbc): Likewise.
	* testsuite/gas/arm/mve-vadc-bad.d: New test.
	* testsuite/gas/arm/mve-vadc-bad.l: New test.
	* testsuite/gas/arm/mve-vadc-bad.s: New test.
	* testsuite/gas/arm/mve-vbrsr-bad.d: New test.
	* testsuite/gas/arm/mve-vbrsr-bad.l: New test.
	* testsuite/gas/arm/mve-vbrsr-bad.s: New test.
	* testsuite/gas/arm/mve-vsbc-bad.d: New test.
	* testsuite/gas/arm/mve-vsbc-bad.l: New test.
	* testsuite/gas/arm/mve-vsbc-bad.s: New test.
This commit is contained in:
Andre Vieira 2019-05-15 17:37:07 +01:00
parent 1b8833198c
commit c2dafc2a05
11 changed files with 241 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
gas/ChangeLog
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@ -1,3 +1,20 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
New instruction encodings.
(do_mve_vadc): New encoding instruction.
(do_mve_vbrsr): Likewise.
(do_mve_vsbc): Likewise.
* testsuite/gas/arm/mve-vadc-bad.d: New test.
* testsuite/gas/arm/mve-vadc-bad.l: New test.
* testsuite/gas/arm/mve-vadc-bad.s: New test.
* testsuite/gas/arm/mve-vbrsr-bad.d: New test.
* testsuite/gas/arm/mve-vbrsr-bad.l: New test.
* testsuite/gas/arm/mve-vbrsr-bad.s: New test.
* testsuite/gas/arm/mve-vsbc-bad.d: New test.
* testsuite/gas/arm/mve-vsbc-bad.l: New test.
* testsuite/gas/arm/mve-vsbc-bad.s: New test.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (MVE_BAD_QREG): New error message.

54
gas/config/tc-arm.c
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@ -14136,6 +14136,9 @@ do_t_loloop (void)
#define M_MNEM_vmovlb 0xeea00f40
#define M_MNEM_vmovnt 0xfe311e81
#define M_MNEM_vmovnb 0xfe310e81
#define M_MNEM_vadc 0xee300f00
#define M_MNEM_vadci 0xee301f00
#define M_MNEM_vbrsr 0xfe011e60
/* Neon instruction encoder helpers. */
@ -16758,6 +16761,52 @@ do_neon_qdmulh (void)
}
}
static void
do_mve_vadc (void)
{
enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
struct neon_type_el et
= neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
if (et.type == NT_invtype)
first_error (BAD_EL_TYPE);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
mve_encode_qqq (0, 64);
}
static void
do_mve_vbrsr (void)
{
enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
struct neon_type_el et
= neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
mve_encode_qqr (et.size, 0);
}
static void
do_mve_vsbc (void)
{
neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
mve_encode_qqq (1, 64);
}
static void
do_mve_vmull (void)
{
@ -23909,6 +23958,10 @@ static const struct asm_opcode insns[] =
ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
/* MVE and MVE FP only. */
mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
@ -23945,6 +23998,7 @@ static const struct asm_opcode insns[] =
mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1

5
gas/testsuite/gas/arm/mve-vadc-bad.d Normal file
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@ -0,0 +1,5 @@
#name: Bad MVE VADC instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vadc-bad.l
.*: +file format .*arm.*

31
gas/testsuite/gas/arm/mve-vadc-bad.l Normal file
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@ -0,0 +1,31 @@
[^:]*: Assembler messages:
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Error: bad type in SIMD instruction -- `vadc.i8 q0,q1,q2'
[^:]*:14: Error: bad type in SIMD instruction -- `vadc.i16 q0,q1,q2'
[^:]*:15: Error: bad type in SIMD instruction -- `vadc.i64 q0,q1,q2'
[^:]*:16: Error: bad type in SIMD instruction -- `vadc.f32 q0,q1,q2'
[^:]*:17: Error: bad type in SIMD instruction -- `vadci.i8 q0,q1,q2'
[^:]*:18: Error: bad type in SIMD instruction -- `vadci.i16 q0,q1,q2'
[^:]*:19: Error: bad type in SIMD instruction -- `vadci.i64 q0,q1,q2'
[^:]*:20: Error: bad type in SIMD instruction -- `vadci.f32 q0,q1,q2'
[^:]*:22: Error: syntax error -- `vadceq.i32 q0,q1,q2'
[^:]*:23: Error: syntax error -- `vadceq.i32 q0,q1,q2'
[^:]*:25: Error: syntax error -- `vadceq.i32 q0,q1,q2'
[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vadct.i32 q0,q1,q2'
[^:]*:28: Error: instruction missing MVE vector predication code -- `vadc.i32 q0,q1,q2'
[^:]*:30: Error: syntax error -- `vadcieq.i32 q0,q1,q2'
[^:]*:31: Error: syntax error -- `vadcieq.i32 q0,q1,q2'
[^:]*:33: Error: syntax error -- `vadcieq.i32 q0,q1,q2'
[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vadcit.i32 q0,q1,q2'
[^:]*:36: Error: instruction missing MVE vector predication code -- `vadci.i32 q0,q1,q2'

36
gas/testsuite/gas/arm/mve-vadc-bad.s Normal file
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@ -0,0 +1,36 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
.irp mnem, vadc.i32, vadci.i32
it \cond
\mnem q0, q1, q2
.endr
.endr
.endm
.syntax unified
.thumb
cond
vadc.i8 q0, q1, q2
vadc.i16 q0, q1, q2
vadc.i64 q0, q1, q2
vadc.f32 q0, q1, q2
vadci.i8 q0, q1, q2
vadci.i16 q0, q1, q2
vadci.i64 q0, q1, q2
vadci.f32 q0, q1, q2
it eq
vadceq.i32 q0, q1, q2
vadceq.i32 q0, q1, q2
vpst
vadceq.i32 q0, q1, q2
vadct.i32 q0, q1, q2
vpst
vadc.i32 q0, q1, q2
it eq
vadcieq.i32 q0, q1, q2
vadcieq.i32 q0, q1, q2
vpst
vadcieq.i32 q0, q1, q2
vadcit.i32 q0, q1, q2
vpst
vadci.i32 q0, q1, q2

5
gas/testsuite/gas/arm/mve-vbrsr-bad.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VBRSR instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vbrsr-bad.l
.*: +file format .*arm.*

14
gas/testsuite/gas/arm/mve-vbrsr-bad.l Normal file
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@ -0,0 +1,14 @@
[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Error: bad type in SIMD instruction -- `vbrsr.64 q0,q1,r2'
[^:]*:12: Error: ARM register expected -- `vbrsr.32 q0,q1,q2'
[^:]*:14: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:15: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:17: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:19: Error: instruction missing MVE vector predication code -- `vbrsr.32 q0,q1,r2'
[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vbrsrt.32 q0,q1,r2'

20
gas/testsuite/gas/arm/mve-vbrsr-bad.s Normal file
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@ -0,0 +1,20 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vbrsr.16 q0, q1, r2
.endr
.endm
.syntax unified
.thumb
cond
vbrsr.64 q0, q1, r2
vbrsr.32 q0, q1, q2
it eq
vbrsreq.32 q0, q1, r2
vbrsreq.32 q0, q1, r2
vpst
vbrsreq.32 q0, q1, r2
vpst
vbrsr.32 q0, q1, r2
vbrsrt.32 q0, q1, r2

5
gas/testsuite/gas/arm/mve-vsbc-bad.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VSBC instructions
#as: -march=armv8.1-m.main+mve
#error_output: mve-vsbc-bad.l
.*: +file format .*arm.*

25
gas/testsuite/gas/arm/mve-vsbc-bad.l Normal file
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@ -0,0 +1,25 @@
[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vsbc.i16 q0,q1,q2'
[^:]*:11: Error: bad type in SIMD instruction -- `vsbci.i16 q0,q1,q2'
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
[^:]*:16: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
[^:]*:18: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
[^:]*:20: Error: instruction missing MVE vector predication code -- `vsbc.i32 q0,q1,q2'
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vsbct.i32 q0,q1,q2'
[^:]*:23: Error: syntax error -- `vsbcieq.i32 q0,q1,q2'
[^:]*:24: Error: syntax error -- `vsbcieq.i32 q0,q1,q2'
[^:]*:26: Error: syntax error -- `vsbcieq.i32 q0,q1,q2'
[^:]*:28: Error: instruction missing MVE vector predication code -- `vsbci.i32 q0,q1,q2'
[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vsbcit.i32 q0,q1,q2'

29
gas/testsuite/gas/arm/mve-vsbc-bad.s Normal file
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@ -0,0 +1,29 @@
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().i32 q0, q1, q2
.endr
.endm
.syntax unified
.thumb
vsbc.i16 q0, q1, q2
vsbci.i16 q0, q1, q2
cond vsbc
cond vsbci
it eq
vsbceq.i32 q0, q1, q2
vsbceq.i32 q0, q1, q2
vpst
vsbceq.i32 q0, q1, q2
vpst
vsbc.i32 q0, q1, q2
vsbct.i32 q0, q1, q2
it eq
vsbcieq.i32 q0, q1, q2
vsbcieq.i32 q0, q1, q2
vpst
vsbcieq.i32 q0, q1, q2
vpst
vsbci.i32 q0, q1, q2
vsbcit.i32 q0, q1, q2